ECE Digital System Design & Synthesis Exercise 1 - Logic Values, Data Types & Operators - With Answers

Size: px
Start display at page:

Download "ECE Digital System Design & Synthesis Exercise 1 - Logic Values, Data Types & Operators - With Answers"

Transcription

1 ECE Digital System Design & Synthesis Exercise 1 - Logic Values, Data Types & Operators - With Answers Fall 2001 Final Version (Important changes from original posted Exercise 1 shown in color) Variables In Verilog, what are nets used for? A: For structural connectivity What are registers used for in Verilog? A: As an abstraction of storage (May or may not be real physical storage) What is the generic name for both nets and registers? A: Signals What is a single bit net called? A: A scalar net What is a multiple bit register called? A: A vector register Logic Values Give the four basic Verilog signal values and their meanings A: 0 - Logical 0 or FALSE A: 1 - Logical 1 or TRUE A: x, X - Unknown logic value A: z, Z - High impedance condition Give the number of driving strengths used for switch level modeling of MOS devices in Verilog: A: 4 each for 0 and 1 net values and 2 for HiZ values for a total of 10. Give the number of charge strengths used for switch level modeling of MOS devices in Verilog: A: 3 each for 0 and 1 net values for a total of 6. Thus there are 16 total strength values. Data Type - Nets Give the two methods for explicitly assigning a value to a net. A: Continuous assignment A: force release procedural continuous assignment Give the two methods for implicitly assigning a value to a net. A: By being connected to an output terminal of a primitive A: By being connected to an output port of a module Net Semantics Give the meaning of each of the following net types; indicate whether there can be just a single driver or multiple drivers. wire A: Single driver, connectivity only; no logical 1

2 tri A: Multiple drivers, same as wire, but 3-stated in hardware wand A: Multiple drivers - wired and wor A: Multiple drivers - wired or triand A: Multiple drivers, same as wand, but 3-state in hardware trior A: Multiple drivers, same as wor but 3-state in hardware supply 0 A: Global net for GND supply 1 A: Global Net for VCC (VDD) Net Declaration Syntax Explain the difference between a net declared as vectored and a net declared as scalared. A: vectored Multiple-bit net treated as a single object - cannot reference individual bits or part-select A: scalared - Bits can be referenced individually and as parts What is the default for a net, vectored or scalared? A: scalared Net Examples - Single Driver Describe fully the net(s) declared by each of the following net declarations. wire x; A: 1-bit wire x; wire x, y; A: 1-bit wires x and y. wire [15:0] data, address; A: 16-bit wires data and address with MSB 15 and LSB 0. wire vectored [0:7] control; A: 8-bit wire control with MSB 0 and LSB 7 that can be instantiated only as all 8 bits. data[15] (instantiation) A: Use of bit 15 of data address[15:8] (instantiation) A: Use of bits 15 down through 8 of address wire [15:0] address = offset + index; A: Declaration of 16-bit wire address with MSB 15 and LSB 0 and continuous assignment = offset + index Net Examples - Multiple Drivers 2

3 Describe in detail the net(s) declared by each of the following net declarations. wor interrupt_1, interrupt_2; A: Two 1-bit wired or nets called interrupt_1 and interrupt_2 tri [31:0] data_bus, operand_bus; A: Two 32-bit three-state nets called data_bus and operand_bus with MSB 31 and LSB 0 supply0 [31:0] GND; A: 32-bit GND net with MSB 31 and LSB 0 supply1 [23:0] VDD; A: 24-bit VDD net with MSB 23 and LSB 0 Initial Value & Undeclared Nets What is the default initial value of a net at t sim = 0? A: The initial value is x. What is the default type for a net that is not declared? A: Defaults to type wire How can the default type for a net that is not declared be changed? A: By a default_nettype compiler directive Data Type Register Register Semantics Give the function that each of the following register types performs. reg A: Stores a logic value integer A: Supports computation time A: Stores time 64-bit unsigned real A: Stores values as real numbers realtime A: Stores time values as real numbers Register Assignment List four Verilog constructs within which a register can be assigned. A: a procedural statement A: a user-defined sequential primitive A: a task, or A: a function. List two Verilog constructs by which a register can never be assigned. A: a primitive gate output or A: a continuous assignment 3

4 Register Examples Describe the register(s) declared by each of the following register declarations; give the number of bits in all cases. reg a, b, c; A: Three 1- bit register: a, b, and c reg [15:0] counter, shift_reg; A: Two 16-bit registers with MSB 15 down to LSB 0: counter and shift integer sum, difference; A: Two integer registers named sum and difference of length wordlength of machine, but at least 32 bits Strings What is the data type for a string? A: A string has no explicit data type A string must be stored in reg (or array). Describe a register with identifier buffer for storing a string of 32 8-bit characters. A: reg [255:0] buffer; Constants Declaration of parameters A sequential circuit has three states A, B, and C with state codes 00, 01, and 10, respectively. Write a parameter statement assigning these codes to their respective states. A: parameter A = 2 b00, B = 2 b01, C = 2 b10; The following gives a parameter regsize and its instantiation. If n = 8, how many bits are in reg R and how are they numbered? parameter regsize = n; reg R[0: n - 1]; A: 8-bit register with MSB 0 and LSB 7. Operators 4

5 Give the function that each of the operators listed performs: Arithmetic (binary) + A: addition (2 s complement modulo 2 n ) - A: subtraction (2 s complement modulo 2 n ) * A: multiplication / A: division % A: modulus (remainder of first operand divided by second operand) Arithmetic (unary) + A: positive sign (if x or z in operand, result is all x) - A: negative sign (if x or z in operand, result is all x) Bitwise ~ A: bitwise not & A: bitwise and A: bitwise or ^ A: bitwise exclusive or ~^ or ^~ A: bitwise exclusive nor Reduction & A: and of all bits in operand ~& A: nand of all bits in operand A: or of all bits in operand ~ A: nor of all bits in operand ^ A: exclusive or of all bits in operand ~^ or ^~ A: exclusive nor of all bits in operand Logical! A: Logical not && A: Logical and A: Logical or = = A: Logical equality (A = B with result unknown if x or z present)!= A: Logical inequality (A not = B with result unknown if x or z present) = = = A: Case equality I( A = B with exact match including x and z values)! = = A: Case inequality (A not = B with any mismatch including x and z values) Relational < A: Less than >= A: Greater than or equal to > A: Greater than <= A: Less than or equal to Shift >> A: Right shift with 0 fill (of left operand shifted by the number of bits given by the right operand) 5

6 << A: Left shift with 0 fill (of left operand shifted by the number of bits given by the right operand) Conditional? : A: (If operand 1, then operand 2, else operand 3) Concatenation and Replications {,} A: Concatenate operands given {int{ }}A: Form vector which is replication of operand int times Expression Bit Widths Depends on: widths of operands and types of operators Verilog fills in smaller-width operands by using zero extension. Final or intermediate result width may increase expression width Width (Unsized constant number) = same as integer (usually 32) Width (Sized constant number) = number of bits specified. Arithmetic binary and bitwise x op y where op is +, -, *, /, %, &,, ^, ^~: Bit width = max (width(x), width(y)) What is the width of A + B for reg[7:0] A; reg[15:0] B;? A: 16 Will the assignment statement assign result = (A+B) >> 1; work properly for all possible pairs of 16-bit operands for reg[15:0] A, B;? A: No, lose overflow Arithmetic unary op x where op is +, - Bit width = width(x) Bitwise negation op x where op is ~ Bit width = width(x) Logical, relational and reduction x op y where op is = =,!=, = = =,!= =, &&,, >, >=, <, <= or op y where op is!, &,, ^, ~&, ~, ~^ Bit width = 1 What is the bit width of (X && (A + B)) for wire X; wire [7:0] A, B;? A: 1 Shift x op y where op is <<, >> Bit width = width(x) Conditional x? y : z 6

7 Bit width = max(width(y), width(z)) What is the bit width of assign result = X? A:B; for wire X; reg[9:0] A; reg[18:10] B; A: 10 Concatenation {x,, y} Bit width = width(x) + + width(y) What is the bit width of {A, B, C} for wire A; reg[7:0] B; reg [15:0] C;? A: 25 Replication {x{y,, z}} Bit width = x * (width(y) + + width(z)) Expressions with Operands Containing x or z Arithmetic If any bit is x or z, result is all x s. Divide by 0 produces all x s. What is the result of assign result = A + B; for A = 4'b1100; B = 2'b11? A: 1111 What is the result of assign result = A + B; for A = 4'b1100; B = 4'bx11? A: xxxx Relational If any bit is x or z, result is x. Logical = = and!= If any bit is x or z, result is x. If lengths of operands are unequal, 0-fill shortest one on left. = = = and!= = All bits including x and z values must match for equality; otherwise unequal. If lengths of operands are unequal, 0-fill shortest one on left. What is the value of (4'b0011) = = (2'b11)? A: 1 Can (4'b0011) = = = (2'b11)? be evaluated? Explain your answer. A: Yes. 0-fill is used as well here; operands as given do not need to be equal length. &&, combines logical values 0,1, x. Multiple bit operands map to single bit as follows: If contains a 1 anywhere, maps to 1. If all 0 s, maps to 0. Otherwise, maps to x. Bitwise Defined by tables for 0, 1, x, z operands. Reduction Defined by tables as for bitwise operators. Shifts z changed to x. Vacated positions zero filled. 7

8 Conditional If conditional expression is ambiguous (e.g., x or z), both expressions are evaluated and bitwise combined as follows: f(1,1) = 1, f(0,0) = 0, otherwise x. What is the value of result in assign result = (2'b1x)? 4'b0011: 4'b0101; A: Since 2'b1x contains a 1, it is known to be non-zero, so is mapped to a 1 (true) giving result = 4'b0011. Suppose that 1'bx replaces 2'b1x. 1'bx maps to x, giving, by the rules shown, result = 4'b0xx1. The rules given correspond to the behavior of a multiplexer implementing the conditional (If both data values are equal to 1, the output is 1 regardless of the select value. Likewise, for both data values equal to 0. If the data values are opposite, then the output is unknown for an unknown value on the select input. 8

Verilog HDL Introduction

Verilog HDL Introduction EEE3050 Theory on Computer Architectures (Spring 2017) Prof. Jinkyu Jeong Verilog HDL Introduction 2017.05.14 TA 이규선 (GYUSUN LEE) / 안민우 (MINWOO AHN) Modules The Module Concept Basic design unit Modules

More information

ECEN 468 Advanced Logic Design

ECEN 468 Advanced Logic Design ECEN 468 Advanced Logic Design Lecture 26: Verilog Operators ECEN 468 Lecture 26 Operators Operator Number of Operands Result Arithmetic 2 Binary word Bitwise 2 Binary word Reduction 1 Bit Logical 2 Boolean

More information

14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages

14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages 14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #22: Introduction to Verilog Hardware Description Languages Basic idea: Language constructs

More information

Chapter 3: Dataflow Modeling

Chapter 3: Dataflow Modeling Chapter 3: Dataflow Modeling Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 3-1 Objectives After completing this chapter, you will be able to: Describe

More information

Introduction to Digital VLSI Design מבוא לתכנון VLSI ספרתי

Introduction to Digital VLSI Design מבוא לתכנון VLSI ספרתי Design מבוא לתכנון VLSI ספרתי Verilog Dataflow Modeling Lecturer: Semester B, EE Dept. BGU. Freescale Semiconductors Israel 9/3/7 Objectives Describe the continuous assignment ( assign ) statement, restrictions

More information

Verilog Dataflow Modeling

Verilog Dataflow Modeling Verilog Dataflow Modeling Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Source:

More information

Chap 6 - Introduction to HDL (b)

Chap 6 - Introduction to HDL (b) Design with Verilog Chap 6 - Introduction to HDL (b) Credit to: MD Rizal Othman Faculty of Electrical & Electronics Engineering Universiti Malaysia Pahang Ext: 6036 Language Elements 1. Operators There

More information

Arithmetic Operators There are two types of operators: binary and unary Binary operators:

Arithmetic Operators There are two types of operators: binary and unary Binary operators: Verilog operators operate on several data types to produce an output Not all Verilog operators are synthesible (can produce gates) Some operators are similar to those in the C language Remember, you are

More information

ECE 4514 Digital Design II. Spring Lecture 7: Dataflow Modeling

ECE 4514 Digital Design II. Spring Lecture 7: Dataflow Modeling ECE 4514 Digital Design II Lecture 7: Dataflow Modeling A language Lecture Today's topic Dataflow Modeling input input input module output output Model with submodules and gates = Structural Model with

More information

Course Topics - Outline

Course Topics - Outline Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 Behavioral modeling B Lecture 7

More information

Lecture 2: Data Types, Modeling Combinational Logic in Verilog HDL. Variables and Logic Value Set. Data Types. Why use an HDL?

Lecture 2: Data Types, Modeling Combinational Logic in Verilog HDL. Variables and Logic Value Set. Data Types. Why use an HDL? Why use an HDL? Lecture 2: Data Types, Modeling Combinational Logic in Verilog HDL Increase digital design engineer s productivity (from Dataquest) Behavioral HDL RTL HDL Gates Transistors 2K 10K gates/week

More information

Verilog Language Concepts

Verilog Language Concepts Verilog Language Concepts Adapted from Z. Navabi Portions Copyright Z. Navabi, 2006 1 Verilog Language Concepts Characterizing Hardware Languages Timing Concurrency Timing and concurrency example Module

More information

Verilog Design Principles

Verilog Design Principles 16 h7fex // 16-bit value, low order 4 bits unknown 8 bxx001100 // 8-bit value, most significant 2 bits unknown. 8 hzz // 8-bit value, all bits high impedance. Verilog Design Principles ECGR2181 Extra Notes

More information

Contents. Appendix D Verilog Summary Page 1 of 16

Contents. Appendix D Verilog Summary Page 1 of 16 Appix D Verilog Summary Page 1 of 16 Contents Appix D Verilog Summary... 2 D.1 Basic Language Elements... 2 D.1.1 Keywords... 2 D.1.2 Comments... 2 D.1.3 Identifiers... 2 D.1.4 Numbers and Strings... 3

More information

Verilog Design Principles

Verilog Design Principles 16 h7fex // 16-bit value, low order 4 bits unknown 8 bxx001100 // 8-bit value, most significant 2 bits unknown. 8 hzz // 8-bit value, all bits high impedance. Verilog Design Principles ECGR2181 Extra Notes

More information

Verilog HDL. A Guide to Digital Design and Synthesis. Samir Palnitkar. SunSoft Press A Prentice Hall Title

Verilog HDL. A Guide to Digital Design and Synthesis. Samir Palnitkar. SunSoft Press A Prentice Hall Title Verilog HDL A Guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press A Prentice Hall Title Table of Contents About the Author Foreword Preface Acknowledgments v xxxi xxxiii xxxvii Part 1:

More information

Schematic design. Gate level design. 0 EDA (Electronic Design Assistance) 0 Classical design. 0 Computer based language

Schematic design. Gate level design. 0 EDA (Electronic Design Assistance) 0 Classical design. 0 Computer based language 1 / 15 2014/11/20 0 EDA (Electronic Design Assistance) 0 Computer based language 0 HDL (Hardware Description Language) 0 Verilog HDL 0 Created by Gateway Design Automation Corp. in 1983 First modern hardware

More information

Course Topics - Outline

Course Topics - Outline Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 Behavioral modeling B Lecture 7

More information

Department of Computer Science and Electrical Engineering. Intro to Verilog II

Department of Computer Science and Electrical Engineering. Intro to Verilog II Department of Computer Science and Electrical Engineering Intro to Verilog II http://6004.csail.mit.edu/6.371/handouts/l0{2,3,4}.pdf http://www.asic-world.com/verilog/ http://www.verilogtutorial.info/

More information

Introduction to Verilog. Garrison W. Greenwood, Ph.D, P.E.

Introduction to Verilog. Garrison W. Greenwood, Ph.D, P.E. Introduction to Verilog Garrison W. Greenwood, Ph.D, P.E. November 11, 2002 1 Digital Design Flow Specification Functional Design Register Transfer Level Design Circuit Design Physical Layout Production

More information

Combinational Logic II

Combinational Logic II Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic

More information

In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified.

In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified. 1 In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified. I will also introduce the idea of a testbench as part of a design specification.

More information

VERILOG 2: LANGUAGE BASICS

VERILOG 2: LANGUAGE BASICS VERILOG 2: LANGUAGE BASICS Verilog module Modules are basic building blocks. These are two example module definitions which you should use: // Safer traditional method module abc (in1, in2, out); input

More information

Verilog HDL:Digital Design and Modeling. Chapter 4. Expressions

Verilog HDL:Digital Design and Modeling. Chapter 4. Expressions Chapter 4 Expressions 1 Verilog HDL:Digital Design and Modeling Chapter 4 Expressions Chapter 4 Expressions 2 Page 120 //example of using a parameter module param1 (a, b, cin, sum); parameter width = 8;

More information

Programmable Logic Devices Verilog VII CMPE 415

Programmable Logic Devices Verilog VII CMPE 415 Synthesis of Combinational Logic In theory, synthesis tools automatically create an optimal gate-level realization of a design from a high level HDL description. In reality, the results depend on the skill

More information

register:a group of binary cells suitable for holding binary information flip-flops + gates

register:a group of binary cells suitable for holding binary information flip-flops + gates 9 차시 1 Ch. 6 Registers and Counters 6.1 Registers register:a group of binary cells suitable for holding binary information flip-flops + gates control when and how new information is transferred into the

More information

Basic operators, Arithmetic, Relational, Bitwise, Logical, Assignment, Conditional operators. JAVA Standard Edition

Basic operators, Arithmetic, Relational, Bitwise, Logical, Assignment, Conditional operators. JAVA Standard Edition Basic operators, Arithmetic, Relational, Bitwise, Logical, Assignment, Conditional operators JAVA Standard Edition Java - Basic Operators Java provides a rich set of operators to manipulate variables.

More information

Under-Graduate Project Logic Design with Behavioral Models

Under-Graduate Project Logic Design with Behavioral Models 97-1 1 Under-Graduate Project Logic Design with Behavioral Models Speaker: 吳佳謙 Adviser: Prof. An-Yeu Wu Date: 2008/10/20 ACCESS IC LAB Operation Assignment Outline Blocking and non-blocking Appendix pp.

More information

Lecture #2: Verilog HDL

Lecture #2: Verilog HDL Lecture #2: Verilog HDL Paul Hartke Phartke@stanford.edu Stanford EE183 April 8, 2002 EE183 Design Process Understand problem and generate block diagram of solution Code block diagram in verilog HDL Synthesize

More information

Lab 4: Arithmetic Logic Unit (ALU)

Lab 4: Arithmetic Logic Unit (ALU) EE 231-1 - Fall 2016 Lab 4: Arithmetic Logic Unit (ALU) Introduction The heart of every computer is an Arithmetic Logic Unit (ALU). This is the part of the computer which performs arithmetic operations

More information

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26)

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26) Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: continued 1 Announcements Consulting hours Introduction to Sim Milestone #1 (due 1/26) 2 1 Overview: Integer Operations Internal representation

More information

Verilog. Reminder: Lab #1 due tonight! Fall 2008 Lecture 3

Verilog. Reminder: Lab #1 due tonight! Fall 2008 Lecture 3 Verilog Hardware Description Languages Verilog -- structural: modules, instances -- dataflow: continuous assignment -- sequential behavior: always blocks -- pitfalls -- other useful features Reminder:

More information

Online Verilog Resources

Online Verilog Resources EECS 427 Discussion 6: Verilog HDL Reading: Many references EECS 427 F08 Discussion 6 1 Online Verilog Resources ASICs the book, Ch. 11: http://www.ge.infn.it/~pratolo/verilog/verilogtutorial.pdf it/ pratolo/verilog/verilogtutorial

More information

Verilog for Combinational Circuits

Verilog for Combinational Circuits Verilog for Combinational Circuits Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2014 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/

More information

Spiral 1 / Unit 4 Verilog HDL. Digital Circuit Design Steps. Digital Circuit Design OVERVIEW. Mark Redekopp. Description. Verification.

Spiral 1 / Unit 4 Verilog HDL. Digital Circuit Design Steps. Digital Circuit Design OVERVIEW. Mark Redekopp. Description. Verification. 1-4.1 1-4.2 Spiral 1 / Unit 4 Verilog HDL Mark Redekopp OVERVIEW 1-4.3 1-4.4 Digital Circuit Design Steps Digital Circuit Design Description Design and computer-entry of circuit Verification Input Stimulus

More information

Design Using Verilog

Design Using Verilog EGC220 Design Using Verilog Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Basic Verilog Lexical Convention Lexical convention are close to C++. Comment // to the of the line. /* to

More information

Synthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis

Synthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis Synthesis of Language Constructs 1 Nets Nets declared to be input or output ports are retained Internal nets may be eliminated due to logic optimization User may force a net to exist trireg, tri0, tri1

More information

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation A Verilog Primer An Overview of Verilog for Digital Design and Simulation John Wright Vighnesh Iyer Department of Electrical Engineering and Computer Sciences College of Engineering, University of California,

More information

Introduction. Following are the types of operators: Unary requires a single operand Binary requires two operands Ternary requires three operands

Introduction. Following are the types of operators: Unary requires a single operand Binary requires two operands Ternary requires three operands Introduction Operators are the symbols which operates on value or a variable. It tells the compiler to perform certain mathematical or logical manipulations. Can be of following categories: Unary requires

More information

Lab 5: Arithmetic Logic Unit (ALU)

Lab 5: Arithmetic Logic Unit (ALU) Lab 5: Arithmetic Logic Unit (ALU) September 29, 2009 Contents 1 Prelab 4 2 Lab 4 3 Supplementary Material 6 3.1 Verilog................................................. 6 3.1.1 Parameters..........................................

More information

IT T35 Digital system desigm y - ii /s - iii

IT T35 Digital system desigm y - ii /s - iii UNIT - V Introduction to Verilog Hardware Description Language Introduction HDL for combinational circuits Sequential circuits Registers and counters HDL description for binary multiplier. 5.1 INTRODUCTION

More information

Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23

Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23 98-1 Under-Graduate Project Synthesis of Combinational Logic Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23 What is synthesis? Outline Behavior Description for Synthesis Write Efficient HDL

More information

Extending SystemVerilog Data Types to Nets

Extending SystemVerilog Data Types to Nets Extending SystemVerilog Data Types to Nets SystemVerilog extended Verilog by adding powerful new data types and operators that can be used to declare and manipulate parameters and variables. Extensions

More information

Informatics Ingeniería en Electrónica y Automática Industrial

Informatics Ingeniería en Electrónica y Automática Industrial Informatics Ingeniería en Electrónica y Automática Industrial Operators and expressions in C Operators and expressions in C Numerical expressions and operators Arithmetical operators Relational and logical

More information

Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog

Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog Verilog Radek Pelánek and Šimon Řeřucha Contents 1 Computer Aided Design 2 Basic Syntax 3 Gate Level Modeling 4 Behavioral Modeling Computer Aided Design Hardware Description Languages (HDL) Verilog C

More information

Digital Design with FPGAs. By Neeraj Kulkarni

Digital Design with FPGAs. By Neeraj Kulkarni Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic

More information

Introduction To Verilog Design. Chun-Hung Chou

Introduction To Verilog Design. Chun-Hung Chou Introduction To Verilog Design Chun-Hung Chou 1 Outline Typical Design Flow Design Method Lexical Convention Data Type Data Assignment Event Control Conditional Description Register Description Synthesizable

More information

Arithmetic Operations

Arithmetic Operations Arithmetic Operations Arithmetic Operations addition subtraction multiplication division Each of these operations on the integer representations: unsigned two's complement 1 Addition One bit of binary

More information

Operators & Expressions

Operators & Expressions Operators & Expressions Operator An operator is a symbol used to indicate a specific operation on variables in a program. Example : symbol + is an add operator that adds two data items called operands.

More information

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE 1 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output

More information

Register Transfer Level in Verilog: Part I

Register Transfer Level in Verilog: Part I Source: M. Morris Mano and Michael D. Ciletti, Digital Design, 4rd Edition, 2007, Prentice Hall. Register Transfer Level in Verilog: Part I Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National

More information

GO - OPERATORS. This tutorial will explain the arithmetic, relational, logical, bitwise, assignment and other operators one by one.

GO - OPERATORS. This tutorial will explain the arithmetic, relational, logical, bitwise, assignment and other operators one by one. http://www.tutorialspoint.com/go/go_operators.htm GO - OPERATORS Copyright tutorialspoint.com An operator is a symbol that tells the compiler to perform specific mathematical or logical manipulations.

More information

Lecture 3: Modeling in VHDL. EE 3610 Digital Systems

Lecture 3: Modeling in VHDL. EE 3610 Digital Systems EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware

More information

N-input EX-NOR gate. N-output inverter. N-input NOR gate

N-input EX-NOR gate. N-output inverter. N-input NOR gate Hardware Description Language HDL Introduction HDL is a hardware description language used to design and document electronic systems. HDL allows designers to design at various levels of abstraction. It

More information

Introduction to VHDL #1

Introduction to VHDL #1 ECE 3220 Digital Design with VHDL Introduction to VHDL #1 Lecture 3 Introduction to VHDL The two Hardware Description Languages that are most often used in industry are: n VHDL n Verilog you will learn

More information

Chapter 3: Operators, Expressions and Type Conversion

Chapter 3: Operators, Expressions and Type Conversion 101 Chapter 3 Operators, Expressions and Type Conversion Chapter 3: Operators, Expressions and Type Conversion Objectives To use basic arithmetic operators. To use increment and decrement operators. To

More information

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign I hope you have completed Part 1 of the Experiment. This lecture leads you to Part 2 of the experiment and hopefully helps you with your progress to Part 2. It covers a number of topics: 1. How do we specify

More information

Introduction to Verilog/System Verilog

Introduction to Verilog/System Verilog NTUEE DCLAB Feb. 27, 2018 Introduction to Verilog/System Verilog Presenter: Yao-Pin Wang 王耀斌 Advisor: Prof. Chia-Hsiang Yang 楊家驤 Dept. of Electrical Engineering, NTU National Taiwan University What is

More information

CSE140L: Components and Design Techniques for Digital Systems Lab

CSE140L: Components and Design Techniques for Digital Systems Lab CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Announcements & Outline Lab 4 due; demo signup times listed on the cse140l site Check

More information

Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1

Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis Spring 2007 Lec #8 -- HW Synthesis 1 Logic Synthesis Verilog and VHDL started out

More information

Hardware Description Language (HDL)

Hardware Description Language (HDL) Hardware Description Language (HDL) What is the need for Hardware Description Language? Model, Represent, And Simulate Digital Hardware Hardware Concurrency Parallel Activity Flow Semantics for Signal

More information

Programming in C++ 5. Integral data types

Programming in C++ 5. Integral data types Programming in C++ 5. Integral data types! Introduction! Type int! Integer multiplication & division! Increment & decrement operators! Associativity & precedence of operators! Some common operators! Long

More information

Expression and Operator

Expression and Operator Expression and Operator Examples: Two types: Expressions and Operators 3 + 5; x; x=0; x=x+1; printf("%d",x); Function calls The expressions formed by data and operators An expression in C usually has a

More information

CSE140L: Components and Design

CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Grade distribution: 70% Labs 35% Lab 4 30% Lab 3 20% Lab 2 15% Lab 1 30% Final exam

More information

LAB K Basic Verilog Programming

LAB K Basic Verilog Programming LAB K Basic Verilog Programming Perform the following groups of tasks: LabK1.v 1. Create a directory to hold the files of this lab. 2. Launch your favourite editor and a command-prompt console; you will

More information

EEL 4783: HDL in Digital System Design

EEL 4783: HDL in Digital System Design EEL 4783: HDL in Digital System Design Lecture 15: Logic Synthesis with Verilog Prof. Mingjie Lin 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for

More information

Hardware description language (HDL)

Hardware description language (HDL) Hardware description language (HDL) A hardware description language (HDL) is a computer-based language that describes the hardware of digital systems in a textual form. It resembles an ordinary computer

More information

Verilog. Verilog for Synthesis

Verilog. Verilog for Synthesis Verilog Verilog for Synthesis 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog enhanced version Verilog-XL 1987: Verilog-XL becoming more popular

More information

Spring 2017 EE 3613: Computer Organization Chapter 5: Processor: Datapath & Control - 2 Verilog Tutorial

Spring 2017 EE 3613: Computer Organization Chapter 5: Processor: Datapath & Control - 2 Verilog Tutorial Spring 2017 EE 3613: Computer Organization Chapter 5: Processor: Datapath & Control - 2 Verilog Tutorial Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio

More information

Chapter 2 Using Hardware Description Language Verilog. Overview

Chapter 2 Using Hardware Description Language Verilog. Overview Chapter 2 Using Hardware Description Language Verilog CSE4210 Winter 2012 Mokhtar Aboelaze based on slides by Dr. Shoab A. Khan Overview Algorithm development isa usually done in MATLAB, C, or C++ Code

More information

EE292: Fundamentals of ECE

EE292: Fundamentals of ECE EE292: Fundamentals of ECE Fall 2012 TTh 10:00-11:15 SEB 1242 Lecture 22 121115 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Review Binary Number Representation Binary Arithmetic Combinatorial Logic

More information

CT 229. Java Syntax 26/09/2006 CT229

CT 229. Java Syntax 26/09/2006 CT229 CT 229 Java Syntax 26/09/2006 CT229 Lab Assignments Assignment Due Date: Oct 1 st Before submission make sure that the name of each.java file matches the name given in the assignment sheet!!!! Remember:

More information

CSE241 VLSI Digital Circuits Winter Recitation 1: RTL Coding in Verilog

CSE241 VLSI Digital Circuits Winter Recitation 1: RTL Coding in Verilog CSE241 VLSI Digital Circuits Winter 2003 Recitation 1: RTL Coding in Verilog CSE241 R1 Verilog.1 Kahng & Cichy, UCSD 2003 Topic Outline Introduction Verilog Background Connections Modules Procedures Structural

More information

Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design

Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two major languages Verilog (IEEE 1364), latest version is

More information

VHDL Structural Modeling II

VHDL Structural Modeling II VHDL Structural Modeling II ECE-331, Digital Design Prof. Hintz Electrical and Computer Engineering 5/7/2001 331_13 1 Ports and Their Usage Port Modes in reads a signal out writes a signal inout reads

More information

Combinational Logic. Prof. Wangrok Oh. Dept. of Information Communications Eng. Chungnam National University. Prof. Wangrok Oh(CNU) 1 / 93

Combinational Logic. Prof. Wangrok Oh. Dept. of Information Communications Eng. Chungnam National University. Prof. Wangrok Oh(CNU) 1 / 93 Combinational Logic Prof. Wangrok Oh Dept. of Information Communications Eng. Chungnam National University Prof. Wangrok Oh(CNU) / 93 Overview Introduction 2 Combinational Circuits 3 Analysis Procedure

More information

EN2911X: Reconfigurable Computing Lecture 05: Verilog (2)

EN2911X: Reconfigurable Computing Lecture 05: Verilog (2) EN2911X: Lecture 05: Verilog (2) Prof. Sherief Reda Division of Engineering, Brown University Fall 09 http://scale.engin.brown.edu Dataflow modeling Module is designed by specifying the data flow, where

More information

Logic Synthesis. EECS150 - Digital Design Lecture 6 - Synthesis

Logic Synthesis. EECS150 - Digital Design Lecture 6 - Synthesis Logic Synthesis Verilog and VHDL started out as simulation languages, but quickly people wrote programs to automatically convert Verilog code into low-level circuit descriptions (netlists). EECS150 - Digital

More information

Hardware description languages

Hardware description languages Specifying digital circuits Schematics (what we ve done so far) Structural description Describe circuit as interconnected elements Build complex circuits using hierarchy Large circuits are unreadable Hardware

More information

Brief Introduction to Verilog HDL (Part 1)

Brief Introduction to Verilog HDL (Part 1) BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS FACULTY OF ELECTRICAL ENGINEERING AND INFORMATICS DEPARTMENT OF MEASUREMENT AND INFORMATION SYSTEMS Brief Introduction to Verilog HDL (Part 1) Tamás Raikovich

More information

Arithmetic Operators. Portability: Printing Numbers

Arithmetic Operators. Portability: Printing Numbers Arithmetic Operators Normal binary arithmetic operators: + - * / Modulus or remainder operator: % x%y is the remainder when x is divided by y well defined only when x > 0 and y > 0 Unary operators: - +

More information

SECTION II: LANGUAGE BASICS

SECTION II: LANGUAGE BASICS Chapter 5 SECTION II: LANGUAGE BASICS Operators Chapter 04: Basic Fundamentals demonstrated declaring and initializing variables. This chapter depicts how to do something with them, using operators. Operators

More information

ME 461 C review Session Fall 2009 S. Keres

ME 461 C review Session Fall 2009 S. Keres ME 461 C review Session Fall 2009 S. Keres DISCLAIMER: These notes are in no way intended to be a complete reference for the C programming material you will need for the class. They are intended to help

More information

EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references. EECS 427 W07 Lecture 14 1

EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references. EECS 427 W07 Lecture 14 1 EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references EECS 427 W07 Lecture 14 1 Online Verilog Resources ASICs the book, Ch. 11: http://www.ge.infn.it/~pratolo/verilog/verilogtutorial.pdf

More information

This Lecture. Some components (useful for the homework) Verilog HDL (will continue next lecture)

This Lecture. Some components (useful for the homework) Verilog HDL (will continue next lecture) Last Lecture The basic component of a digital circuit is the MOS transistor Transistor have instrinsic resistance and capacitance, so voltage values in the circuit take some time to change ( delay ) There

More information

2.1. Unit 2. Integer Operations (Arithmetic, Overflow, Bitwise Logic, Shifting)

2.1. Unit 2. Integer Operations (Arithmetic, Overflow, Bitwise Logic, Shifting) 2.1 Unit 2 Integer Operations (Arithmetic, Overflow, Bitwise Logic, Shifting) 2.2 Skills & Outcomes You should know and be able to apply the following skills with confidence Perform addition & subtraction

More information

UNIT V: SPECIFICATION USING VERILOG HDL

UNIT V: SPECIFICATION USING VERILOG HDL UNIT V: SPECIFICATION USING VERILOG HDL PART -A (2 Marks) 1. What are identifiers? Identifiers are names of modules, variables and other objects that we can reference in the design. Identifiers consists

More information

P-1/74. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU.

P-1/74. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU. : P-1/74 Textbook: Verilog HDL 2 nd. Edition Samir Palnitkar Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter 3 P-2/74 Chapter 3 Basic Concepts Outline of Chapter

More information

structure syntax different levels of abstraction

structure syntax different levels of abstraction This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital

More information

Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this

Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital

More information

Verilog Tutorial. Introduction. T. A.: Hsueh-Yi Lin. 2008/3/12 VLSI Digital Signal Processing 2

Verilog Tutorial. Introduction. T. A.: Hsueh-Yi Lin. 2008/3/12 VLSI Digital Signal Processing 2 Verilog Tutorial T. A.: Hsueh-Yi Lin Introduction 2008/3/12 VLSI Digital Signal Processing 2 Verilog: A common language for industry HDL is a common way for hardware design Verilog VHDL Verilog is widely

More information

EECS150 - Digital Design Lecture 10 Logic Synthesis

EECS150 - Digital Design Lecture 10 Logic Synthesis EECS150 - Digital Design Lecture 10 Logic Synthesis September 26, 2002 John Wawrzynek Fall 2002 EECS150 Lec10-synthesis Page 1 Logic Synthesis Verilog and VHDL stated out as simulation languages, but quickly

More information

Lecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1

Lecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1 Lecture 1: VHDL Quick Start Digital Systems Design Fall 10, Dec 17 Lecture 1 1 Objective Quick introduction to VHDL basic language concepts basic design methodology Use The Student s Guide to VHDL or The

More information

Figure RTL View of Absolute Model (Synplicity/Synplify Pro)

Figure RTL View of Absolute Model (Synplicity/Synplify Pro) Arithmetic Machines 329 Figure 6.1.1-14 RTL View of Absolute Model (Synplicity/Synplify Pro) The question often arises as to the whether the NUMERIC_STD or NUMERIC_UNSIGNED package should be used when

More information

Verilog Module 1 Introduction and Combinational Logic

Verilog Module 1 Introduction and Combinational Logic Verilog Module 1 Introduction and Combinational Logic Jim Duckworth ECE Department, WPI 1 Module 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog

More information

Introduction. Purpose. Intended Audience. Conventions. Close

Introduction. Purpose. Intended Audience. Conventions. Close Introduction Introduction Verilog-XL is a simulator that allows you to test the logic of a design. The process of logic simulation in Verilog-XL is as follows: 1. Describe the design to Verilog-XL. 2.

More information

ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog

ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7

More information

Verilog Coding Guideline

Verilog Coding Guideline Verilog Coding Guideline Digital Circuit Lab TA: Po-Chen Wu Outline Introduction to Verilog HDL Verilog Syntax Combinational and Sequential Logics Module Hierarchy Write Your Design Finite State Machine

More information

A flow chart is a graphical or symbolic representation of a process.

A flow chart is a graphical or symbolic representation of a process. Q1. Define Algorithm with example? Answer:- A sequential solution of any program that written in human language, called algorithm. Algorithm is first step of the solution process, after the analysis of

More information

Parallel logic circuits

Parallel logic circuits Computer Mathematics Week 9 Parallel logic circuits College of Information cience and Engineering Ritsumeikan University last week the mathematics of logic circuits the foundation of all digital design

More information