ECOM4311 Digital Systems Design
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1 ECOM 4311 Digital Systems Design Eng. Monther Abusultan Computer Engineering Dept. Islamic University of Gaza Page 1
2 Agenda 1. VHDL : Data Types Cont d 2. VHDL : Operators 3. VHDL : Signal Assignments Page 2
3 Data Types Signed/Unsigned - Defined in the std_logic_arith package. - Syntax is similar to that of STD_LOGIC_VECTOR not that of an Integer. - Arithmetic operations are allowed, Logical operations are not allowed. (contrary to STD_LOGIC_VECTOR). Relational operations are allowed. Page 3
4 Data Types Signed/Unsigned - Unsigned is never lower than zero. Ex 0101 represents the decimal represents the decimal 13 - Signed can be positive or negative (two s compliment) Ex 0101 represents the decimal represents the decimal -3 Page 4
5 Data Types Subtypes - A subtype is a type with a constraint. - Operations between type and its subtype are allowed. Ex SUBTYPE natural IS INTEGER RANGE 0 TO INTEGER'HIGH; SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO 'Z'; - Recall that STD_LOGIC=('X','0','1','Z','W','L','H','-'). - Therefore, my_logic=('0','1','z'). Page 5
6 Data Types Arrays - Arrays can be one-dimensional (1D), two-dimensional (2D), or 1Dx1D. - They can also be of higher dimensions, but they are not synthesizable. TYPE type_name IS ARRAY (specification) OF data_type; Ex TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; TYPE matrix IS ARRAY (0 TO 3) OF row; TYPE matrix2d IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; Page 6
7 Data Conversion conv_integer(p) : Converts INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an INTEGER value. (STD_LOGIC_VECTOR is not included) conv_unsigned(p, b): Converts INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an UNSIGNED value with size b bits. conv_signed(p, b): Converts INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to a SIGNED value with size b bits. conv_std_logic_vector(p, b): Converts INTEGER, UNSIGNED, SIGNED, or STD_LOGIC to a STD_LOGIC_VECTOR value with size b bits. Page 7
8 VHDL Operators VHDL Operators - Data types define both "values" and "operators" - There are "Pre-Determined" data types Pre-determined = Built-In = STANDARD Package - We can add additional types/operators by including other Packages - We'll first start with the STANDARD Package that comes with VHDL Page 8
9 Logical Operators VHDL Operators - works on types BIT, BIT_VECTOR, BOOLEAN - vectors must be same length - the result is always the same type as the input not and nand or nor xor xnor (NOT operator has precedence over the others) Page 9
10 Numerical Operators VHDL Operators - works on types INTEGER, REAL - the types of the input operands must be the same + "addition" - "subtraction" * "multiplication" / "division" mod "modulus" rem "remainder" abs "absolute value" ** "exponential" Page 10
11 VHDL Operators Relational Operators - used to compare objects of the same type - Output is always BOOLEAN (TRUE, FALSE) - works on types: BOOLEAN, BIT, BIT_VECTOR, CHARACTER, INTEGER, REAL, TIME = "equal" /= "not equal" < "less than" <= "less than or equal" > "greater than" >= "greater than or equal" Page 11
12 VHDL Operators Shift Operators - works on one-dimensional arrays - works on arrays that contain types BIT, BOOLEAN - the operator requires 1) An Operand (what is to be shifted) 2) Number of Shifts (specified as an INTEGER) - a negative Number of Shifts (i.e., "-") is valid and reverses the shift sll srl sla sra rol ror "shift left logical" "shift right logical" "shift left arithmetic" "shift right arithmetic" "rotate left" "rotate right" Page 12
13 Concatenation Operator VHDL Operators - combines objects of same type into an array - the order is preserved & "concatenate" ex) New_Bus <= ( Bus1(7:4) & Bus2(3:0) ) Page 13
14 VHDL Operators STD_LOGIC_1164 Operators - To expand the data types we have in VHDL, we include the IEEE Package "STD_LOGIC_1164" - This gives us the data types: STD_LOGIC STD_LOGIC_VECTOR - This gives us all of the necessary operators for these types Logical Numerical Relational Shift Page 14
15 VHDL Operators Assignment Operators - The signal assignment operator is <= - The variable assignment operator is := - The Results is always on the Left, Operands on the Right - Types need to all be of the same type - need to watch the length of arrays! Ex) x :=y; sum <= x + y; NewBus <= m & k; Page 15
16 Delayed Assignments Delay Modeling - VHDL allows us to include timing information into assignment statements - this gives us the ability to model real world gate delay - we use the keyword "after" in our assignment followed by a time operand. Ex) B <= not A after 2ns; - VHDL has two types of timing models that allow more accurate representation of real gates 1) Inertial Delay (default) 2) Transport Delay Page 16
17 Delayed Assignments Inertial Delay - if the input has two edge transitions in less time than the inertial delay, the pulse is ignored said another way - if the input pulse width is smaller than the delay, it is ignored - this models the behavior of trying to charge up the gate capacitance of a MOSFET ex) B <= A after 5ns; any pulses less than 5ns in width are ignored. Page 17
18 Delayed Assignments Transport Delay - transport delay will always pass the pulse, no matter how small it is. - this models the behavior of transmission lines - we have to explicitly call out this type of delay using the "transport" keyword ex) B <= transport A after 5ns; B <= transport not A after t_delay; Page 18
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