Contents 1 Basic of Test and Role of HDLs 2 Verilog HDL for Design and Test

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1 1 Basic of Test and Role of HDLs Design and Test RTL Design Process Postmanufacturing Test Test Concerns Test Methods Testability Methods Testing Methods Cost of Test HDLs in Digital System Test Hardware Modeling Developing Test Methods Virtual Testers Testability Hardware Evaluation Protocol Aware ATE ATE Architecture and Instrumentation Digital Stimulus and Measure Instruments DC Instrumentation AC Instrumentation RF Instrumentation Ate Summary Verilog HDL for Design and Test Motivations of Using HDLs for Developing Test Methods Using Verilog in Design Using Verilog for Simulation Using Verilog for Synthesis Using Verilog in Test Good Circuit Analysis Fault List Compilation and Testability Analysis Fault Simulation Test Generation Testability Hardware Design xi

2 xii Basic Structures of Verilog Modules, Ports, Wires, and Variables Levels of Abstraction Logic Value System Combinational Circuits Transistor-Level Description Gate-Level Description Equation-Level Description Procedural Level Description Instantiating Other Modules Sequential Circuits Registers and Shift Registers State Machine Coding A Complete Example (Adding Machine) Control/Data Partitioning Adding Machine Specification CPU Implementation Testbench Techniques Testbench Techniques A Simple Combinational Testbench A Simple Sequential Testbench Limiting Data Sets Synchronized Data and Response Handling Random Time Intervals Text IO Simulation Code Coverage PLI Basics Access Routines Steps for HDL/PLI Implementation Fault Injection in the HDL/PLI Environment Summary Fault and Defect Modeling Fault Modeling Fault Abstraction Functional Faults Structural Faults Structural Gate Level Faults Recognizing Faults Stuck-Open Faults Stuck-at-0 Faults Stuck-at-1 Faults Bridging Faults State-Dependent Faults Multiple Faults Single Stuck-at Structural Faults Detecting Single Stuck-at Faults

3 xiii 3.3 Issues Related to Gate Level Faults Detecting Bridging Faults Undetectable Faults Redundant Faults Fault Collapsing Indistinguishable Faults Equivalent Single Stuck-at Faults Gate-Oriented Fault Collapsing Line-Oriented Fault Collapsing Problem with Reconvergent Fanouts Dominance Fault Collapsing Fault Collapsing in Verilog Verilog Testbench for Fault Collapsing PLI Implementation of Fault Collapsing Summary Fault Simulation Applications and Methods Fault Simulation Gate-Level Fault Simulation Fault Simulation Requirements An HDL Environment Sequential Circuit Fault Simulation Fault Dropping Related Terminologies Fault Simulation Applications Fault Coverage Fault Simulation in Test Generation Fault Dictionary Creation Fault Simulation Technologies Serial Fault Simulation Parallel Fault Simulation Concurrent Fault Simulation Deductive Fault Simulation Comparison of Deductive Fault Simulation Critical Path Tracing Fault Simulation Differential Fault Simulation Summary Test Pattern Generation Methods and Algorithms Test Generation Basics Boolean Difference Test Generation Process Fault and Tests Terminologies and Definitions Controllability and Observability Controllability Observability

4 xiv Probability-Based Controllability and Observability SCOAP Controllability and Observability Distances Based Random Test Generation Limiting Number of Random Tests Combinational Circuit RTG Sequential Circuit RTG Summary Deterministic Test Generation Algorithms Deterministic Test Generation Methods Two-Phase Test Generation Fault-Oriented TG Basics The D-Algorithm PODEM (Path-Oriented Test Generation) Other Deterministic Fault-Oriented TG Methods Fault-Independent Test Generation Sequential Circuit Test Generation Test Data Compaction Forms of Test Compaction Test Compatibility Static Compaction Dynamic Compaction Summary Design for Test by Means of Scan Making Circuits Testable Tradeoffs Testing Sequential Circuits Testability of Combinational Circuits Testability Insertion Improving Observability Improving Controllability Sharing Observability Pins Sharing Control Pins Reducing Select Inputs Simultaneous Control and Observation Full Scan DFT Technique Full Scan Insertion Flip-Flop Structures Full Scan Design and Test Scan Architectures Full Scan Design Shadow Register DFT Partial Scan Methods Multiple Scan Design Other Scan Designs

5 xv 7.5 RT Level Scan Design RTL Design Full Scan RTL Design Multiple Scan Scan Designs for RTL Summary Standard IEEE Test Access Methods Boundary Scan Basics Boundary Scan Architecture Test Access Port Boundary Scan Registers TAP Controller The Decoder Unit Select and Other Units Boundary Scan Test Instructions Mandatory Instructions Board Level Scan Chain Structure One Serial Scan Chain Multiple-Scan Chain with One Control Test Port Multiple-Scan Chains with One TDI, TDO but Multiple TMS Multiple-Scan Chain, Multiple Access Port RT Level Boundary Scan Inserting Boundary Scan Test Hardware for CUT Two Module Test Case Virtual Boundary Scan Tester Boundary Scan Description Language Summary Logic Built-in Self-test BIST Basics Memory-based BIST BIST Effectiveness BIST Types Designing a BIST Test Pattern Generation Engaging TPGs Exhaustive Counters Ring Counters Twisted Ring Counter Linear Feedback Shift Register Output Response Analysis Engaging ORAs One s Counter Transition Counter Parity Checking Serial LFSRs (SISR) Parallel Signature Analysis

6 xvi 9.4 BIST Architectures BIST-related Terminologies A Centralized and Separate Board-level BIST Architecture (CSBL) Built-in Evaluation and Self-test (BEST) Random Test Socket (RTS) LSSD On-chip Self Test Self-testing Using MISR and SRSG Concurrent BIST BILBO Enhancing Coverage RT Level BIST Design CUT Design, Simulation, and Synthesis RTS BIST Insertion Configuring the RTS BIST Incorporating Configurations in BIST Design of STUMPS RTS and STUMPS Results Summary Test Compression Test Data Compression Compression Methods Code-based Schemes Scan-based Schemes Decompression Methods Decompression Unit Architecture Cyclical Scan Chain Code-based Decompression Scan-based Decompression Summary Memory Testing by Means of Memory BIST Memory Testing Memory Structure Memory Fault Model Stuck-At Faults Transition Faults Coupling Faults Bridging and State CFs Functional Test Procedures March Test Algorithms March C- Algorithm MATS+ Algorithm Other March Tests

7 11.5 xvii MBIST Methods Simple March MBIST March C- MBIST Disturb MBIST Summary Appendix A Using HDLs for Protocol Aware ATE Appendix B Gate Components for PLI Test Applications Appendix C Programming Language Interface Test Utilities Appendix D IEEE Std Boundary Scan Verilog Description Appendix E Boundary Scan IEEE Virtual Tester Appendix F Generating Netlist by Register Transfer Level Synthesis (NetlistGen) Index

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