8051 Core Specification

Size: px
Start display at page:

Download "8051 Core Specification"

Transcription

1 8051 Core Specification Authors: Jaka Simsic Simon Teran Rev. 0.1 August 14, 2001 First Draft Rev 0.1 First Draft 1 of 26

2 Revision History Rev. Date Authors Description /08/01 Jaka Simsic, Simon Teran First Draft Rev 0.1 First Draft 2 of 26

3 Table Of Contents INTRODUCTION... 7 FEATURES... 7 ARCHITECTURE... 9 MEMORY ORGANIZATION... 9 Logical separation of program and data memory... 9 Program Memory... 9 Data Memory... 9 Using both external memories together CPU CLOCK INTERRUPT STRUCTURE PORT STRUCTURES Writing to a Port Read-Modify-Write Feature TIMER/COUNTERS RESET OPERATION INSTRUCTION SET Addressing Modes Instructions TIMER/COUNTERS Timer/Counter modes INTERRUPTS External interrupts Timer 0 and Timer 1 interrupts Handling of Interrupts RESET REGISTERS LIST OF REGISTERS PSW: Program Status Word INTERRUPTS HANDLING REGISTERS IE: Interrupt Enable Register. 24 IP: Interupt Priority Register TIMER/COUNTERS CONTROL REGISTERS..25 TCON: Timer/Counter Control Register 25 Rev 0.1 First Draft 3 of 26

4 TMOD: Timer/Counter Mode Control Register.26 Rev 0.1 First Draft 4 of 26

5 Table Of Figures Figure 1 Features of 8051 core... 8 Figure 2 Internal Data Memory Figure 3 Interrupt locations in 8051 Program Memory Rev 0.1 First Draft 5 of 26

6 Table Of Tables Table 1 Alternate Functions of Port 3 Pins Table 2 Read-modify-write Instructions Table 3 List of Arithmetic Instructions Table 4 List of Logical Instructions Table 5 List of Data Transfer Instructions that Access Internal Data Memory Table 6 List of DataTransfer Instructions that Access External Data Memory Space Table 7 List of Lookup Table Read Instructions Table 8 List of Boolean Instructions Table 9 List of Unconditional Jumps Table 10 List of Conditional Jumps Table 11 Interrupt Priority Within Level Table 12 List of Registers Table 13 Register Bank selection Table 14 Timer/Counter Operating Mode selection Rev 0.1 First Draft 6 of 26

7 1 Introduction The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980's by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system products. The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory. Features The features of the 8051 core are: 8-bit CPU optimized for control applications Exstensive Boolean processing (single-bit logic) capabilities 64K Program Memory address space 64K Data Memory address space up to 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bidirectional and individually adressable I/O lines Two 16-bit timer/counters 6-source/5-vector interrupt structure with two priority levels Figure 1 shows the features of 8051 core. Rev 0.1 First Draft 7 of 26

8 Figure 1 Features of 8051 core Rev 0.1 First Draft 8 of 26

9 2 Architecture MEMORY ORGANIZATION Logical separation of program and data memory All 8051 devices have specific memory organization, they have separate address spaces for Program (ROM) and Data (RAM) Memory. This logical separation of Memory is useful because it allows the Data Memory to be accessed by 8-bit addresses, which can obviously be more quickly stored and manipulated by an 8-bit CPU. Of course, the l6-bit Data Memory addresses can still be generated with the DPTR register. Program Memory Program Memory can only be read, not written to. The address space for 8051 core is 16- bit, so there is maximum of 64K bytes of Program Memory. Up to 4 Kbytes of Program Memory can be on chip, internal Program Memory of the 8051 core. For access to external Program Memory is used signal PSEN (Program Store Enable). Data Memory Data Memory is on a separate address space than Program Memory. For external Data Memory accesses the CPU generates read and write signals RD and WR, as needed. The memory architecture of 8051 core includes 128 bytes of on-chip Data Memory which are more easily accessible directly by its instructions and there is also a number of Special Function Registers (SFRs). Internal Data Memory contains four banks of eight registers and a special 32-byte long segment which is bit addressable by a special subset of the 8051 instructions, the bit-instructions. External memory of maximum 64K bytes is accessable by "movx" instructions. Figure 2 shows 128 bytes of on-chip Data Memory, with its 4 banks of registers and 32-byte bit addressable segment. Rev 0.1 First Draft 9 of 26

10 7FH bank select bits in PSW H 18H 10H 08H 2FH 1FH 17H 0FH bit addressable space (bit addresses 0-7F) 4 banks of 8 registers (R0-R7), selected by two bits in PSW register 00 07H 0 RESET value of Stack Pointer Figure 2 Internal Data Memory, 128 bytes Using both external memories together Both memories (external Program Memory and external Data Memory) can be combined if desired.the read strobe to the external Program/Data memory is composed of the RD and PSEN signals which must be applied to the inputs of an AND gate and then the output of the gate can be used as the read strobe. CPU CLOCK 8051 microcontroller has a clock input pin. INTERRUPT STRUCTURE The 8051 core provides 4 interrupt sources: 2 external interrupts, 2 timer interrupts. Rev 0.1 First Draft 10 of 26

11 Additional description of interrupt structure follows in Operations chapter. PORT STRUCTURES The 8051 core contains four I/O ports. All four ports in the 8051 core are bidirectional. Each port has SFR (Special Function Registers P0 through P3) which works like a latch, an output driver and an input buffer. Both the output driver and the input buffer of Port 0, and the output driver of Ports 2 are used for accessing the external memory. It works like this: Port 0 outputs the low byte of the external memory address (which is time-multiplexed with the byte being written or read) and Port 2 outputs the highbyte of the external memory address (this is only needed when the address is 16 bits wide). If the address in question is 8 bits wide the Port 2 pins are not needed in this application. The Port 3 pins are multifunctional. Their alternate functions are listed in Table 1. Port Pin P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Function ~INT0 (external interrupt) ~INT1 (external interrupt) T0 (Timer/Counter 0 external input) T1 (Timer/Counter 1 external input) ~WR (external Data Memory writestrobe) ~RD (external DataMemory readstrobe) Table 1 Alternate Functions of Port 3 Pins This alternate functions are activated with the 1 written in the corresponding bit latch in the port SFR. Writing to a Port The new value arrives at the latch during the last phase (Phase 2), of the final cycle of the instruction that changes the value in a port latch. Because the port latches are sampled by their output buffers only during Phase 1 of any clock period (during Phase 2 the output buffer holds the value it saw during the previous Phase 1), the new value in the port latch won t actually appear at the output pin until the next Phase 1, which will be at the beginning of the following machine cycle. Rev 0.1 First Draft 11 of 26

12 Read-Modify-Write Feature When reading a port some instructions read the latch and others read the pin. The instructions that read the latch rather than the pin are the ones that read a value (possibly change it), and then rewrite it to the latch. Instructions with these attributes are called read-modify-write instructions. The instructions listed in a Table 2 below are readmodify-write instructions. ANL (logical AND, e.g., ANL PI, A) ORL (logical OR, e.g., ORL P2, A) XRL (logical EX-OR, e.g., XRL P3, A) JBC (jump if bit = 1 and clear bit, e.g., JBC P1.1, LABEL) CPL (complement bit, e.g., CPL P3.0) INC (increment, e.g., INC P2) DEC (decrement, e.g., DEC P2) DJNZ (decrernent and jump if not zero, e.g., DJNZ P3, LABEL) MOV,PX.Y, C (move carry bit to bit Y of Port X) CLR PX.Y (clear bit Y of Port X) SETB PX.Y (set bit Y of Port X) Table 2 Read-modify-write Instructions TIMER/COUNTERS The 8051 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. Both can work either as timers or event counters. Both have four different operating modes from which to select. All modes are described in Operations chapter. RESET The reset input is the RST pin. Rev 0.1 First Draft 12 of 26

13 3 Operation INSTRUCTION SET The instruction set of 8051 core is like already said optimized for 8-bit control applications. This optimization shows in a variety of fast addressing modes for accessing the internal RAM in order to facilitate byte operations on small data structures. The instruction set is also good for systems that require a lot of Boolean processing because it has an extensive support for one-bit variables as a separate data type (that makes direct bit manipulation a lot easier). Addressing Modes In the next section follows a brief description of the 8051 instruction set addressing modes. DIRECT ADDRESSING In direct addressing the operand is specified by an 8-bit address field in the instruction. This address mode is possible only for addressing internal Data RAM and SFRs. INDIRECT ADDRESSING In indirect addressing the instruction specifies a register which contains the address of the operand. The address register for 8-bit addresses can be R0 or R1 of the selected register bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit data pointer register, DPTR. Both internal and external RAM can be indirectly addressed. Rev 0.1 First Draft 13 of 26

14 REGISTER INSTRUCTIONS Special instructions are used for accessing four register banks (containing registers R0 to R7). This instructions have a 3-bit register specification within the opcode of the instruction. This way of accessing the registers is much more efficient, since there is no need for the address byte. When such instruction is executed one of registers in selected register bank is accessed. Register bank is selected by two bank select bits in PSW. REGISTER-SPECIFIC INSTRUCTIONS These are instructions which are specific to a certain register and they don't need an address byte (they always operate with the same register). IMMEDIATE CONSTANTS In this address mode the value of a constant follows the opcode. For example: MOV A, #10 loads the Accumulator with the decimal number 10. INDEXED ADDRESSING In this mode only Program Memory can be accessed and it can only be a read. This addressing mode is used for reading look-up tables in Program Memory and another type of indexed addressing is used in the case jump instruction. Instructions In Tables 3 to 10 in following section are described the instructions of 8051 core. Each Table contains a categorie of instructions, like Arithmetic instructions, Logical instructions, etc. Values in column Execution time in all Tables are meant to be in µs but this depends from the speed of processor. The abreviations in column Addressing modes stand for: Dir..Direct Addressing Rev 0.1 First Draft 14 of 26

15 Ind. Indirect Addressing Reg.Register Instructions Imm Immediate Constants All Addressing modes are described above. If the instruction is register-specific the column Addressing modes notes which register is used. ARITHMETIC INSTRUCTIONS Mnemonic Operation Addressing modes Execution time ADD A, <byte> A = A + <byte> Dir, Ind, Reg, Imm 1 ADDC A, <byte> A = A + <byte> + C Dir, Ind, Reg, Imm 1 SUBB A, <byte> A = A - <byte> - C Dir, Ind, Reg, Imm 1 INC A A = A + 1 Accumulator only 1 INC <byte> <byte> = <byte> + l DPTR only 1 INC DPTR DPTR = DPTR + 1 Dir, Ind, Reg 2 DEC A A = A 1 Accumulator only 1 DEC <byte> <byte> = <byte> - l Dir, Ind, Reg 1 MUL AB B:A=B x A ACC and B only 4 DIV AB A = Int [A/B] ACC and B only 4 B = Mod [A/Bl DA A Decimal Adjust Accumulator only 1 Table 3 List of Arithmetic Instructions LOGICAL INSTRUCTIONS Mnemonic Operation Addressing modes Execution time ANL A, < byte> A = A.AND. <byte> Dir, Ind, Reg, Imm 1 ANL A, < byte> <byte> = <byte>.and. A Dir 1 ANL <byte>, #data <byte> = <byte>.and. #data Dir 2 ORL A, < byte> A = A.OR. <byte> Dir, Ind, Reg, Imm 1 ORL A, < byte> <byte> = <byte>.or. A Dir 1 ORL <byte>, #data <byte> = <byte>.or. #data Dir 2 XRL A, < byte> A = A.XOR. <byte> Dir, Ind, Reg, Imm 1 XRL A, < byte> <byte> = <byte>.xor. A Dir 1 XRL <byte>, #data <byte> = <byte>.xor. #data Dir 2 CRL A A = 00H Accumulator only 1 CPL A A =.NOT. A Accumulator only 1 RL A Rotate ACC Left 1 bit Accumulator only 1 RLC A Rotate Left through Carry Accumulator only 1 RR A Rotate ACC Right 1 bit Accumulator only 1 RRC A Rotate Right through Carry Accumulator only 1 SWAP A Swap Nibbles in A Accumulator only 1 Table 4 List of Logical Instructions Rev 0.1 First Draft 15 of 26

16 DATA TRANSFERS Mnemonic Operation Addressing modes Execution time MOV A, <src> A = <src> Dir, Ind, Reg, Imm 1 MOV <dest>, A <dest> = A Dir, Ind, Reg 1 MOV <dest>, <src> <dest> = <src> Dir, Ind, Reg, Imm 2 MOV DPTR, #data 16 DPTR = 16-bit immediate Imm 2 constant PUSH <src> INCSP: SP, <src> Dir 2 POP <dest> MOV : DECSP Dir 2 XCH A, <byte> ACC and <byte> exchange data Dir, Ind, Reg 1 XCHD ACC exchange low nibbles Ind 1 Table 5 List of Data Transfer Instructions that Access Internal Data Memory Address width Mnemonic Operation Execution time 8 bits MOVX Read external 2 8 bits A Write external 2 16 bits MOVX Read external 2 16 bits A Write external 2 Table 6 List of DataTransfer Instructions that Access External Data Memory Space LOOKUP TABLES Mnemonic Operation Execution time MOVC Read Program Memory at 2 (A + DPTR) MOVC Read Program Memory at (A + PC) 2 Table 7 List of Lookup Table Read Instructions Rev 0.1 First Draft 16 of 26

17 BOOLEAN INSTRUCTIONS Mnemonic Operation Execution time ANL C, bit C = C.AND. bit 2 ANL C, /bit C = C.AND..NOT. bit 2 ORL C, bit C = C.OR. bit 2 ORL C, /bit C = C.OR..NOT. bit 2 MOV C, bit C = bit 1 MOV bit, C bit = C 2 CRL C C = 1 1 CRL bit bit = 0 1 SETB C C = 1 1 SETB bit bit = 1 1 CPL C C =.NOT. C 1 CPL bit bit =.NOT. bit 1 JC rel Jump if C = 1 2 JNC rel Jump if C = 0 2 JB bit, rel Jump if bit = 1 2 JNB bit, rel Jump if bit = 0 2 JBC bit, rel Jump if bit = 1; CLR bit 2 Table 8 List of Boolean Instructions JUMP lnstructions Mnemonic Operation Execution Time JMP addr Jump to addr 2 + DPTR Jump to A + DPTR 2 CALL addr Call subroutine at addr 2 RET Return from subroutine 2 RETI Return from interrupt 2 NOP No operation 1 Table 9 List of Unconditional Jumps Mnemonic Operation Addressing Modes Execution Time JZ rel Jump if A = 0 Accumulator only 2 JNZ rel Jumpif A 0 Accumulator only 2 DJNZ <byte>, rel Decrement and jump if not zero Dir, Reg 2 CJNE A, <byte>, rel Jump if A <byte> Dir, Imm 2 CJNE <byte>, #data, rel Jump if <byte> #data Ind, Reg 2 Table 10 List of Conditional Jumps Rev 0.1 First Draft 17 of 26

18 TIMER/COUNTERS Like already said the 8051 core has two 16-bit Timer/Counter registers. These are Timer/Counter 0 and Timer/Counter 1. These registers can be used as timers or as event counters. When a register is in the Timer state, it is incremented every machine cycle, in the Counter function, the register is incremented when there is a l-to-0 transition at its external input pin, pin T0 for Timer/Counter 0 or pin T1 for Timer/Counter 1. Both registers have additional operating modes. These four operating modes are all described in next section. Timer/Counter modes The selection for ''Timer'' or ''Counter'' function is done by control bits C/T in the Special Function Register TMOD (see Registers chapter). Both Timer/Counters have four operating modes which, Modes 0, 1, and 2 are the same for both Timer/Counters, Mode 3 is different. Modes are selected by bit pairs (M1, M0) in TMOD SFR. Another SFR, which is used for work with the Timer/Counters is TCON, which, among other, contains flag (TFx) and control (TRx) bits. MODE 0 Both Timer 1 and Timer 0 in Mode 0 operate as an 8-bit Counters (with a divide-by-32 prescaler). In this mode, the Timer register is configured as a 13-Bit register. The 13-Bit register consists of all 8 bits of THl and the lower 5 bits of TL1. The upper 3 bits of TLl are indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers. The Timer interrupt flag TF1 is set when the count rolls over from all 1s to all 0s. Mode 0 operation is the same for Timer 0 as for Timer 1. Just substitute Timer 0 for the corresponding Timer 1 signals. MODE 1 Mode 1 is the same as Mode 0 (for both Timers), except that the Timer register is configured as 16-bit register. Rev 0.1 First Draft 18 of 26

19 MODE 2 In Mode 2 both Timer registers are configured as an 8-bit Counters (TLl and TL0) with automatic reload. Overflow from TL1 (TL0) sets TFl (TF0), and also reloads TL1 (TL0) with the contents of THl (TH0), which is preset by software. The reload leaves TH1 (TH0) unchanged. MODE 3 Mode 3 is different for Timer 1 and Timer0. In Mode 3 Timer 1 just holds its count. It operates the same as when the TRl is set to 0. For Timer 0 is different, in Mode 3 TL0 and TH0 of Timer 0 are established as two separate counters. TL0 uses the Timer 0 control bits for its work: C/T, GATE, TR0, ~INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TFl from Timer 1. TH0 is now actually in control of the Timer 1 interrupt. Mode 3 is provided for applications that require an extra 8-bit timer or counter. With Timer 0 in Mode 3, 8051 core looks like it has three Timer/Countes. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used in any application not requiring an interrupt. INTERRUPTS As previously noted, the 8051 core provides 4 interrupt sources (2 external interrupts, 2 timer interrupts). They are all controlled via two SFRs, IE and IP (both registers are described in Registers chapter). Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the SFR named IE (Interrupt Enable). In the register also exists a global disable bit, which can be cleared to disable all interrupts at once. Likewise each interrupt source can also be individually set to one of two priority levels by setting or clearing a bit in the SFR named IP (Interrupt Priority). A low-priority interrupt can be interrupted by high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can t be interrupted by any other interrupt source. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced, so within each priority level there is a second priority structure. This internal priority structure is determined by the polling sequence, the priority levels are shown in Table Rev 0.1 First Draft 19 of 26

20 Source Priority Within Level IE0 highest TF0 IE1 TF1 lowest Table 11 Interrupt Priority Within Level External interrupts The external interrupts ~INT0 and ~INT1 have two ways of activation, they can be levelactivated or transition-activated. This depends on bits IT0 and ITl in Special Function Register TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in SFR TCON. On-chip hardware cleares the flag that generated an external interrupt when the service routine is vectored to, but only if the interrupt was transition-activated. When the interrupt is level-activated, then the external requesting source is controling the request flag, not the on-chip hardware. Timer 0 and Timer 1 interrupts Beside the external interrupt there are also the Timer 0 and Timer 1 interrupts. The Timers interrupts are generated by TF0 and TFl flags in their respective Timer/Counter registers. Similary like in the case of transition-activated external interrupts, the flag that generated an interrupt is cleared by the on-chip hardware when the service routine is vectored to. Handling of Interrupts When interrupt occurs (or correctly, when the flag for an enabled interrupt is found to be set (l)), the interrupt system generates an LCALL to the appropriate location in Program Memory, unless some other condition blocks the interrupt. Several conditions can block an interrupt: - an interrupt of equal or higher priority level is already in progress - the current (polling) cycle is not the final cycle in the execution of the instruction in progress - the instruction in progress is RETI or any write to the IE or IP registers. If an interrupt flag is active but not being responded to for one of the above conditions, must be still active when the blocking condition is removed, or the denied interrupt will not be serviced. Next step is saving the registers on stack. The hardware-generated LCALL causes only the contents of the Program Counter to be pushed onto the stack, and reloads the PC with the beginning address of the service routine. In some cases it also clears the flag that Rev 0.1 First Draft 20 of 26

21 generated the interrupt, and in other cases it doesn t. It clears an external interrupt flag (IE0 or IEl) only if it was transition-activated. Like already said only the Program Counter is automatically pushed onto the stack, not the PSW or any other register. Having only the PC be automatically saved gives programmer more freedom to decide how much time to spend saving other registers. Programmer must also be more careful with proper selection, which registers to save. The service routine for each interrupt begins at a fixed location. The interrupt locations are spaced at 8-byte interval, begining at 0003H for External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1 and 001BH for Timer 1, like shown in Figure 3. Execution of service routine continues from that location until the end, that is until it encounters RETI instruction. The RETI instruction does two things. It informs the processor that this interrupt routine is finished and secondly, reloads the PC from the two top bytes from the stack. Similar results colud be accomplished with RET instruction, with the distinction that the interrupt control system would be thinking an interrupt was still in progress. 001BH INTERRUPT LOCATIONS RESET 0013H 000BH 0003H 0000H Figure 3 Interrupt locations in 8051 Program Memory RESET The reset input is the RST pin. To accomplish a reset the RST pin must be held high for at least two machine cycles. In the response on the RST signal the CPU generates an internal reset. The external reset signal is asynchronous to the internal clock. Rev 0.1 First Draft 21 of 26

22 In the internal reset algorithm, 0s are written to all the SFRs except the port latches and the Stack Pointer. The port latches are initialized to FFH and the Stack Pointer to 07H. Important is also to know that driving the ALE and PSEN pins to 0 while reset is active could cause the device to go into an indeterminate state. The internal RAM is not affected by reset. On power up the RAM content is indeterminate. Rev 0.1 First Draft 22 of 26

23 4 Registers This section describes registers inside the 8051 core. The 8051 has a number of Special Function Registers (SFRs). Following Table 12 contains a list of all the SFRs end their addresses: LIST OF REGISTERS ACC Accumulator 0E0H B B Register 0F0H PSW Program Status Word 0D0H SP Stack Pointer 81H DPTR Data Pointer (2 Bytes) DPL Low Byte 82H DPH High Byte 83H P0 Port 0 80H P1 Port 1 90H P2 Port 2 0A0H P3 Port 3 0B0H IP Interrupt Priority Control 0B8H IE Interrupt Enable Control 0A8H TMOD Timer/Counter Mode Control 89H TCON Timer/Counter Control 88H TH0 Timer/Counter 0 High Byte 8CH TL0 Timer/Counter 0 Low Byte 8AH TH1 Timer/Counter 1 High Byte 8DH TL1 Timer/Counter 1 Low Byte 8BH Table 12 List of Registers Some SFRs can have their bits assigned for various functions. These registers are PSW, PCON, IE, IP, TCON and TMOD. A brief description of this SFRs is provided in next section. Rev 0.1 First Draft 23 of 26

24 PSW: Program Status Word (bit addressable) The PSW register contains several status bits that reflect the current state of the CPU. CY AC F0 RS1 RS0 OV P CY PSW.7 Carry Flag AC PSW.6 Auxiliary Carry Flag FO PSW.5 Flag 0 available to the user for general purpose RS1 PSW.4 Register Bank selector bit 1 RS0 PSW.3 Register Bank selector bit 0 OV PSW.2 Overflow Flag PSW.1 User definable flag P PSW.0 Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even umber of 1 bits in the accumulator. With RS1 and RS0 bits we can select the corresponding register bank. RS1 RS0 Register Bank Address H-07H 08H-0FH 10H-17H 18H-1FH Table 13 Register Bank selection INTERRUPTS HANDLING REGISTERS Both IE and IP registers are used for managing and controlling interrupts. The IE register is used for enableing (or disableing) interrupts and IP is used for setting the priority of interrupts. IE: Interrupt Enable Register (bit addressable) If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled. EA ET1 EX1 ET0 EX0 EA IE.7 Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA =1, each interrupt source is individually enabled or disabled by setting or Rev 0.1 First Draft 24 of 26

25 clearing its enable bit. IE.6 Not implemented IE.5 Not implemented IE.4 Not implemented ET1 IE.3 Enable or disable the Timer 1 overflow interrupt EX1 IE.2 Enable or disable External Interrupt 1 ET0 IE.1 Enable or disable the Timer 0 overflow interrupt EX0 IE.0 Enable or disable External Interrupt 0 IP: Interuppt Priority Register (bit addressable) If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1 the corresponding interrupt has a higher priority. PT1 PX1 PT0 PX0 IP.7 Not implemented IP.6 Not implemented IP.5 Not implemented IP.4 Not implemented PT1 IP.3 Defines the Timer 1 interrupt priority level PXl IP.2 Defines External Interrupt 1 priority level PT0 IP.1 Defines the Timer 0 interrupt priority level PX0 IP.0 Defines the External Interrupt 0 priority level TIMER/COUNTERS CONTROL REGISTERS Next two registers (TCON and TMOD) are used for work with Timer/Counters. Registers are used for controlling Timer/Counters and for switching between different operating modes. TCON: Timer/Counter Control Register (bit addressable) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TFl TCON.7 Timer 1 overflow flag. Set by hardware when the Timer/Counter 1 overflows. Cleared by hardware as processor vectors to the interrupt service routine. TR1 TCON.6 Timer 1 run control bit. Set/clared by software to turn Rev 0.1 First Draft 25 of 26

26 Timer/Counter 1 ON/OFF. TF0 TCON.5 Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hardware as processor vectors to the service routine. TR0 TCON.4 Timer 0 run control bit. Set/cleared by software to turn Timer/Counter ON/OFF. IE1 TCON.3 External Interrupt 1 edge flag. Set by hardware when External Interrupt edge is detected. Cleared by hardware when interrupt is processed. IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered External Interrupt. IE0 TCON.1 External Interrupt 0 edge flag. Set by hardware when External Interrupt edge detected. Cleared by hardware when interrupt is processed. IT0 TCON.0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered External Interrupt. TMOD: Timer/Counter Mode Control Register (not bit addressable) GATE C/T M1 M0 GATE C/T M1 M0 First half (from left) of TMOD register is for controling and managing TIMER 1, second half (from left) is for TIMER 0. GATE C/T When TRx (in TCON) is set and GATE = 1, TIMER/COUNTERx will run only while INTx pin is high (hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = 1 (software control). Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin). Ml Mode selector bit (see Table 14) M0 Mode selector bit (see Table 14) M1 M0 Operating Mode bit Timer (MCS-48 compatible) bit Timer/Counter bit Auto-Reload Timer/Counter (Timer 0). TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits, TH0 is an 8-bit Timer and is controlled by Timer 1 control bits (Timer 1) Timer/Counter 1 stopped Table 14 Timer/Counter Operating Mode selection Rev 0.1 First Draft 26 of 26

Microcontroller Intel [Instruction Set]

Microcontroller Intel [Instruction Set] Microcontroller Intel 8051 [Instruction Set] Structure of Assembly Language [ label: ] mnemonic [operands] [ ;comment ] Example: MOV R1, #25H ; load data 25H into R1 2 8051 Assembly Language Registers

More information

Microprocessors 1. The 8051 Instruction Set. Microprocessors 1 1. Msc. Ivan A. Escobar Broitman

Microprocessors 1. The 8051 Instruction Set. Microprocessors 1 1. Msc. Ivan A. Escobar Broitman Microprocessors 1 The 8051 Instruction Set Microprocessors 1 1 Instruction Groups The 8051 has 255 instructions Every 8-bit opcode from 00 to FF is used except for A5. The instructions are grouped into

More information

SN8F5000 Family Instruction Set

SN8F5000 Family Instruction Set SONiX Technology Co., Ltd. 8051-based Microcontroller 1 Overview SN8F5000 is 8051 Flash Type microcontroller supports comprehensive assembly instructions and which are fully compatible with standard 8051.

More information

C51 Family. Architectural Overview of the C51 Family. Summary

C51 Family. Architectural Overview of the C51 Family. Summary Architectural Overview of the C51 Family C51 Family Summary 1. Introduction............................................................ I.1. 1.1. TSC80C51/80C51/80C31.................................................................

More information

Architecture & Instruction set of 8085 Microprocessor and 8051 Micro Controller

Architecture & Instruction set of 8085 Microprocessor and 8051 Micro Controller of 8085 microprocessor 8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configuration 8-bit

More information

8051 Microcontroller

8051 Microcontroller 8051 Microcontroller EE4380 Fall 2001 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas 8051 Architecture Programmer s View Register Set Instruction Set Memory

More information

8051 Overview and Instruction Set

8051 Overview and Instruction Set 8051 Overview and Instruction Set Curtis A. Nelson Engr 355 1 Microprocessors vs. Microcontrollers Microprocessors are single-chip CPUs used in microcomputers Microcontrollers and microprocessors are different

More information

Programming of 8085 microprocessor and 8051 micro controller Study material

Programming of 8085 microprocessor and 8051 micro controller Study material 8085 Demo Programs Now, let us take a look at some program demonstrations using the above instructions Adding Two 8-bit Numbers Write a program to add data at 3005H & 3006H memory location and store the

More information

Memory organization Programming model - Program status word - register banks - Addressing modes - instruction set Programming examples.

Memory organization Programming model - Program status word - register banks - Addressing modes - instruction set Programming examples. MICROCONTROLLERS AND APPLICATIONS 1 Module 2 Module-2 Contents: Memory organization Programming model - Program status word - register banks - Addressing modes - instruction set Programming examples. MEMORY

More information

Digital Blocks Semiconductor IP

Digital Blocks Semiconductor IP Digital Blocks Semiconductor IP 805 Microcontroller General Description The Digital Blocks Microcontroller Verilog IP Core is complaint with the MCS 5 Instruction Set and contains standard 805 MCU peripherals,

More information

Digital Blocks Semiconductor IP

Digital Blocks Semiconductor IP 805 SFR Bus Digital Blocks Semiconductor IP 805 Microcontroller Configurable Peripherals General Description The Digital Blocks (Configurable Peripherals) Microcontroller Verilog IP Core is complaint with

More information

Microcontroller. Instruction set of 8051

Microcontroller. Instruction set of 8051 UNIT 2: Addressing Modes and Operations: Introduction, Addressing modes, External data Moves, Code Memory, Read Only Data Moves / Indexed Addressing mode, PUSH and POP Opcodes, Data exchanges, Example

More information

Digital Blocks Semiconductor IP

Digital Blocks Semiconductor IP Digital Blocks Semiconductor IP DB805C-FSM 805 Microcontroller FSM Finite State Machine General Description The Digital Blocks DB805C-FSM IP Core contains Digital Blocks compact DB805C CPU Core & GPIO

More information

80C51 family programmer s guide and instruction set. 80C51 Family. PROGRAMMER S GUIDE AND INSTRUCTION SET Memory Organization. Philips Semiconductors

80C51 family programmer s guide and instruction set. 80C51 Family. PROGRAMMER S GUIDE AND INSTRUCTION SET Memory Organization. Philips Semiconductors PROGRAMMER S GUIDE AND INSTRUCTION SET Memory Organization Program Memory The 80C51 has separate address spaces for program and data memory. The Program memory can be up to 64k bytes long. The lower 4k

More information

EEE3410 Microcontroller Applications Department of Electrical Engineering Lecture 4 The 8051 Architecture

EEE3410 Microcontroller Applications Department of Electrical Engineering Lecture 4 The 8051 Architecture Department of Electrical Engineering Lecture 4 The 8051 Architecture 1 In this Lecture Overview General physical & operational features Block diagram Pin assignments Logic symbol Hardware description Pin

More information

Module Contents of the Module Hours COs

Module Contents of the Module Hours COs Microcontrollers (EE45): Syllabus: Module Contents of the Module Hours COs 1 8051 MICROCONTROLLER ARCHITECTURE: Introduction to Microprocessors and Microcontrollers, the 8051 Architecture, 08 1 and pin

More information

MASSEY UNIVERSITY PALMERSTON NORTH CAMPUS

MASSEY UNIVERSITY PALMERSTON NORTH CAMPUS MASSEY UNIVERSITY PALMERSTON NORTH CAMPUS EXAMINATION FOR 159.233 COMPUTER SYSTEMS Semester One June 2008 Time allowed: THREE (3) hours This exam contains THREE (3) questions ANSWER ALL THREE (3) QUESTIONS

More information

Q. Classify the instruction set of 8051 and list out the instructions in each type.

Q. Classify the instruction set of 8051 and list out the instructions in each type. INTRODUCTION Here is a list of the operands and their meanings: A - accumulator; Rn - is one of working registers (R0-R7) in the currently active RAM memory bank; Direct - is any 8-bit address register

More information

UNIT 2 THE 8051 INSTRUCTION SET AND PROGRAMMING

UNIT 2 THE 8051 INSTRUCTION SET AND PROGRAMMING UNIT 2 THE 8051 INSTRUCTION SET AND PROGRAMMING Instructions Alphabetical List of Instructions ACALL: Absolute Call ADD, ADDC: Add Accumulator (With Carry) AJMP: Absolute Jump ANL: Bitwise AND CJNE: Compare

More information

C51 Family. C51 Family Programmer s Guide and Instruction Set. Summary

C51 Family. C51 Family Programmer s Guide and Instruction Set. Summary C51 Family Programmer s Guide and Instruction Set Summary 1. Memory Organization.................................................... I.3.2 1.1. Program Memory.......................................................................

More information

Contents 8051 Instruction Set BY D. BALAKRISHNA, Research Assistant, IIIT-H Chapter I : Control Transfer Instructions Lesson (a): Loop Lesson (b): Jump (i) Conditional Lesson (c): Lesson (d): Lesson (e):

More information

MCS -51 Programmer s Guide and Instruction Set

MCS -51 Programmer s Guide and Instruction Set MCS -51 Programmer s Guide and Instruction Set November 1992 Order Number 270249-003 COPYRIGHT INTEL CORPORATION 1996 MCS -51 PROGRAMMER S GUIDE AND INSTRUCTION SET CONTENTS PAGE MEMORY ORGANIZATION 1

More information

DR bit RISC Microcontroller. Instructions set details ver 3.10

DR bit RISC Microcontroller. Instructions set details ver 3.10 DR80390 8-bit RISC Microcontroller Instructions set details ver 3.10 DR80390 Instructions set details - 2 - Contents 1. Overview 7 1.1. Document structure. 7 2. Instructions set brief 7 2.1. Instruction

More information

Dodatak. Skup instrukcija

Dodatak. Skup instrukcija Dodatak Skup instrukcija Arithmetic Operations [@Ri] implies contents of memory location pointed to by R0 or R1 Rn refers to registers R0-R7 of the currently selected register bank 2 ADD A,

More information

Embedded Controller Programming

Embedded Controller Programming Embedded Controller Programming Counters, Timers and I/O in Assembly Language Ken Arnold Copyright 2000-2004 Ken Arnold 1 Outline Timer/Counters Serial Port More 8051 Instructions Examples Copyright 2000-2004

More information

UNIT THE 8051 INSTRUCTION SET AND PROGRAMMING

UNIT THE 8051 INSTRUCTION SET AND PROGRAMMING UNIT THE 8051 INSTRUCTION SET AND PROGRAMMING Instructions Alphabetical List of Instructions ACALL: Absolute Call ADD, ADDC: Add Accumulator (With Carry) AJMP: Absolute Jump ANL: Bitwise AND CJNE: Compare

More information

CS 320. Computer Architecture Core Architecture

CS 320. Computer Architecture Core Architecture CS 320 Computer Architecture 8051 Core Architecture Evan Hallam 19 April 2006 Abstract The 8051 is an 8-bit microprocessor designed originally in the 1980 s by the Intel Corporation. This inexpensive and

More information

The Timers/Counters The Serial Interface The Interrupt System Reset P0.0-P0.7 P2.0-P2.7. Port 2 Drivers. Port 2 Latch

The Timers/Counters The Serial Interface The Interrupt System Reset P0.0-P0.7 P2.0-P2.7. Port 2 Drivers. Port 2 Latch HARDWARE DESCRIPTION This chapter provides a detailed description of the 80C51 microcontroller (see Figure 1). Included in this description are: The port drivers and how they function both as ports and,

More information

8051 Microcontrollers

8051 Microcontrollers 8051 Microcontrollers Richa Upadhyay Prabhu NMIMS s MPSTME richa.upadhyay@nmims.edu March 15, 2016 8051 INSTRUCTIONS JUMP, LOOP AND CALL INSTRUCTIONS 8051 INSTRUCTIONS Repeating a sequence of instructions

More information

Introduction To MCS-51

Introduction To MCS-51 Introduction To MCS-51 By Charoen Vongchumyen Department of Computer Engineering Faculty of Engineering KMITLadkrabang 8051 Hardware Basic Content Overview Architechture Memory map Register Interrupt Timer/Counter

More information

UNIT MICROCONTROLLER AND ITS PROGRAMMING

UNIT MICROCONTROLLER AND ITS PROGRAMMING M i c r o p r o c e s s o r s a n d M i c r o c o n t r o l l e r s P a g e 1 UNIT-7 8051 MICROCONTROLLER AND ITS PROGRAMMING INTRODUCTION The microcontroller incorporates all the features that are found

More information

Programming Book Microcontroller Kit. Rev 3.0 January, Wichit Sirichote

Programming Book Microcontroller Kit. Rev 3.0 January, Wichit Sirichote Programming Book1 8051 Microcontroller Kit Rev 3.0 January, 016 016 Wichit Sirichote 1 Contents Overview...3 SAFTY INFORMATION...3 Tools...3 Experiment 1 Blinking LED...4 Experiment Binary number counting...9

More information

Assembly Language programming (2)

Assembly Language programming (2) EEE3410 Microcontroller Applications LABORATORY Experiment 2 Assembly Language programming (2) Name Class Date Class No. Marks Arithmetic, Logic and Jump instructions Objectives To learn and practice the

More information

Dragonchip. Instruction Set Manual

Dragonchip. Instruction Set Manual Dragonchip Instruction Set Manual Version 3.1 July 2004 The Objective of this document is to provide the user a detail description to the each instruction set used in Dragonchip s MCU family. There are

More information

Instruction Set Of 8051

Instruction Set Of 8051 Instruction Set Of 8051 By Darshan Patel M.Tech (Power Electronics & Drives) Assistant Professor, Electrical Department Sankalchand Patel college of Engineering-Visnagar Introduction The process of writing

More information

EE6502- MICROPROCESSOR AND MICROCONTROLLER

EE6502- MICROPROCESSOR AND MICROCONTROLLER . EE6502- MICROPROCESSOR AND MICROCONTROLLER UNIT III - 8051 MICROCONTROLLER PART - A 1. What is Microcontroller? A device which contains the microprocessor with integrated peripherals like memory, serial

More information

Y51 Microcontroller. Technical Manual

Y51 Microcontroller. Technical Manual Y51 Microcontroller Technical Manual Disclaimer Systemyde International Corporation reserves the right to make changes at any time, without notice, to improve design or performance and provide the best

More information

TUTORIAL. Donal Heffernan University of Limerick May Tutorial D.Heffernan 2000,

TUTORIAL. Donal Heffernan University of Limerick May Tutorial D.Heffernan 2000, 8051 TUTORIAL Donal Heffernan University of Limerick May-2002 8051 Tutorial D.Heffernan 2000, 2001 1 Blank 8051 Tutorial D.Heffernan 2000, 2001 2 Some reference material: Test books + MacKenzie Scott.

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. 8051 8052 and 80C51 Hardware Description December 1992 Order Number 270252-006

More information

The Microcontroller. Lecture Set 3. Major Microcontroller Families. Example Microcontroller Families Cont. Example Microcontroller Families

The Microcontroller. Lecture Set 3. Major Microcontroller Families. Example Microcontroller Families Cont. Example Microcontroller Families The Microcontroller Lecture Set 3 Architecture of the 8051 Microcontroller Microcontrollers can be considered as self-contained systems with a processor, memory and I/O ports. In most cases, all that is

More information

8051 Microcontroller

8051 Microcontroller 8051 Microcontroller 1 Salient Features (1). 8 bit microcontroller originally developed by Intel in 1980. (2). High-performance CMOS Technology. (3). Contains Total 40 pins. (4). Address bus is of 16 bit

More information

8051 microcontrollers

8051 microcontrollers 8051 microcontrollers Presented by: Deepak Kumar Rout Synergy Institute of Engineering and Technology, Dhenkanal Chapter 2 Introduction Intel MCS-51 family of microcontrollers consists of various devices

More information

ENE 334 Microprocessors

ENE 334 Microprocessors Page 1 ENE 334 Microprocessors Lecture 9: MCS-51: Moving Data : Dejwoot KHAWPARISUTH http://webstaff.kmutt.ac.th/~dejwoot.kha/ ENE 334 MCS-51 Moving Data Page 2 Moving Data: Objectives Use commands that

More information

Rev. No. History Issue Date Remark

Rev. No. History Issue Date Remark Preliminary Bar Code Reader Document Title Bar Code Reader Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 5, 2000 Preliminary 0.1 Change document title from Bar Code Reader

More information

8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT89S52

8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT89S52 Features Compatible with MCS -51 Products 8K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 10,000 Write/Erase Cycles 4.0V to 5.5V Operating Range Fully Static Operation: 0 Hz to 33 MHz

More information

INSTRUCCIONES ARITMETICAS ERROR! MARCADOR NO DEFINIDO.

INSTRUCCIONES ARITMETICAS ERROR! MARCADOR NO DEFINIDO. INSTRUCCIONES ARITMETICAS ERROR! MARCADOR NO DEFINIDO. ADD A,Rn Add register to 28..2F 1 12 X X X accumulator ADD A,direct Add direct byte 25 2 12 X X X to accumulator ADD A,@Ri Add indirect RAM 26..27

More information

ISSI. IS89C51 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 4-Kbytes of FLASH ISSI IS89C51 NOVEMBER 1998 FEATURES GENERAL DESCRIPTION

ISSI. IS89C51 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 4-Kbytes of FLASH ISSI IS89C51 NOVEMBER 1998 FEATURES GENERAL DESCRIPTION IS89C51 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 4-Kbytes of FLASH NOVEMBER 1998 FEATURES 80C51 based architecture 4-Kbytes of on-chip Reprogrammable Flash Memory 128 x 8 RAM Two 16-bit Timer/Counters

More information

Highlights. FP51 (FPGA based 1T 8051 core)

Highlights. FP51 (FPGA based 1T 8051 core) Copyright 2017 PulseRain Technology, LLC. FP51 (FPGA based 1T 8051 core) 10555 Scripps Trl, San Diego, CA 92131 858-877-3485 858-408-9550 http://www.pulserain.com Highlights 1T 8051 Core Intel MCS-51 Compatible

More information

VRS540-4kB Flash, 128B RAM, 25~40MHz, 8-Bit MCU

VRS540-4kB Flash, 128B RAM, 25~40MHz, 8-Bit MCU VRS540-4kB Flash, 28B RAM, 25~40MHz, 8-Bit MCU 34 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B H4 Tel: (54) 87-2447 http://www.goalsemi.com P.3 P.2 XTAL NC P0./AD VRS540 Overview

More information

MICROPROCESSORS AND MICROCONTROLLERS MATERIAL. Features of 8051:

MICROPROCESSORS AND MICROCONTROLLERS MATERIAL. Features of 8051: DEPARTMENT OF ECE MICROPROCESSORS AND MICROCONTROLLERS MATERIAL UNIT V 8051 MICROCONTROLLERS To make a complete microcomputer system, only microprocessor is not sufficient. It is necessary to add other

More information

UNIT MICROCONTROLLER

UNIT MICROCONTROLLER Page UNIT-5 805 MICROCONTROLLER INTRODUCTION The microcontroller incorporates all the features that are found in microprocessor. The microcontroller has built in ROM, RAM, Input Output ports, Serial Port,

More information

Application Brief D-005

Application Brief D-005 Interfacing the Avago HDSP-2xxx LED Alphanumeric Displays with the Intel 8751H Microcontroller Application Brief D-005 Introduction The HDSP-21xx/-25xx series of products is ideal for applications where

More information

8051 Memory Organization BY D. BALAKRISHNA, Research Assistant, IIIT-H Chapter 1: Memory Organization There are 2 types of memories available in 8051 microcontroller. Program memory/c code memory (ROM)

More information

VRS550-8kB Flash, 256B RAM, 25~40MHz, 8-Bit MCU VRS560-16kB Flash, 256B RAM, 40MHz, 8-Bit MCU

VRS550-8kB Flash, 256B RAM, 25~40MHz, 8-Bit MCU VRS560-16kB Flash, 256B RAM, 40MHz, 8-Bit MCU VRS550-8kB Flash, 256B RAM, 25~40MHz, 8-Bit MCU VRS560-6kB Flash, 256B RAM, 40MHz, 8-Bit MCU 34 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B H4 Tel: (54) 87-2447 http://www.goalsemi.com

More information

VRS570 32K Flash, 1kB RAM, 25~40MHz, 8-Bit MCU VRS580 64K Flash, 1kB RAM, 25~40MHz, 8-Bit MCU

VRS570 32K Flash, 1kB RAM, 25~40MHz, 8-Bit MCU VRS580 64K Flash, 1kB RAM, 25~40MHz, 8-Bit MCU VRS570 32K Flash, 1kB RAM, 25~40MHz, 8-Bit MCU VRS580 64K Flash, 1kB RAM, 25~40MHz, 8-Bit MCU 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com

More information

MODULE-1. Short Answer Questions

MODULE-1. Short Answer Questions MODULE-1 Short Answer Questions 1. Give the comparison between microprocessor and microcontroller. It is very clear from figure that in microprocessor we have to interface additional circuitry for providing

More information

Legacy documentation refer to the Altium Wiki for current information. TSK51x MCU

Legacy documentation refer to the Altium Wiki for current information. TSK51x MCU Summary Core Reference CR0115 (v2.0) March 13, 2008 The TSK51x is a fully functional, 8-bit microcontroller, incorporating the Harvard architecture. This core reference includes architectural and hardware

More information

Arithmetic and Logic

Arithmetic and Logic 8051 - Arithmetic and Logic EE4380 Fall 2001 Class 8 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas Signed Arithmetic - Concepts Representation of the sign

More information

ET355 Microprocessors Thursday 6:00 pm 10:20 pm

ET355 Microprocessors Thursday 6:00 pm 10:20 pm ITT Technical Institute ET355 Microprocessors Thursday 6:00 pm 10:20 pm Unit 4 Chapter 6, pp. 139-174 Chapter 7, pp. 181-188 Unit 4 Objectives Lecture: BCD Programming Examples of the 805x Microprocessor

More information

Principle and Interface Techniques of Microcontroller

Principle and Interface Techniques of Microcontroller Principle and Interface Techniques of Microcontroller --8051 Microcontroller and Embedded Systems Using Assembly and C LI, Guang ( 李光 ) Prof. PhD, DIC, MIET WANG, You ( 王酉 ) PhD, MIET 杭州 浙江大学 2011 Chapter

More information

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: 8051 Architecture Module No: CS/ES/5 Quadrant 1 e-text

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: 8051 Architecture Module No: CS/ES/5 Quadrant 1 e-text e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: 8051 Architecture Module No: CS/ES/5 Quadrant 1 e-text In this lecture the detailed architecture of 8051 controller, register bank,

More information

AL8051S 8-BIT MICROCONTROLLER Application Notes

AL8051S 8-BIT MICROCONTROLLER Application Notes AL8051S 8-BIT MICROCONTROLLER Application Notes 6-14-2012 Table of Contents GENERAL INFORMATION... 3 FEATURES... 3 Key features... 3 Design features... 3 INTERFACE... 4 Symbol... 4 Signal description...

More information

8XC51RA RB RC Hardware Description

8XC51RA RB RC Hardware Description 8XC51RA RB RC Hardware Description February 1995 Order Number 272668-001 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement

More information

What Registers are available? Programming in Assembler. Assembler Programming - like early Basic. Assembler Data Movement Instructions

What Registers are available? Programming in Assembler. Assembler Programming - like early Basic. Assembler Data Movement Instructions Programming in Assembler Need knowledge of CPU 8051 Programmers model what registers are available? what memory is available? code memory (for programs) data memory (for variables and the stack) what instructions

More information

Handshake Solutions. HT80C51 User Manual

Handshake Solutions. HT80C51 User Manual HT8C5 User Manual HT8C5 User Manual Document Information Document Information Document Title Date of Creation 27/6/25 Date of last change 27/6/25 File name Status Version Number.7 Client / Target Audience

More information

8051 Programming: Arithmetic and Logic

8051 Programming: Arithmetic and Logic 8051 Programming: Arithmetic and Logic EE4380 Fall 2002 Class 4 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas Topics Signed and Unsigned arithmetic Binary

More information

Question Bank Microprocessor and Microcontroller

Question Bank Microprocessor and Microcontroller QUESTION BANK - 2 PART A 1. What is cycle stealing? (K1-CO3) During any given bus cycle, one of the system components connected to the system bus is given control of the bus. This component is said to

More information

Chapter Family Microcontrollers Instruction Set

Chapter Family Microcontrollers Instruction Set Chapter 4 8051 Family Microcontrollers Instruction Set Lesson 5 Program Flow Control and Interrupt Flow Control Instructions 2 Branch instructions- Jump to new value of Program Counter (PC) LJMP address16

More information

8051 Instruction Set

8051 Instruction Set 8051 Instruction Set 23-ug-16 ptkarule@rediffmail.com 1 Programmers Model of 8051 7FH 30H 2FH 20H 1FH 00H General Purpose Bit addressable Register Banks 1FH 18H 17H 10H 0FH 08H 07H 00H R7 R6 R5 R4 R3 R2

More information

MICROPROCESSOR LABORATORY MANUAL

MICROPROCESSOR LABORATORY MANUAL MICROPROCESSOR LABORATORY MANUAL T.C. AYDIN ADNAN MENDERES UNIVERSITY ENGINEERING FACULTY ELECTRICAL & ELECTRONICS ENGINEERING DEPARTMENT Prepared by: Res. Asst. Abdullah GÜLDEREN Aydın 2019 Contents 1.

More information

Interrupts. EE4380 Fall 2001 Class 9. Pari vallal Kannan. Center for Integrated Circuits and Systems University of Texas at Dallas

Interrupts. EE4380 Fall 2001 Class 9. Pari vallal Kannan. Center for Integrated Circuits and Systems University of Texas at Dallas 8051 - Interrupts EE4380 Fall 2001 Class 9 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas Polling Vs Interrupts Polling: MCU monitors all served devices continuously,

More information

Three criteria in Choosing a Microcontroller

Three criteria in Choosing a Microcontroller The 8051 Microcontroller architecture Contents: Introduction Block Diagram and Pin Description of the 8051 Registers Some Simple Instructions Structure of Assembly language and Running an 8051 program

More information

8051 Microcontrollers

8051 Microcontrollers 8051 Microcontrollers Richa Upadhyay Prabhu NMIMS s MPSTME richa.upadhyay@nmims.edu March 8, 2016 Controller vs Processor Controller vs Processor Introduction to 8051 Micro-controller In 1981,Intel corporation

More information

TUTORIAL Assembly Language programming (2)

TUTORIAL Assembly Language programming (2) 8051 Assembly Language programming (2) TUTORIAL 4 EEE3410 Microcontroller Applications 1. Write the instructions to move value 34h into register A and value 3Fh into register B, then add them together.

More information

Principle and Interface Techniques of Microcontroller

Principle and Interface Techniques of Microcontroller Principle and Interface Techniques of Microcontroller --8051 Microcontroller and Embedded Systems Using Assembly and C LI, Guang ( 李光 ) Prof. PhD, DIC, MIET WANG, You ( 王酉 ) PhD, MIET 杭州 浙江大学 2014 Chapter

More information

8051 Programming using Assembly

8051 Programming using Assembly 8051 Programming using Assembly The Instruction Addressing Modes dest,source ; dest = source A,#72H ;A=72H A, # r ;A= r OR 72H R4,#62H ;R4=62H B,0F9H ;B=the content of F9 th byte of RAM DPTR,#7634H DPL,#34H

More information

Chapter 09. Programming in Assembly

Chapter 09. Programming in Assembly Chapter 09 Programming in Assembly Lesson 03 Programming Approach for Main and Interrupt Service Routines in 8051 Program Approach for programming Main Program Instructions 3 Main program initial instructions

More information

CPEG300 Embedded System Design. Lecture 6 Interrupt System

CPEG300 Embedded System Design. Lecture 6 Interrupt System CPEG300 Embedded System Design Lecture 6 Interrupt System Hamad Bin Khalifa University, Spring 2018 Correction Lecture 3, page 18: Only direct addressing mode is allowed for pushing or popping the stack:

More information

MICROPROCESSOR & MICROCONTROLLER

MICROPROCESSOR & MICROCONTROLLER a) From road north to East From road east to north From road south to west From road west to south From road west to north b) From road north to East From road south to west From road south to north From

More information

8051 Microcontroller Logical Operations. Prepared by : A. B. Modi Target Audience : 5 th Semester Students

8051 Microcontroller Logical Operations. Prepared by : A. B. Modi Target Audience : 5 th Semester Students 8051 Microcontroller Logical Operations Prepared by : A. B. Modi Target Audience : 5 th Semester Students Learning Objectives After learning this chapter, Students should be able to: Describe and Use byte-level

More information

Vidyalankar T.E. Sem. V [ETRX] Microprocessors and Microcontrollers I Prelim Question Paper Solution

Vidyalankar T.E. Sem. V [ETRX] Microprocessors and Microcontrollers I Prelim Question Paper Solution 1. (a) 1. (b) T.E. Sem. V [ETRX] Microprocessors and Microcontrollers I Prelim Question Paper Solution Priority modes. 1) Fully Nested Mode : It is a general purpose mode. IR 0 highest priority IR 1 lowest

More information

80C51 Block Diagram. CSE Overview 1

80C51 Block Diagram. CSE Overview 1 80C51 Block Diagram CSE 477 8051 Overview 1 80C51 Memory CSE 477 8051 Overview 3 8051 Memory The data width is 8 bits Registers are 8 bits Addresses are 8 bits i.e. addresses for only 256 bytes! PC is

More information

8XC151SA and 8XC151SB Hardware Description

8XC151SA and 8XC151SB Hardware Description 8XC151SA and 8XC151SB Hardware Description June 1996 Order Number 272832-001 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement

More information

8051 Microcontroller Assembly Programming

8051 Microcontroller Assembly Programming 8051 Microcontroller Assembly Programming EE4380 Fall 2002 Class 3 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas Topics Machine code 8051 Addressing Modes

More information

Lecture 5. EEE3410 Microcontroller Applications Department of Electrical Engineering Assembly Language Programming (1)

Lecture 5. EEE3410 Microcontroller Applications Department of Electrical Engineering Assembly Language Programming (1) Department of Electrical Engineering Lecture 5 8051 Assembly Language Programming (1) 1 In this Lecture 8051 programming model Assembly language syntax Operation codes and operands Machine instructions

More information

Introduction to uc & Embedded Systems

Introduction to uc & Embedded Systems Introduction to uc & Embedded Systems Prepared by, Tamim Roshdy Embedded Systems What is an embedded system? An embedded system is an application that contains at least one programmable computer (typically

More information

8-BIT MICROCONTROLLER

8-BIT MICROCONTROLLER 8-BIT MICROCONTROLLER Table of Contents- 1 GENERAL DESCRIPTION... 4 2 FEATURES... 5 3 PARTS INFORMATION LIST... 6 3.1 Lead Free (RoHS) Parts information list... 6 4 PIN CONFIGURATIONS... 7 5 PIN DESCRIPTIONS...

More information

Chapter 9. Programming Framework

Chapter 9. Programming Framework Chapter 9 Programming Framework Lesson 1 Registers Registers Pointers Accumulator Status General Purpose Outline CPU Registers Examples 8-bitA (Accumulator) Register 8-bit B Register 8-bitPSW (Processor

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER 14 EXAMINATION Model Answer

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER 14 EXAMINATION Model Answer MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC 27001 2005 Certified) SUMMER 14 EXAMINATION Model Answer Subject Code : 12187 Page No: 1/28 Important Instructions to examiners: 1)

More information

FACULTY OF ENGINEERING LAB SHEET

FACULTY OF ENGINEERING LAB SHEET FACULTY OF ENGINEERING LAB SHEET MICROCONTROLLER AND MICROPROCESSOR SYSTEMS ECE2216 TRIMESTER 1 (2017/2018) MP2: Construction and programming of a basic electronic piano *Note: On-the-spot evaluation may

More information

The Final Word on 8051 Microcontroller

The Final Word on 8051 Microcontroller The Final Word on 8051 Microcontroller This is a book about the Intel 8051 microcontroller and its large family of descendants. It is intended to give you, the reader, some new techniques for optimizing

More information

8-bit Microcontroller with 2/4-Kbyte Flash AT89LP2052 AT89LP4052

8-bit Microcontroller with 2/4-Kbyte Flash AT89LP2052 AT89LP4052 Features Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85 C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable (ISP) Flash

More information

IA8044/IA8344 Variants IA8044 4kB internal ROM with R0117 version 2.3 firmware, 192 byte internal RAM, 64kB external program and data space.

IA8044/IA8344 Variants IA8044 4kB internal ROM with R0117 version 2.3 firmware, 192 byte internal RAM, 64kB external program and data space. FEATURES Form, Fit, and Function Compatible with the Intel 8044/8344 Packaging options available: 40 Pin Plastic Dual In-Line Package (PDIP), 44 Pin Plastic Leaded Chip Carrier (PLCC) 8-Bit Control Unit

More information

Microcontrollers can be considered as self-contained systems with a processor, memory and I/O ports.

Microcontrollers can be considered as self-contained systems with a processor, memory and I/O ports. 8051 Architecture 1 Microcontrollers can be considered as self-contained systems with a processor, memory and I/O ports. In most cases, all that is missing is the software to define the operation of the

More information

MODEL ANSWER SUBJECT- MICROCONTROLLER(12187) CLASS-EJ5E CLASS TEST-02 Q1.)Attempt any THREE of the following.

MODEL ANSWER SUBJECT- MICROCONTROLLER(12187) CLASS-EJ5E CLASS TEST-02 Q1.)Attempt any THREE of the following. MODEL ANSWER SUBJECT- MICROCONTROLLER(12187) CLASS-EJ5E CLASS TEST-02 Q1.)Attempt any THREE of the following. (9M) 1) Describe the instructions SWAP A and MOVX@DPTR,A with one example. (3Marks) SWAP A

More information

ENE 334 Microprocessors

ENE 334 Microprocessors Page 1 ENE 334 Microprocessors Lecture 10: MCS-51: Logical and Arithmetic : Dejwoot KHAWPARISUTH http://webstaff.kmutt.ac.th/~dejwoot.kha/ ENE 334 MCS-51 Logical & Arithmetic Page 2 Logical: Objectives

More information

SUMMER 13 EXAMINATION

SUMMER 13 EXAMINATION MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC - 27001-2005 Certified) Subject Code: 12187 SUMMER 13 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should

More information

CHAPTER ASSEMBLY LANGUAGE PROGRAMMING

CHAPTER ASSEMBLY LANGUAGE PROGRAMMING CHAPTER 2 8051 ASSEMBLY LANGUAGE PROGRAMMING Registers Register are used to store information temporarily: A byte of data to be processed An address pointing to the data to be fetched The vast majority

More information

Microcontroller and Applications

Microcontroller and Applications S.Y. Diploma : Sem. IV [DE/EJ/ET/EN/EX/EQ/IS/IC/IE] Microcontroller and Applications Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 70 Q.1 Attempt any FIVE of the following : [10] Q.1(a) Define

More information

IA8044/IA8344. SDLC Communications Controller. Data Sheet. SDLC Communications Controller January 9, 2015

IA8044/IA8344. SDLC Communications Controller. Data Sheet. SDLC Communications Controller January 9, 2015 IA8044/IA8344 SDLC Communications Controller Page 1 of 65 1-888-824-4184 Copyright 2015 by Innovasic Semiconductor, Inc. Published by Innovasic Semiconductor, Inc. 3737 Princeton Drive NE, Suite 130, Albuquerque,

More information