Microcontroller Intel [Instruction Set]

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1 Microcontroller Intel 8051 [Instruction Set]

2 Structure of Assembly Language [ label: ] mnemonic [operands] [ ;comment ] Example: MOV R1, #25H ; load data 25H into R1 2

3 8051 Assembly Language Registers MOV Instruction: MOV destination, source Example: 1. MOV A, $55H 2. MOV R0, A 3. MOV A, R3 3

4 Instruction Groups The 8051 has 255 instructions Every 8-bit opcode from 00 to FF is used except for A5. The instructions are grouped into 5 groups Arithmetic Logic Data Transfer Boolean Branching

5 Arithmetic Instructions ADD 8-bit addition between the accumulator (A) and a second operand. The result is always in the accumulator. The CY flag is set/reset appropriately. ADDC 8-bit addition between the accumulator, a second operand and the previous value of the CY flag. Useful for 16-bit addition in two steps. The CY flag is set/reset appropriately.

6 Arithmetic Instructions DA Decimal adjust the accumulator. Format the accumulator into a proper 2 digit packed BCD number. Operates only on the accumulator. Works only after the ADD instruction. SUBB Subtract with Borrow. Subtract an operand and the previous value of the borrow (carry) flag from the accumulator. A A - <operand> - CY. The result is always saved in the accumulator. The CY flag is set/reset appropriately.

7 Arithmetic Instructions INC Increment the operand by one. The operand can be a register, a direct address, an indirect address, the data pointer. DEC Decrement the operand by one. The operand can be a register, a direct address, an indirect address. MUL AB / DIV AB Multiply A by B and place result in A:B. Divide A by B and place result in A:B.

8 Logical Operations ANL / ORL Work on byte sized operands or the CY flag. ANL A, Rn ANL A, direct ANL ANL A, #data ANL direct, A ANL direct, #data ANL C, bit ANL C, /bit

9 Logical Operations XRL Works on bytes only. CPL / CLR Complement / Clear. Work on the accumulator or a bit. CLR P1.2

10 Logical Operations RL / RLC / RR / RRC Rotate the accumulator. RL and RR without the carry RLC and RRC rotate through the carry. SWAP A Swap the upper and lower nibbles of the accumulator. No compare instruction. Built into conditional branching instructions.

11 Data Transfer Instructions MOV 8-bit data transfer for internal RAM and the SFR. MOV A, Rn MOV A, direct MOV MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV MOV direct, #data A direct #data

12 Data Transfer Operations MOV 1-bit data transfer involving the CY flag MOV C, bit MOV bit, C MOV 16-bit data transfer involving the DPTR MOV DPTR, #data

13 Data Transfer Instructions MOVC Move Code Byte Load the accumulator with a byte from program memory. Must use indexed addressing MOVC MOVC

14 Data Transfer Instructions MOVX Data transfer between the accumulator and a byte from external data memory. MOVX MOVX MOVX MOVX A, A

15 Data Transfer Instructions PUSH / POP Push and Pop a data byte onto the stack. The data byte is identified by a direct address from the internal RAM locations. PUSH POP DPL 40H

16 Data Transfer Instructions XCH Exchange accumulator and a byte variable XCH A, Rn XCH A, direct XCH XCHD Exchange lower digit of accumulator with the lower digit of the memory location specified. XCHD The lower 4-bits of the accumulator are exchanged with the lower 4-bits of the internal memory location identified indirectly by the index register. The upper 4-bits of each are not modified.

17 Boolean Operations This group of instructions is associated with the single-bit operations of the This group allows manipulating the individual bits of bit addressable registers and memory locations as well as the CY flag. The P, OV, and AC flags cannot be directly altered. This group includes: Set, clear, and, or complement, move. Conditional jumps.

18 Boolean Operations CLR Clear a bit or the CY flag. CLR P1.1 CLR C SETB Set a bit or the CY flag. SETB A.2 SETB C CPL Complement a bit or the CY flag. CPL 40H ; Complement bit 40 of the bit addressable memory

19 Boolean Operations ORL / ANL OR / AND a bit with the CY flag. ORL C, 20H ; OR bit 20 of bit addressable ; memory with the CY flag MOV ANL C, /34H ; AND complement of bit 34 of bit addressable memory with the CY flag. Data transfer between a bit and the CY flag. MOV C, 3FH ; Copy the CY flag to bit 3F of the bit addressable memory. MOV P1.2, C ; Copy the CY flag to bit 2 of P1.

20 Boolean Operations JC / JNC Jump to a relative address if CY is set / cleared. JB / JNB Jump to a relative address if a bit is set / cleared. JB ACC.2, <label> JBC Jump to a relative address if a bit is set and clear the bit.

21 Branching Instructions The 8051 provides four different types of unconditional jump instructions: Short Jump SJMP Uses an 8-bit signed offset relative to the 1 st byte of the next instruction. Long Jump LJMP Uses a 16-bit address. 3 byte instruction capable of referencing any location in the entire 64K of program memory.

22 Branching Instructions Absolute Jump AJMP Uses an 11-bit address. 2 byte instruction The upper 3-bits of the address combine with the 5-bit opcode to form the 1 st byte and the lower 8-bits of the address form the 2 nd byte. The 11-bit address is substituted for the lower 11-bits of the PC to calculate the 16-bit address of the target. The location referenced must be within the 2K Byte memory page containing the AJMP instruction. Indirect Jump JMP + DPTR

23 Branching Instructions The 8051 provides 2 forms for the CALL instruction: Absolute Call ACALL Uses an 11-bit address similar to AJMP The subroutine must be within the same 2K page. Long Call LCALL Uses a 16-bit address similar to LJMP The subroutine can be anywhere. Both forms push the 16-bit address of the next instruction on the stack and update the stack pointer.

24 Branching Instructions The 8051 provides 2 forms for the return instruction: Return from subroutine RET Pop the return address from the stack and continue execution there. Return from ISV RETI Pop the return address from the stack. Restore the interrupt logic to accept additional interrupts at the same priority level as the one just processed. Continue execution at the address retrieved from the stack. The PSW is not automatically restored.

25 Branching Instructions The 8051 supports 5 different conditional jump instructions. ALL conditional jump instructions use an 8-bit signed offset. Jump on Zero JZ / JNZ Jump if the A == 0 / A!= 0 The check is done at the time of the instruction execution. Jump on Carry JC / JNC Jump if the C flag is set / cleared.

26 Branching Instructions Jump on Bit JB / JNB Jump if the specified bit is set / cleared. Any addressable bit can be specified. Jump if the Bit is set then Clear the bit JBC Jump if the specified bit is set. Then clear the bit.

27 Branching Instructions Compare and Jump if Not Equal CJNE Compare the magnitude of the two operands and jump if they are not equal. The values are considered to be unsigned. The Carry flag is set / cleared appropriately. CJNE CJNE CJNE CJNE A, direct, rel A, #data, rel Rn, #data, #data, rel

28 Branching Instructions Decrement and Jump if Not Zero DJNZ Decrement the first operand by 1 and jump to the location identified by the second operand if the resulting value is not zero. DJNZ DJNZ Rn, rel direct, rel No Operation NOP

29 Addressing Modes Five addressing modes are available: Immediate Register Direct Indirect Indexed There are three more modes: Relative Absolute Long These are used with calls, branches and jumps and are handled automatically by the assembler.

30 Immediate Addressing The data is directly specified in the instruction. Useful for getting constants into registers. Immediate data must be preceded with a # sign. MOV R0, #0F0H ; Load R0 with the value F0H The immediate value is a maximum of 8-bits. One exception, when dealing with the DPTR register it can be 16-bits. MOV DPTR, #2000H ; Load the value 2000H into the DPTR register

31 Register Addressing Mode Direct access to eight registers R0 through R7. MOV A, R0 MOV R1, A ADD A, R1 Not all combinations are valid. MOV R2, R1 ; Invalid There are 4 banks of registers accessible through register addressing. Only one bank can be accessed at a time controllable through bit RS0 and RS1 of the PSW. MOV PSW, # B Set RS0:RS1 to 11, therefore, accessing register bank 3.

32 Direct Addressing Direct addressing can access any on-chip hardware register. All on-chip memory locations and registers have 8-bit addresses. Can use the 8-bit address in the instruction. MOV A, 4H ; A mem[04h] Or can use the register name. MOV A, R4 Don t get confused with Immediate mode. No # sign.

33 Indirect Addressing R0 and R1 may be used as pointer registers where their contents indicate an address in internal RAM where the data is to be read or written. MOV R1, #40H ; Make R1 point to location 40 MOV ; Move the contents of 40H to A R1 ; Move contents of R1 into the ; memory location pointed to by R0.

34 Indirect Addressing Can also be used for accessing external memory: Can use R0 and R1 to point to external memory locations 00H to FFH. MOVX ; Move contents of external memory location whose address is in R1 into A Can also use DPTR to point to all 64k of external memory. MOVX

35 Indexed Addressing Use a register for storing a pointer to memory and another register for storing an offset. The effective address is the sum of the two: EA = Pointer + Offset MOVC ; Move byte from memory located at DPTR+A to A.

36 Program Control Instructions Unconditional Branch ajmp addr11 ; absolute jump ljmp addr16 ; long jump sjmp rel ; short jump to relative address ; jump indirect Conditional branch jz, jnz rel ; short conditional jump to rel. addr djnz rel ; decrement and jump if not zero cjne rel ; compare and jump if not equal Subroutine Call acall addr11 ; absolute subroutine call lcall addr16 ; long subroutine call ret ; return from subroutine call reti ; return from ISV

37 Target Address Target address can be, absolute: A complete physical address addr16: 16 bit address, anywhere in the 64k addr11: 11 bit address, anywhere within 2k page. rel: relative (forward or backward) -128 bytes to +127 bytes from the current code location Target address calculation for relative jumps PC of next instruction + rel address For jump backwards, drop the carry PC = 15H, SJMP 0FEH Address is 15H + FEH = 13H Basically jump to next instruction minus two (current instruction)

38 Conditional Jumps jz, jnz : Conditional on A=0 Checks to see if A is zero jz jumps if A is zero and jnz jumps is A not zero No arithmetic op need be performed (unlike 8086/8085) djnz : dec a byte and jump if not equal to zero djnz Rn, rel djnz direct, rel jnc : Conditional on carry CY flag jc rel jnc rel cjne : compare and jump if not equal cjne A, direct, rel cjne Rn, #data, rel #data, rel

39 Loop using djnz Add 3 to A ten times mov A, #0 ; clear A mov R2, #10 ; R2 10, can also say 0AH AGAIN: add A, #03 ; add 3 to A djnz R2, AGAIN ; repeat until R2==0 mov R5, A ; save the result in R5 Loop within loop using djnz mov R3, #100 loop1: mov R2, #10 ; trying for 1000 loop iterations loop2: nop ; no operation djnz R2, loop2 ; repeat loop2 until R2==0 djnz R3, loop1 ; repeat loop1 until R3==0

40 Unconditional Jumps LJMP addr16 Long jump. Jump to a 2byte target address 3 byte instruction SJMP rel Jump to a relative address from PC+127 to PC-128 Jump to PC (00H 7FH) Jump to PC 128 (80H FFH)

41 Call Instructions Subroutines: Reusable code snippets LCALL addr16 Long call. 3 byte instruction. Call any subroutine in entire 64k code space PC is stored on the stack ACALL addr11 2 byte instruction Call any subroutine within 2k of code space Other than this, same behavior as LCALL Saves code ROM for devices with less than 64K ROM RET Return from a subroutine call, Pops PC from stack

Microprocessors 1. The 8051 Instruction Set. Microprocessors 1 1. Msc. Ivan A. Escobar Broitman

Microprocessors 1. The 8051 Instruction Set. Microprocessors 1 1. Msc. Ivan A. Escobar Broitman Microprocessors 1 The 8051 Instruction Set Microprocessors 1 1 Instruction Groups The 8051 has 255 instructions Every 8-bit opcode from 00 to FF is used except for A5. The instructions are grouped into