MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences

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1 MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences Introductory Digital Systems Lab (6.111) uiz - Spring 2004 Prof. Anantha Chandrakasan Student Name: Problem 1 (16 Points): Problem 2 (24 Points): Problem 3 (24 Points): Problem 4 (16 Points): Problem 5 (20 Points): Total (100 Points): 1 of 10

2 Problem 1: Sequential Building Block Characterization: Consider the following implementation of a register. Assume that an inverter has a delay of 1 and that the switch is ideal. The switch is closed when the control input is high. K K D K K Master (inverting) Latch Slave (inverting) Latch (a) What type of register is shown above (circle one)?(4 points) positive edge-triggered negative edge-triggered (b) What is the setup time (t su ), hold time (t hold ), and propagation (t cq ) delay. Assume that K and K are ideal (i.e., the delay to derive K from K is zero). (12 points) 2 of 10

3 Problem 2: Clock Gating Circuit Assume for the entire problem that the counter reset is synchronous. (a) Consider the one second clock from lab2. The 1Hz enable is derived from the circuit below (the clock is the Mhz clock). Assume that a global reset signal puts the count to 0 (the circuit is not shown here). Suppose the 1Hz enable is used to clock other circuits that need to be updated once per second (e.g., the register shown below). Identify the main problem with this circuit. (4 points) register 1Hz Enable In D Out reset Counter Count[20:0] 21 Combinational Logic (comparator) = K 21 d (b) The following is a simple modification that is proposed to solve the problem of part (a). The counter is negative edge-triggered and the AND gate is introduced before the register clock. Assume that the AND gate is ideal (i.e., has zero delay). Does this circuit fix the problem of part (a)? If so, under what conditions does this circuit function properly? If not, explain why. (6 points) register 1Hz Enable In D Out reset Counter Count [20:0] 21 Combinational Logic (comparator) = K K 21 d of 10

4 (c) The solution of (b) is not a synchronous one (i.e., a single global clock to every register). Propose a fix to the problem in part (a) using a single clock (K). That is, both the counter and register are clocked from the same clock (K). The signal In should be loaded into the register once per second. You may add additional components in the diagram below. (6 points) reset 1Hz Enable register Counter Count [20:0] 21 Combinational Logic (comparator) = In D K Out K 21 d (d) For each of the following signals, specify if glitches are allowed. (circle one) (8 points) (i) Data lines to the M6264 when Glitches Not Allowed Glitches are Allowed writing (when W is low, G is high, chip is enabled) as long as it settles well before W goes high (ii) Address lines to the M6264 when Glitches Not Allowed Glitches are Allowed reading (when W is high, G is low, chip is enabled) as long as it settles well before the output data is required (iii) R/W for the AD670 (ADC) Glitches Not Allowed Glitches are Allowed when CE and CS are low (iv) Data inputs for the AD558 (DAC) Glitches Not Allowed Glitches are Allowed when CE and CS are low 4 of 10

5 Problem 3: Arithmetic (a) Consider the following 16-bit Carry Bypass Adder. Assume that the Sum Logic () block for stage i has as inputs P i, G i, and C in,i. Assume the following delays: Delay to produce the P i, G i signals from the A i, B i inputs is 1 (i.e., the delay of the logic block) Delay to compute C out_i from P i, G i and C in,i inputs is 1 (i.e., the delay of the Carry Logic () block) Delay to compute S i from C in,i, P i, G i being valid is 2 (i.e., the delay of the Sum Logic () block) Delay for the 2:1 multiplexor is 2 Delay to compute the group propagate, GP i, is 1 Highlight the critical path for this 16-bit adder directly on figure below (6 points) A 0 B 0 A 1 B 1 A 2 B 2 A 3 B 3 GP 0 = P 0 P 1 P 2 P 3 A 4 B 4 A 5 B 5 A 6 B 6 A 7 B 7 GP 1 = P 4 P 5 P 6 P 7 A 8 B 8 A 9 B 9 A 10 B 10 A 11 B 11 GP 2 = P 8 P 9 P 10 P 11 A 12 B 12 A 13 B 13 A 14 B 14 A 15 B 15 C in, C out,15 S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15 (b) Based on the structure in (a), assuming a block size equal to 4, write down an equation for the delay of an N input adder, where N is a multiple of 4. (6 points) 5 of 10

6 (c) Consider a 64-tap filter implemented using an accumulator architecture as shown below. How many bits will be required for the adder? (6 points)? reset_accumulator In (twos complement) 8-bits Coefficient (twos complement) 8-bits Twos Complement Multiplier 16-bits Twos complement, sign exted to match the adder width +? D K (d) There is an error in the following implementation of the carry out logic. Identify the error and propose a simple solution (it might involve changing the logic). (6 points) A B A B C in 0 1 C out 6 of 10

7 Problem 4: FA (a) Consider an FA architecture with three identical 4-input SRAM based lookup tables. For this problem do not worry about the circuits to perform the write operation into the SRAM. Each SRAM is shown to have 4 inputs (i.e., address bits) and one output bit. Draw the circuit diagram for using the three SRAMs shown below to implement an arbitrary function Y of 5-input variables in 4, in 3, in 2, in 1, in 0? Do not add any additional components. (8 points) in 4 SRAM1 in 3 in 2 in 1 in 0 A 3 A 2 A 1 A 0 SRAM3 Y SRAM2 7 of 10

8 (b)what is the function implemented by SRAM3 corresponding to your solution in part 4(a)? Explain. (8 points) 8 of 10

9 PROBLEM 5: Verilog (a) Consider the follow piece of code to implement a synchronizer (with two registers). Does the code implement the required functionality? (explain). If the code does not properly implement a synchronizer, modify the code as necessary. (6 points) input in; reg q1, q2; (posedge clk) begin q1 = in; q2 = q1; (b) The following Verilog code should synthesize to a purely combinational logic function (3:1 multiplexor, where we don t care about the case when sel = 11). Does it? If not, fix the code so that there are no memory elements. (6 points) module mux_3to1 (a, b,c, sel, out); input [1:0] sel; input a,b, c; output out; reg out; (a or b or c or sel) begin case (sel) 2 b00: out = a; 2 b01: out = b; 2 b10: out = c; case module 9 of 10

10 (c) A simple digital system consists of a four state FSM which increments a 4-bit synchronous counter when the FSM is in state 10. An asynchronous reset signal is used to force both the state machine and the counter to all zeros whenever it is high. Identify the major problem with this code when synthesized and propose a fix (i.e., make the necessary modifications to the code below. You may add a control signal). (8 points) module simple_fsm(clk, reset, count); input reset, clk; output [3:0] count; reg [3:0] count; reg [1:0] state; reg [1:0] next; (posedge clk or posedge reset) begin if (reset) begin state <= 2'b00; else begin state <= next; (state or reset) begin if (reset) count = 4'b0000; case (state) 2'b00: next = 2'b01; 2'b01: next = 2'b10; 2'b10: begin next = 2'b11; count = count +1; 2'b11: next = 2'b00; case //always module 10 of 10