EECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15


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1 1.) CLD2 problem 2.2 We are allowed to use AND gates, OR gates, and inverters. Note that all of the Boolean expression are already conveniently expressed in terms of AND's, OR's, and inversions. Thus, we can build the logic circuit directly from the Boolean expression by directly mapping each AND, OR, or inversion operation to its appropriate gate. a. X Y Z b. X Y Z c. X Y Z d. X Y Z e. X Y Z W Page 1 of 15
2 2.) CLD2 problem 2.3 This problem constrains you to using only NOR and NOT gates. Fortunately, the circuits are written such that using any other gate would make life more difficult than it would be using only NOR/NOT! Both circuits, in schematic form, are reproduced below: a. Y Z X b. Y X Z Page 2 of 15
3 3.) CLD2 problem 2.20 The first two parts in this problem asks for you to write a Boolean expression, given a logic expression in mform or M. By logic expression in canonical minterm (or sum of products) form, the problem means something of the form: ABC D ABC D In other words, a certain number of 4literal terms (each literal is ANDed together), who are all ORed together to form the complete Boolean expression. Likewise, canonical maxterm (or product of sums) form will look something like: ( A B C ( A B C In other words, a certain number of 4literal terms (each literal is ORed together), who are all ANDed together. The problem gives us a logic expression in m form. m form specifies a list of numbers, where each number corresponds to a 4literal term (an A, C and D (or their negations) ANDed together). The question is: how do you relate each number in the list to a Boolean term of 4 variables an A, C and D (or their negations) ANDed/ORed together)? The first two parts of this problem require that you use this relation from m Boolean expression, and the solutions below offer a simple way of determining the relation. a) In the first part, we are asked to produce a Boolean expression from the minterm specification: m(1,2,3,5,8,13) There are numerous ways of relating 1,2,3 to 4literal Boolean terms, however, the simplest is to use a graycode chart. A graycode chart (and you will learn much more about these when we cover Kmaps) is a 4x4 chart (for the 4variable (i.e. A, expression) that maps each 1,2,3 in m form to a Boolean expression. The chart is drawn like this: Page 3 of 15
4 AB CD The important point is that for any 4variable Boolean expression s chart looks exactly like the chart above. Specifically, we draw a standard 4x4 chart, label the columns and the rows with the binary numbers: 00, 01, 11, 10; and label the upper lefthand corner with AB (on top) and CD (on the side). The chart is called a graycode chart because of the ordering of the 00, 01, 11 and 10. Graycode means that consecutive index can only be different from the previous index by 1 bit. So, 01 is different from 00 by 1bit (the least significant bit), 11 is different from 01 by 1bit, and 10 is different from 11 by 1bit. Notice that 00, 01, 10, 11 (a fairly common way of enumerating binary values) is not a graycode. The AB and CD in the upper lefthand corner specify that the column binary values (because AB sits on top) represent tuples of { A, B}, and the row binary values represent tuples of { C, D} (because CD sits on the side). For example, the first row specifies the negation of D CD, namely C ; whereas the fourth row specifies C D. Likewise for the columns and AB. The next step in specifying the chart is to fill in each cell with a number that corresponds to a number in the m(1,2,3,5,8,13) list. We fill in every 4x4 chart in the exact same way: each cell gets the value specified by: { column, row}. So, every cell gets a value from 015, as { column, row} specifies a 4bit binary value. For example, the upperleft hand cell gets { 00,00}, or 0. The bottomright hand cell gets { 10,10}, or 10. The completed chart is shown below: AB CD Again, this chart is the same for every 4variable function! Feel free to memorize it! Now that the 4x4 chart is specified, we can read off what cell numbers appear in the m(1,2,3,5,8,13) list: Page 4 of 15
5 1 { 00,01} A BC D 2 { 00,10} 3 00,11} A BC D A { BC D 5 { 01,01} A BC D 8 { 10,00} A BC D 13 { 11,01} A BC D And the final Boolean expression in canonical minterm form is: + A BC D A BC D + A BC D + A BC D + A BC D + A BC D You may have noticed that we could have retrieved this mapping just from translating each cell number directly into binary, and reading off each literal from the binary (skipping the drawthechart step). You could also have used a truth table, which is the book s preferred method until Kmaps are developed. These methods are perfectly valid. The chart provides a symbolic abstraction for something that might otherwise be errorprone on an exam. b) To find the Boolean expression in canonical maxterm form, we will again use the 4x4 chart that was drawn above: AB CD As we are finding the maxterm form (see pg. 62 of your text for algorithms used to convert between one form and another), we will replace the ( 1,2,3,5,8,13) in m (1,2,3,5,8,13) with all those cell numbers (between 015) that do not appear in ( 1,2,3,5,8,13). Our adjusted bigm form expression is: M (0,4,6,7,9,10,11,12,14,15) This looks familiar: we can now relate each number 0, 4, 6, to a cell in the 4x4 chart, and just read off the 4literal terms. There is one more step, however, as we are working in maxterm form: we must negate each literal in each 4literal term, and form ORed terms instead of ANDed Page 5 of 15
6 terms. These Ored 4literal terms will be ANDed together to form the final expression. This corresponds to product of sums form. The combined process of selecting those numbers not in the m(1,2,3,5,8,13) list for our M (0,4,6,7,9,10,11,12,14,15) list, and negating each literal found using the 4x4 chart, while forming the product of sums form, is the equivalent of using DeMorgan s Law on the Boolean expression specified by m (1,2,3,5,8,13). We proceed as follows: 0 { 11,11} 4 { 10,11} 6 { 10,01} 7 { 10,00} 9 { 01,10} 10 { 01,01} 11 { 01,00} 12 { 00,11} 14 { 00,01} 15 { 00,00} And the final Boolean expression in canonical maxterm form is: c) Here, we are asked to express the complement of f in little m notation, and as a canonical minterm expression. m(1,2,3,5,8,13) To express the complement, we need only to sum the all the minterms not listed in the expression for : (note that since f is an expression of 4 variables, the truth table has entries, and thus minterm indexes range from 0 to 15) m(0,4,6,7,9,10,11,12,14,15) Page 6 of 15
7 Rewriting this in canonical minterm form is trivial (read the solution to part a. for details on this process). 0 { 0000} A BCD 4 { 0100} A BCD 6 { 0110} A BC D 7 { 0111} A BCD 9 { 1001} A BCD 10 { 1010} A BC D 11 { 1011} A BCD 12 { 1100} AB CD 14 { 1110} ABC D 15 { 1111} ABCD = A BCD + A BCD + A BC D + A BCD + A BCD + AB CD + ABC D + ABCD ABCD + ABCD + d) In this part, we are asked to express the complement of f in big M notation, and as a canonical maxterm expression. We have previously derived the big M expression for f (see part b): M(0,4,6,7,9,10,11,12,14,15) (note that the components of a maxterm expression are also the components of the minterm complement.) To obtain the expression for the complement, we need only to take the product of all maxterms not listed in the expression for. Thus : M(1,2,3,5,8,13) We follow the same tactic as before to turn this into a canonical form: express each maxterm index listed in binary, flip all of the bits if writing a maxterm expression (for minterms : 9 4 b1001, but for maxterms, 4 b0110), and assign the leftmost digit to A, and the rightmost digit to D. Then invert the terms that correspond to zeroes. ) 1 { 0001} { 1110} C D 2 { 0010} { 1101} Page 7 of 15
8 3 { 0011} { 1100} 5 { 0101} { 1010} 8 { 1000} { 0111} ( A 13 { 1101} { 0010} The canonical Boolean expression in maxterm form is: ) ( = C D A C D ) * * ( A Another way to approach this problem is to realize that to express as a minterm statement, we simply need to take the complement of the maxterm expression using DeMorgan s law. Similarly, to write as a maxterm expression, simply invert the minterm statement of using DeMorgan s: + = A BC D A BC D + A BC D + A BC D + A BC D + A BC D + = not( A BC D A BC D + A BC D + A BC D + A BC D + A BC D ) = ) C D C D ) ( A Page 8 of 15
9 4.) CLD2 problem 6.4 Preset and Clear have the same functionality as Set and Reset, respectively; Preset will makes the output a logic 1, and Clear makes the output a logic 0. (The names are changed to avoid confusion with the Set/Reset inputs of the RS latch.) Asynchronous means that these inputs will immediately affect the output, regardless of the state of the clock. If neither Preset nor Clear is asserted, the circuit should function like a typical D flipflop. Since the output of the circuit needs to change immediately when Preset or Clear is asserted, logic needs to be added inside the basic D flipflop block shown in Figure (Compare this to the synchronous solution to problem 6.5, where the combinational logic can be placed outside the D flipflop.) What will immediately assert Q, regardless of the state of the Clock? Remember that the RS latch is transparent asserting S will immediately (after some propagation delay) assert Q. So, we need to be able to change the state of the RS inputs on the final RS latch in order to affect the outputs Q and Q. Let s define two more variables for clarity: X = the output from the top pair of NOR gates in Figure 6.24, and Y = the output from the bottom pair of NOR gates. Thus, in the original D flipflop circuit, X=R and Y=S. We want Q to be asserted when the following conditions are true: 1) the original D flipflop circuit asserts S, OR 2) the Preset signal is asserted. However, we also need to handle the case when both the Preset and Clear inputs are asserted to avoid a possible race condition. The problem does not specify whether Preset or Clear is dominant; for this problem let s make the circuit Cleardominant. That means that if Preset and Clear are both asserted, the Preset signal is ignored and the output Q is logic 0. Using the definitions above, the functionality of the additional logic can be described as: Reset = (original circuit asserts X) OR (Clear is asserted) Set = [(original circuit asserts Y) OR (Preset is asserted)] AND (Clear is not asserted) The inputs to the final RS latch are thus: R = X + C S = (Y + P) C The final circuit is shown in Figure 1 D Flipflop with Asynchronous Preset/Clear. Page 9 of 15
10 1 D Flipflop with Asynchronous Preset/Clear Page 10 of 15
11 5.) CLD2 problem 6.5 Because the preset and clear are synchronous, it is only necessary to modify the input to the flipflop. This is different from the asynchronous solution (6.4) where the internals of the flipflop must be changed. In this case, we AND ~Clear with D and OR the result with Preset to get the new input into the flipflop. This gives us the following truth table. By placing the OR gate with Preset after the AND gate with ~Clear, we ensure that the flipflop is presetdominant. Clear Preset D Resulting Input D FlipFlop with Synchronous Preset/Clear. Presetdominant. Page 11 of 15
12 6.) CLD2 problem 6.10 Despite the ambiguity, the masterslave flipflop referred to in this problem is a negative edgetriggered flipflop. It, therefore, produces the same waveform as the standard negative edgetriggered flipflop. The waveforms for all circuits asked for are shown in Figure2 Waveforms. Clk D Negative edgetriggered MasterSlave Positive edgetriggered Clocked 2 Waveforms Page 12 of 15
13 7.) CLD2 problem 6.13 A JK flip flop has the following behavior: When J == K == 0, Q maintains its current value When J == 0 and K == 1, Q is reset to 0 at the next positive edge of the clock When J == 1 and K == 0, Q is set to 0 at the next positive edge of the clock When J == K == 1, Q will invert its current value at the next positive edge of the clock This behavior can be characterized by the truth table shown in Table 613 (with Q next representing the value Q will become after the next positive clock edge). J K Q Q next Table 613: Truth table for calculating Q next from J, K, and the current Q From the truth table we arrive at the following (unsimplified) boolean expression: Q next = J K Q + JK Q + JK Q + JKQ Using boolean algebra, this can be simplified to: Q next = JQ + K Q Page 13 of 15
14 Now that we have a simple expression for Q next in terms of the current state, Q, and the inputs J and K, we can now build the circuit logic to find Q next. We can then plug that wire into the D input of the DQ flip flop, and use the Q output of the the DQ Flip Flop as the output of the JK Flip Flop. This configuration is shown in Figure 3 JK Flipflop. K Q next D Q Q Q J Clk Clk 3 JK Flipflop Page 14 of 15
15 8.) Broken Accumulator The problem with the drawn accumulator is that it introduces a combinational logic loop; the output of the adder is directly connected to its own input. As the adder begins to perform the addition, it will also begin to alter its output, which simultaneously changes one of its own input. Since one of its input changes, the adder must compute a new output, which changes the input again. This system will never reach a steady state (unless In == 0) and will not accumulate properly. To fix this, we must add synchronicity to the circuit. This can be done by adding a register between the output of the adder and its input, shown in Figure 4 Accumulator. This register synchronizes this circuit so that it will only add once every cycle, allowing the output of the adder to settle completely in between different cycles. Only when the positive each of the next cycle hits will the register propagate the adder output back to the input of the adder, allowing it to perform the next add. In + Q Q D Clk Clk 4 Accumulator Page 15 of 15
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