Administrivia. CSE 370 Spring 2006 Introduction to Digital Design Lecture 9: Multilevel Logic

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Ralf Scott
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SE 370 Spring 2006 Introduction to igital esign Lecture 9: Multilevel Logic Last Lecture Introduction to Verilog Today Multilevel Logic Hazards dministrivia Hand in Homework #3 Homework #3 posted

1 SE 370 Spring 2006 Introduction to igital esign Lecture 9: Multilevel Logic Last Lecture Introduction to Verilog Today Multilevel Logic Hazards dministrivia Hand in Homework #3 Homework #3 posted this afternoon Lab #4 posted. note from drienne: When it says write an expression in canonical minterm form or canonical maxterm form, unless it explicitly says to use the shorthand m and M notation, please write a oolean expression. (Not deducted for in HW#2-#3 or on the Quiz.) Sequential Verilog-- locking and non-blocking assignments locking assignments (Q = ) Variable is assigned immediately New value is used by subsequent statements Non-blocking assignments (Q <= ) Variable is assigned after all scheduled statements are executed Value to be assigned is computed but saved for later Usual use: Register assignment Registers simultaneously take new values after the clock edge Example: Swap LK) temp = ; = ; = temp; LK) <= ; <= ; Sequential Verilog-- ssignments- watch out! locking versus Non-blocking reg,, ; clk) = ; = ; = ; reg,, ; clk) <= ; <= ; <= ;

2 Timing diagrams Sideways truth tables Show time-response of circuits Real gates have real delays Example: ' = 0 elays cause transient =1 time Example: = in 2-level logic 1 2 canonical sum-of-products minimized sum-of-products Some texts call timing diagrams waveforms 3 4 canonical product-of-sums minimized product-of-sums Timing diagram for = Time waveforms for 1 4 are identical Except for timing hazards (glitches) More on this shortly... Multilevel logic asic idea: Simplify logic using >2 gate levels Time space (speed versus gate count) tradeoff Two-level logic usually Has smaller delays (faster circuits) ut more gates and more wires (more circuit area) Sometimes has large fan-ins (slow) Easier to eliminate hazards Multilevel logic usually Has less gates (smaller circuits) ut can be slower (more gate delays) Harder to eliminate hazards

3 Multilevel logic example unction SOP: = E E E G is minimized! Six 3-input Ns; one 7-input OR; 25 wires Multilevel: = ()(E) G actored form One 3-input OR, two 2-input OR's, one 3-input N; 10 wires E G 3-level circuit = ()(E) G Multilevel NN/NN conversion = () ' original N-OR network introduce bubbles (conserve inversions) ' ' Level 1 Level 2 Level 3 Level 4 Multilevel NOR/NOR conversion Generic multilevel conversion = () ' original N-OR network ' Level 1 Level 2 Level 3 Level 4 = = (a) (b) original circuit add double bubbles at inputs introduce bubbles (conserve inversions) ' (c) ' ' distribute bubbles some mismatches (d) ' ' insert inverters to fix mismatches

4 N-OR-Invert and OR-N- Invert blocks OI and OI are dense 3-level building blocks 2x2 OI uses only 8 transistors Minimal delay logical concept N OR Invert 2x2 OI symbol 3x2 OI symbol Using OI and OI blocks pproach Start by finding If using OI, find in minimized SOP form If using OI, find in minimized POS form orm OI as ( ) Example: = ' ' SOP form: ' = '' OI form: = ('' )' ' ' Example: OI and OI OI form Use SOP ' = '' ' ' = ('' ' ')' ' ' ' ' OI form Use POS ' = (')(')('') = [(')(')('')]' ' ' ' ' Issues with multilevel design No global definition of optimal multilevel circuit Optimality deps on user-defined goals Synthesize an implementation that meets design goals Synthesis requires -tool help No simple hand methods like K-maps tools manipulate oolean expressions actoring, decomposition, etc. overed in more detail in SE467

5 Multilevel logic summary dvantages over 2-level logic Smaller circuits Reduced fan-in Less wires isadvantages w.r.t 2-level logic More difficult design Less powerful optimizing tools ynamic hazards What you should know for SE370 The basic multilevel idea Multilevel NN/NN and NOR/NOR conversion OI gates Hazards/glitches Hazards/glitches: Undesired output switching Occurs when different pathways have different delays Wastes power; causes circuit noise angerous if logic makes a decision while output is unstable angerous if using asynchronous circuits Solutions esign hazard-free circuits ifficult when logic is multilevel Wait until signals are stable Use synchronous circuits Types of hazards Static 1-hazard Output should stay logic 1 Gate delays cause brief glitch to logic 0 Static 0-hazard Output should stay logic 0 Gate delays cause brief glitch to logic 1 ynamic hazards Output should toggle cleanly Gate delays cause multiple transitions Static hazards Occur when a literal and its complement momentarily assume the same value Through different paths with different delays auses an (ideally) static output to glitch multiplexer S S' S S' static-0 hazard

6 ynamic hazards Occur when a literal assumes multiple values Through different paths with different delays auses an output to toggle multiple times ynamic hazards ynamic hazard Eliminating static hazards In 2-level logic circuits ssuming single-bit changes Key idea: Glitches happen when a changing input spans separate k-map encirclements Example: 1101 to 0101 change can cause a static-1 glitch = ' ' ' ' Eliminating static hazards (con t) Solution: dd redundant k-map encirclements Ensure that all single-bit changes are covered irst eliminate static-1 hazards: Use SOP form = ' ' ' ' ' ' Summary of hazards We can eliminate static hazards in 2-level logic or single-bit changes Eliminating static hazards also eliminates dynamic hazards Hazards are a difficult problem Multiple-bit changes in 2-level logic are hard Static hazards in multilevel logic are harder ynamic hazards in multilevel logic are harder yet tools and simulation/testing are indispensable Test vectors probe a design for hazards

! Replace maxterm OR gates with NOR gates! Place compensating inversion at inputs of AND gate

! Replace maxterm OR gates with NOR gates! Place compensating inversion at inputs of AND gate Two-level logic using NN gates (cont d) ELE 4 igital Electronics Week : ombinational Logic Implementation! OR gate with inverted inputs is a NN gate " de Morgan's: ' ' = ( )'! Two-level NN-NN network "