ECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 5 2/22/2018

Size: px
Start display at page:

Download "ECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 5 2/22/2018"

Transcription

1 ECE 331 Hardware Organization and Design Professor Jay Taneja UMass ECE - jtaneja@umass.edu Discussion 5 2/22/2018

2 Today s Discussion Topics Program Concepts Floating Point Floating Point Conversion Floating Point Special Cases

3 1 M I P S Reference Data CORE INSTRUCTION SET OPCODE FOR- / FUNCT NAME, MNEMONIC MAT OPERATION (in Verilog) (Hex) Add add R R[rd] = R[rs] + R[rt] (1) 0 / 20 hex Add Immediate addi I R[rt] = R[rs] + SignExtImm (1,2) 8 hex Add Imm. Unsigned addiu I R[rt] = R[rs] + SignExtImm (2) 9 hex Add Unsigned addu R R[rd] = R[rs] + R[rt] 0 / 21 hex And and R R[rd] = R[rs] & R[rt] 0 / 24 hex And Immediate andi I R[rt] = R[rs] & ZeroExtImm (3) c hex if(r[rs]==r[rt]) Branch On Equal beq I 4 PC=PC+4+BranchAddr (4) hex if(r[rs]!=r[rt]) Branch On Not Equal bne I 5 PC=PC+4+BranchAddr (4) hex Jump j J PC=JumpAddr (5) 2 hex Jump And Link jal J R[31]=PC+8;PC=JumpAddr (5) 3 hex Jump Register jr R PC=R[rs] 0 / 08 hex R[rt]={24 b0,m[r[rs] Load Byte Unsigned lbu I 24 +SignExtImm](7:0)} (2) hex Load Halfword R[rt]={16 b0,m[r[rs] lhu I 25 Unsigned +SignExtImm](15:0)} (2) hex Load Linked ll I R[rt] = M[R[rs]+SignExtImm] (2,7) 30 hex NAME NUMBER USE $zero 0 The Constant Value 0 $at 1 Assembler Temporary $v0-$v1 2-3 Values for Function Results and Expression Evaluation $a0-$a3 4-7 Arguments $t0-$t Temporaries $s0-$s Saved Temporaries $t8-$t Temporaries $k0-$k Reserved for OS Kernel $gp 28 Global Pointer $sp 29 Stack Pointer $fp 30 Frame Pointer $ra 31 Return Address Load Upper Imm. lui I R[rt] = {imm, 16 b0} f hex Load Word lw I R[rt] = M[R[rs]+SignExtImm] (2) 23 hex Nor nor R R[rd] = ~ (R[rs] R[rt]) 0 / 27 hex Or or R R[rd] = R[rs] R[rt] R[rt](15:0) (2) 0 / 25 hex Or Store Immediate Word sw I R[rt] M[R[rs]+SignExtImm] = ZeroExtImm = R[rt] (3) (2) 2b d hex Subtract sub R R[rd] = R[rs] - R[rt] (1) 0 / 22 hex 0 / 23

4 Program Concepts Program Counter ($pc) register that contains the address of the instruction currently being executed Stack Pointer ($sp) register that contains the address of the top of the stack (memory set aside for a program s computations) Frame Pointer ($fp) register that contains the address of the previous top of the stack from before the current procedure

5 Parts of a Floating Point Number x 10-3 Exponent Sign of mantissa Location of decimal point Mantissa Sign of exponent Base Mantissa is also called Significand ECE232: Floating Point 12

6 Single Precision Format Note that the exponent has no explicit sign bit Base? 32 bits M: Mantissa (23 bits) E: Exponent (8 bits) S: Sign of mantissa (1 bit) ECE232: Floating Point 13

7 Working with normalization (single precision) S {0,1} (1-bit) 1 E 254 (8-bits unsigned integer); Bias = f base-2 < Formula provides for the full range of possible floating point numbers. F S = (-1) 1. f * 2 E-Bias ECE232: Floating Point 17

8 IEEE Floating-Point Format single: 8 bits double: 11 bits S Exponent single: 23 bits double: 52 bits Fraction x = (-1) S (1+ Fraction) 2 (Exponent -Bias) S: sign bit (0 Þ non-negative, 1 Þ negative) Normalize significand: 1.0 significand < 2.0 Always has a leading pre-binary-point 1 bit, so no need to represent it explicitly (hidden bit) Significand is Fraction with the 1. restored Exponent: excess representation: actual exponent + Bias Ensures exponent is unsigned Single: Bias = 127; Double: Bias = ECE232: Floating Point 18

9 Categories of Floating Point Representation Depending on the value of the exponent and fraction, the floating point number can take on different meanings ECE232: Floating Point 22

10 An0ther Single precision example = 3 0 = positive mantissa x 2 3 = = ECE232: Floating Point 10

11 Floating Point Special Representations S E-127 F = (-1) 1. f * < 2 f 1 E 254 (single precision) Single Precision Double Precision Object represented Exponent Fraction Exponent Fraction nonzero 0 nonzero ± denormalized number Anything Anything ± floating point number ± infinity 255 nonzero 2047 nonzero NaN (not a number) ECE232: Floating Point 15

12 1 M I P S Reference Data CORE INSTRUCTION SET OPCODE FOR- / FUNCT NAME, MNEMONIC MAT OPERATION (in Verilog) (Hex) Add add R R[rd] = R[rs] + R[rt] (1) 0 / 20 hex Add Immediate addi I R[rt] = R[rs] + SignExtImm (1,2) 8 hex Add Imm. Unsigned addiu I R[rt] = R[rs] + SignExtImm (2) 9 hex Add Unsigned addu R R[rd] = R[rs] + R[rt] 0 / 21 hex And and R R[rd] = R[rs] & R[rt] 0 / 24 hex And Immediate andi I R[rt] = R[rs] & ZeroExtImm (3) c hex if(r[rs]==r[rt]) Branch On Equal beq I 4 PC=PC+4+BranchAddr (4) hex if(r[rs]!=r[rt]) Branch On Not Equal bne I 5 PC=PC+4+BranchAddr (4) hex Jump j J PC=JumpAddr (5) 2 hex Jump And Link jal J R[31]=PC+8;PC=JumpAddr (5) 3 hex Jump Register jr R PC=R[rs] 0 / 08 hex R[rt]={24 b0,m[r[rs] Load Byte Unsigned lbu I 24 +SignExtImm](7:0)} (2) hex Load Halfword R[rt]={16 b0,m[r[rs] lhu I 25 Unsigned +SignExtImm](15:0)} (2) hex Load Linked ll I R[rt] = M[R[rs]+SignExtImm] (2,7) 30 hex NAME NUMBER USE $zero 0 The Constant Value 0 $at 1 Assembler Temporary $v0-$v1 2-3 Values for Function Results and Expression Evaluation $a0-$a3 4-7 Arguments $t0-$t Temporaries $s0-$s Saved Temporaries $t8-$t Temporaries $k0-$k Reserved for OS Kernel $gp 28 Global Pointer $sp 29 Stack Pointer $fp 30 Frame Pointer $ra 31 Return Address Load Upper Imm. lui I R[rt] = {imm, 16 b0} f hex Load Word lw I R[rt] = M[R[rs]+SignExtImm] (2) 23 hex Nor nor R R[rd] = ~ (R[rs] R[rt]) 0 / 27 hex Or or R R[rd] = R[rs] R[rt] R[rt](15:0) (2) 0 / 25 hex Or Store Immediate Word sw I R[rt] M[R[rs]+SignExtImm] = ZeroExtImm = R[rt] (3) (2) 2b d hex Subtract sub R R[rd] = R[rs] - R[rt] (1) 0 / 22 hex 0 / 23

13 Floating Point Special Representations S E-127 F = (-1) 1. f * f < 2 There are two Zeroes, ±0, and two Infinities ± NaN (Not-a-Number) may have a sign and have a non-zero fraction - used for program diagnostics NaNs and Infinities have all 1s in the Exp field, E=255. F+ =, F/ =0 ECE232: Floating Point 14 Source: I. Koren, Computer Arithmetic Algorithms, 2nd Edition, 2002

14 IEEE Floating-Point Format single: 8 bits double: 11 bits S Exponent single: 23 bits double: 52 bits Fraction x = (-1) S (1+ Fraction) 2 (Exponent -Bias) S: sign bit (0 Þ non-negative, 1 Þ negative) Normalize significand: 1.0 significand < 2.0 Always has a leading pre-binary-point 1 bit, so no need to represent it explicitly (hidden bit) Significand is Fraction with the 1. restored Exponent: excess representation: actual exponent + Bias Ensures exponent is unsigned Single: Bias = 127; Double: Bias = 1203 ECE232: Floating Point 18

15 An0ther Single precision example = 3 0 = positive mantissa x 2 3 = = ECE232: Floating Point 10

16 Floating Point Special Representations S E-127 F = (-1) 1. f * f < 2 There are two Zeroes, ±0, and two Infinities ± NaN (Not-a-Number) may have a sign and have a non-zero fraction - used for program diagnostics NaNs and Infinities have all 1s in the Exp field, E=255. F+ =, F/ =0 ECE232: Floating Point 14 Source: I. Koren, Computer Arithmetic Algorithms, 2nd Edition, 2002

17 Floating Point Special Representations S E-127 F = (-1) 1. f * < 2 f 1 E 254 (single precision) Single Precision Double Precision Object represented Exponent Fraction Exponent Fraction nonzero 0 nonzero ± denormalized number Anything Anything ± floating point number ± infinity 255 nonzero 2047 nonzero NaN (not a number) ECE232: Floating Point 15

ECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 3 2/8/2018

ECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 3 2/8/2018 ECE 331 Hardware Organization and Design Professor Jay Taneja UMass ECE - jtaneja@umass.edu Discussion 3 2/8/2018 Study Jams Leader: Chris Bartoli Tuesday 5:30-6:45pm Elab 325 Wednesday 8:30-9:45pm Elab

More information

ECE232: Hardware Organization and Design

ECE232: Hardware Organization and Design ECE232: Hardware Organization and Design Lecture 11: Floating Point & Floating Point Addition Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Last time: Single Precision Format

More information

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local

More information

CS 351 Exam 2 Mon. 11/2/2015

CS 351 Exam 2 Mon. 11/2/2015 CS 351 Exam 2 Mon. 11/2/2015 Name: Rules and Hints The MIPS cheat sheet and datapath diagram are attached at the end of this exam for your reference. You may use one handwritten 8.5 11 cheat sheet (front

More information

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design. Computer Organization - Previously covered ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

More information

MIPS%Assembly% E155%

MIPS%Assembly% E155% MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary

More information

CS 61c: Great Ideas in Computer Architecture

CS 61c: Great Ideas in Computer Architecture MIPS Instruction Formats July 2, 2014 Review New registers: $a0-$a3, $v0-$v1, $ra, $sp New instructions: slt, la, li, jal, jr Saved registers: $s0-$s7, $sp, $ra Volatile registers: $t0-$t9, $v0-$v1, $a0-$a3

More information

Computer Architecture. The Language of the Machine

Computer Architecture. The Language of the Machine Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers

More information

ECE 30 Introduction to Computer Engineering

ECE 30 Introduction to Computer Engineering ECE 30 Introduction to Computer Engineering Study Problems, Set #3 Spring 2015 Use the MIPS assembly instructions listed below to solve the following problems. arithmetic add add sub subtract addi add

More information

Floating-point Arithmetic. where you sum up the integer to the left of the decimal point and the fraction to the right.

Floating-point Arithmetic. where you sum up the integer to the left of the decimal point and the fraction to the right. Floating-point Arithmetic Reading: pp. 312-328 Floating-Point Representation Non-scientific floating point numbers: A non-integer can be represented as: 2 4 2 3 2 2 2 1 2 0.2-1 2-2 2-3 2-4 where you sum

More information

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction

More information

Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying

More information

Course Administration

Course Administration Fall 2017 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture 2/4 Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701 E-mail: kodi@ohio.edu

More information

Lecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)

Lecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook) Lecture 2 Instructions: Language of the Computer (Chapter 2 of the textbook) Instructions: tell computers what to do Chapter 2 Instructions: Language of the Computer 2 Introduction Chapter 2.1 Chapter

More information

Lecture 5: Procedure Calls

Lecture 5: Procedure Calls Lecture 5: Procedure Calls Today s topics: Memory layout, numbers, control instructions Procedure calls 1 Memory Organization The space allocated on stack by a procedure is termed the activation record

More information

CSCI 402: Computer Architectures. Arithmetic for Computers (3) Fengguang Song Department of Computer & Information Science IUPUI.

CSCI 402: Computer Architectures. Arithmetic for Computers (3) Fengguang Song Department of Computer & Information Science IUPUI. CSCI 402: Computer Architectures Arithmetic for Computers (3) Fengguang Song Department of Computer & Information Science IUPUI 3.5 Today s Contents Floating point numbers: 2.5, 10.1, 100.2, etc.. How

More information

Computer Architecture. MIPS Instruction Set Architecture

Computer Architecture. MIPS Instruction Set Architecture Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design

More information

CS 61C: Great Ideas in Computer Architecture. MIPS Instruction Formats

CS 61C: Great Ideas in Computer Architecture. MIPS Instruction Formats CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructor: Justin Hsia 6/27/2012 Summer 2012 Lecture #7 1 Review of Last Lecture New registers: $a0-$a3, $v0-$v1, $ra, $sp Also: $at,

More information

Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21

Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 2.9 Communication with People: Byte Data & Constants Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 32: space 33:! 34: 35: #...

More information

The MIPS Instruction Set Architecture

The MIPS Instruction Set Architecture The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use

More information

5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers

5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-2 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

More information

ECE331: Hardware Organization and Design

ECE331: Hardware Organization and Design ECE331: Hardware Organization and Design Lecture 15: Midterm 1 Review Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Basics Midterm to cover Book Sections (inclusive) 1.1 1.5

More information

Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011

Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011 CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-3 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

More information

Instructions: Language of the Computer

Instructions: Language of the Computer Instructions: Language of the Computer Tuesday 22 September 15 Many slides adapted from: and Design, Patterson & Hennessy 5th Edition, 2014, MK and from Prof. Mary Jane Irwin, PSU Summary Previous Class

More information

MIPS Reference Guide

MIPS Reference Guide MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

More information

Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.

More information

CS3350B Computer Architecture MIPS Introduction

CS3350B Computer Architecture MIPS Introduction CS3350B Computer Architecture MIPS Introduction Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada Thursday January

More information

Lecture 4: MIPS Instruction Set

Lecture 4: MIPS Instruction Set Lecture 4: MIPS Instruction Set No class on Tuesday Today s topic: MIPS instructions Code examples 1 Instruction Set Understanding the language of the hardware is key to understanding the hardware/software

More information

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

More information

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

More information

M2 Instruction Set Architecture

M2 Instruction Set Architecture M2 Instruction Set Architecture Module Outline Addressing modes. Instruction classes. MIPS-I ISA. High level languages, Assembly languages and object code. Translating and starting a program. Subroutine

More information

A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3

A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3 A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU

More information

Computer Architecture I Midterm I

Computer Architecture I Midterm I Computer Architecture I Midterm I April 11 2017 Computer Architecture I Midterm I Chinese Name: Pinyin Name: E-Mail... @shanghaitech.edu.cn: Question Points Score 1 1 2 12 3 16 4 14 5 18 6 17 7 22 Total:

More information

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

MIPS Coding Snippets. Prof. James L. Frankel Harvard University. Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved.

MIPS Coding Snippets. Prof. James L. Frankel Harvard University. Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved. MIPS Coding Snippets Prof. James L. Frankel Harvard University Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved. Loading a 32-bit constant into a register # Example loading

More information

Computer Architecture Chapter 3. Fall 2005 Department of Computer Science Kent State University

Computer Architecture Chapter 3. Fall 2005 Department of Computer Science Kent State University Computer Architecture Chapter 3 Fall 2005 Department of Computer Science Kent State University Objectives Signed and Unsigned Numbers Addition and Subtraction Multiplication and Division Floating Point

More information

MIPS Instruction Set

MIPS Instruction Set MIPS Instruction Set Prof. James L. Frankel Harvard University Version of 7:12 PM 3-Apr-2018 Copyright 2018, 2017, 2016, 201 James L. Frankel. All rights reserved. CPU Overview CPU is an acronym for Central

More information

ECE232: Hardware Organization and Design

ECE232: Hardware Organization and Design ECE232: Hardware Organization and Design Lecture 4: Logic Operations and Introduction to Conditionals Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Overview Previously examined

More information

MIPS Assembly Programming

MIPS Assembly Programming COMP 212 Computer Organization & Architecture COMP 212 Fall 2008 Lecture 8 Cache & Disk System Review MIPS Assembly Programming Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2

More information

Levels of Programming. Registers

Levels of Programming. Registers Levels of Programming COSC 2021: Computer Organization Instructor: Dr. Amir Asif Department of Computer Science York University Handout # 3: MIPS Instruction Set I Topics: 1. Arithmetic Instructions 2.

More information

I-Format Instructions (3/4) Define fields of the following number of bits each: = 32 bits

I-Format Instructions (3/4) Define fields of the following number of bits each: = 32 bits CS61C L10 MIPS Instruction Representation II (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #10 Instruction Representation II 2007-7-8 Review There are register calling conventions!

More information

ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design

ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 Sources: Computer

More information

Processor. Han Wang CS3410, Spring 2012 Computer Science Cornell University. See P&H Chapter , 4.1 4

Processor. Han Wang CS3410, Spring 2012 Computer Science Cornell University. See P&H Chapter , 4.1 4 Processor Han Wang CS3410, Spring 2012 Computer Science Cornell University See P&H Chapter 2.16 20, 4.1 4 Announcements Project 1 Available Design Document due in one week. Final Design due in three weeks.

More information

Chapter Three. Arithmetic

Chapter Three. Arithmetic Chapter Three 1 Arithmetic Where we've been: Performance (seconds, cycles, instructions) Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: Implementing

More information

comp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions

comp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions Procedure Calls A procedure of a subroutine is like an agent which needs certain information to perform a

More information

Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero

Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero Do-While Example In C++ do { z--; while (a == b); z = b; In assembly language loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero 25 Comparisons Set on less than (slt) compares its source registers

More information

CS3350B Computer Architecture

CS3350B Computer Architecture CS3350B Computer Architecture Winter 2015 Lecture 4.1: MIPS ISA: Introduction Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted d from lectures on Computer Organization and Design, Patterson & Hennessy,

More information

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix

More information

ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation

ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation ICS 233 COMPUTER ARCHITECTURE MIPS Processor Design Multicycle Implementation Lecture 23 1 Add immediate unsigned Subtract unsigned And And immediate Or Or immediate Nor Shift left logical Shift right

More information

Chapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes

Chapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes Chapter 2 Instructions: Language of the Computer Adapted by Paulo Lopes Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects

More information

Anne Bracy CS 3410 Computer Science Cornell University. See P&H Chapter: , , Appendix B

Anne Bracy CS 3410 Computer Science Cornell University. See P&H Chapter: , , Appendix B Anne Bracy CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. See P&H Chapter: 2.16-2.20, 4.1-4.4,

More information

CSE 141 Computer Architecture Summer Session Lecture 3 ALU Part 2 Single Cycle CPU Part 1. Pramod V. Argade

CSE 141 Computer Architecture Summer Session Lecture 3 ALU Part 2 Single Cycle CPU Part 1. Pramod V. Argade CSE 141 Computer Architecture Summer Session 1 2004 Lecture 3 ALU Part 2 Single Cycle CPU Part 1 Pramod V. Argade Reading Assignment Announcements Chapter 5: The Processor: Datapath and Control, Sec. 5.3-5.4

More information

Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology

Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology Computer Organization MIPS Architecture Department of Computer Science Missouri University of Science & Technology hurson@mst.edu Computer Organization Note, this unit will be covered in three lectures.

More information

SPIM Instruction Set

SPIM Instruction Set SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

More information

CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014

CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014 B CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014 DUE : March 3, 2014 READ : - Related sections of Chapter 2 - Related sections of Chapter 3 - Related sections of Appendix A - Related sections

More information

CS/COE1541: Introduction to Computer Architecture

CS/COE1541: Introduction to Computer Architecture CS/COE1541: Introduction to Computer Architecture Dept. of Computer Science University of Pittsburgh http://www.cs.pitt.edu/~melhem/courses/1541p/index.html 1 Computer Architecture? Application pull Operating

More information

MIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions

MIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register

More information

Introduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University

Introduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Introduction to the MIPS Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Introduction to the MIPS The Microprocessor without Interlocked Pipeline Stages

More information

Computer Organization & Design

Computer Organization & Design Computer Organization & Design Peng Liu ( 刘鹏 ) College of Information Science & Electronic Engineering Zhejiang University, Hangzhou 310027, China liupeng@zju.edu.cn Lecture 2 MIPS Instruction Set Architecture

More information

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

Computer Organization and Structure. Bing-Yu Chen National Taiwan University Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing

More information

IEEE Standard for Floating-Point Arithmetic: 754

IEEE Standard for Floating-Point Arithmetic: 754 IEEE Standard for Floating-Point Arithmetic: 754 G.E. Antoniou G.E. Antoniou () IEEE Standard for Floating-Point Arithmetic: 754 1 / 34 Floating Point Standard: IEEE 754 1985/2008 Established in 1985 (2008)

More information

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

More information

5DV118 Computer Organization and Architecture Umeå University Department of Computing Science Stephen J. Hegner. Topic 3: Arithmetic

5DV118 Computer Organization and Architecture Umeå University Department of Computing Science Stephen J. Hegner. Topic 3: Arithmetic 5DV118 Computer Organization and Architecture Umeå University Department of Computing Science Stephen J. Hegner Topic 3: Arithmetic These slides are mostly taken verbatim, or with minor changes, from those

More information

Computer Architecture. Chapter 3: Arithmetic for Computers

Computer Architecture. Chapter 3: Arithmetic for Computers 182.092 Computer Architecture Chapter 3: Arithmetic for Computers Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 2008, Morgan Kaufmann Publishers and Mary Jane Irwin

More information

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei Computer Architecture Instruction Set Architecture part 2 Mehran Rezaei Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter

More information

Number Systems Standard positional representation of numbers: An unsigned number with whole and fraction portions is represented as:

Number Systems Standard positional representation of numbers: An unsigned number with whole and fraction portions is represented as: N Number Systems Standard positional representation of numbers: An unsigned number with whole and fraction portions is represented as: a n a a a The value of this number is given by: = a n Ka a a a a a

More information

CS3350B Computer Architecture MIPS Instruction Representation

CS3350B Computer Architecture MIPS Instruction Representation CS3350B Computer Architecture MIPS Instruction Representation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada

More information

ECE331: Hardware Organization and Design

ECE331: Hardware Organization and Design ECE331: Hardware Organization and Design Lecture 8: Procedures (cont d), Binary Numbers and Adders Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Review: Procedure Calling Steps

More information

TSK3000A - Generic Instructions

TSK3000A - Generic Instructions TSK3000A - Generic Instructions Frozen Content Modified by Admin on Sep 13, 2017 Using the core set of assembly language instructions for the TSK3000A as building blocks, a number of generic instructions

More information

CS61C L10 MIPS Instruction Representation II, Floating Point I (6)

CS61C L10 MIPS Instruction Representation II, Floating Point I (6) CS61C L1 MIPS Instruction Representation II, Floating Point I (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #1 Instruction Representation II, Floating Point I 25-1-3 There is one

More information

COMPSCI 313 S Computer Organization. 7 MIPS Instruction Set

COMPSCI 313 S Computer Organization. 7 MIPS Instruction Set COMPSCI 313 S2 2018 Computer Organization 7 MIPS Instruction Set Agenda & Reading MIPS instruction set MIPS I-format instructions MIPS R-format instructions 2 7.1 MIPS Instruction Set MIPS Instruction

More information

Instructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1

Instructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1 Instructions: MIPS ISA Chapter 2 Instructions: Language of the Computer 1 PH Chapter 2 Pt A Instructions: MIPS ISA Based on Text: Patterson Henessey Publisher: Morgan Kaufmann Edited by Y.K. Malaiya for

More information

MIPS Assembly Language. Today s Lecture

MIPS Assembly Language. Today s Lecture MIPS Assembly Language Computer Science 104 Lecture 6 Homework #2 Midterm I Feb 22 (in class closed book) Outline Assembly Programming Reading Chapter 2, Appendix B Today s Lecture 2 Review: A Program

More information

EE 361 University of Hawaii Fall

EE 361 University of Hawaii Fall C functions Road Map Computation flow Implementation using MIPS instructions Useful new instructions Addressing modes Stack data structure 1 EE 361 University of Hawaii Implementation of C functions and

More information

Numeric Encodings Prof. James L. Frankel Harvard University

Numeric Encodings Prof. James L. Frankel Harvard University Numeric Encodings Prof. James L. Frankel Harvard University Version of 10:19 PM 12-Sep-2017 Copyright 2017, 2016 James L. Frankel. All rights reserved. Representation of Positive & Negative Integral and

More information

Rui Wang, Assistant professor Dept. of Information and Communication Tongji University.

Rui Wang, Assistant professor Dept. of Information and Communication Tongji University. Instructions: ti Language of the Computer Rui Wang, Assistant professor Dept. of Information and Communication Tongji University it Email: ruiwang@tongji.edu.cn Computer Hierarchy Levels Language understood

More information

We will study the MIPS assembly language as an exemplar of the concept.

We will study the MIPS assembly language as an exemplar of the concept. MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and

More information

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont ) Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise

More information

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:

More information

CSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.

CSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI. CSCI 402: Computer Architectures Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI Recall Big endian, little endian Memory alignment Unsigned

More information

ECE 15B Computer Organization Spring 2010

ECE 15B Computer Organization Spring 2010 ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 7: Procedures I Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy, and classes taught by and

More information

ece4750-tinyrv-isa.txt

ece4750-tinyrv-isa.txt ========================================================================== Tiny RISC-V Instruction Set Architecture ========================================================================== # Author :

More information

Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.

Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA. Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic

More information

Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:

Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#: Computer Science and Engineering 331 Midterm Examination #1 Fall 2000 Name: Solutions S.S.#: 1 41 2 13 3 18 4 28 Total 100 Instructions: This exam contains 4 questions. It is closed book and notes. Calculators

More information

Arithmetic. Chapter 3 Computer Organization and Design

Arithmetic. Chapter 3 Computer Organization and Design Arithmetic Chapter 3 Computer Organization and Design Addition Addition is similar to decimals 0000 0111 + 0000 0101 = 0000 1100 Subtraction (negate) 0000 0111 + 1111 1011 = 0000 0010 Over(under)flow For

More information

MIPS (SPIM) Assembler Syntax

MIPS (SPIM) Assembler Syntax MIPS (SPIM) Assembler Syntax Comments begin with # Everything from # to the end of the line is ignored Identifiers are a sequence of alphanumeric characters, underbars (_), and dots () that do not begin

More information

Format. 10 multiple choice 8 points each. 1 short answer 20 points. Same basic principals as the midterm

Format. 10 multiple choice 8 points each. 1 short answer 20 points. Same basic principals as the midterm Final Review Format 10 multiple choice 8 points each Make sure to show your work Can write a description to the side as to why you think your answer is correct for possible partial credit 1 short answer

More information

--------------------------------------------------------------------------------------------------------------------- 1. Objectives: Using the Logisim simulator Designing and testing a Pipelined 16-bit

More information

Thomas Polzer Institut für Technische Informatik

Thomas Polzer Institut für Technische Informatik Thomas Polzer tpolzer@ecs.tuwien.ac.at Institut für Technische Informatik Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq rs, rt, L1 if (rs == rt) branch to

More information

Compiling Techniques

Compiling Techniques Lecture 10: An Introduction to MIPS assembly 18 October 2016 Table of contents 1 Overview 2 3 Assembly program template.data Data segment: constant and variable definitions go here (including statically

More information

University of California at Santa Barbara. ECE 154A Introduction to Computer Architecture. Quiz #1. October 30 th, Name (Last, First)

University of California at Santa Barbara. ECE 154A Introduction to Computer Architecture. Quiz #1. October 30 th, Name (Last, First) University of California at Santa Barbara ECE 154A Introduction to Computer Architecture Quiz #1 October 30 th, 2012 Name (Last, First) All grades will be posted on the website as a single spreadsheet

More information

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

More information

Computer Architecture

Computer Architecture CS3350B Computer Architecture Winter 2015 Lecture 4.2: MIPS ISA -- Instruction Representation Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design,

More information

Anne Bracy CS 3410 Computer Science Cornell University. [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon]

Anne Bracy CS 3410 Computer Science Cornell University. [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon] Anne Bracy CS 3410 Computer Science Cornell University [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon] Understanding the basics of a processor We now have the technology to build a CPU! Putting it all

More information

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

Computer Organization and Structure. Bing-Yu Chen National Taiwan University Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing

More information

CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14

CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14 CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 13 & 14 Dr. Kinga Lipskoch Fall 2017 Frame Pointer (1) The stack is also used to store variables that are local to function, but

More information

ECE 154A Introduction to. Fall 2012

ECE 154A Introduction to. Fall 2012 ECE 154A Introduction to Computer Architecture Fall 2012 Dmitri Strukov Lecture 4: Arithmetic and Data Transfer Instructions Agenda Review of last lecture Logic and shift instructions Load/store instructionsi

More information

instructions aligned is little-endian

instructions aligned is little-endian MEMÓRIA Data Types These instructions load and store aligned data: Load word (lw) Load halfword (lh) Load halfword unsigned (lhu) Load byte (lb) Load byte unsigned (lbu) Store word (sw) Store halfword

More information

Chapter 2A Instructions: Language of the Computer

Chapter 2A Instructions: Language of the Computer Chapter 2A Instructions: Language of the Computer Copyright 2009 Elsevier, Inc. All rights reserved. Instruction Set The repertoire of instructions of a computer Different computers have different instruction

More information

Review. Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I Logical Operators (1/3) Bitwise Operations

Review. Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I Logical Operators (1/3) Bitwise Operations CS6C L9 MIPS Logical & Shift Ops, and Instruction Representation I () inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I 25-9-28

More information