CISC Processor Design

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1 CISC Processor Design Virendra Singh Indian Institute of Science Bangalore Lecture 3 SE-273: Processor Design

2 Processor Architecture Processor Architecture CISC RISC Jan 21,

3 Processor Architecture PI Controlle r Control Signals From memory Datapath Status Signals PO To memory Jan 21, 2008 SE-273@SERC 3

4 Instruction Set Instruction Set Should be complete One should be able to construct a machine level program to evaluate any function Should be efficient Frequently required functions can be completed quickly using relatively few instructions Should be regular Should contain expected opcodes and addressing modes Compatible with existing machines Jan 21, 2008 SE-273@SERC 4

5 Instruction Set Instruction Format Op-code Operands Addressing Register Specification Effective Address Implicit Reference Jan 21,

6 Micro-coded Implementation Clock-Phase Generator Bus Controller Control Store State Sequencer Control Word Decoder Controller Instruction Decoder Program Counter Registers R0 R1 Rn Shifter ALU Datapath Jan 21,

7 PLA Implementation Clock-Phase Generator PLA Bus Controller Instruction Decoder Control Word Decoder Controller Program Counter Registers R0 R1 Rn Shifter ALU Datapath Jan 21,

8 Random Logic Implementation Clock-Phase Generator Bus Controller Random Logic Controller Program Counter Registers R0 R1 Rn Shifter ALU Datapath Jan 21,

9 Micro-coded Implementation Clock-Phase Generator Bus Controller Control Store Instruction Sequencer Instruction Decoder Encoded Control Word Fields Control Word Decoder Decoded Datapath Control Instruction Prefetch Register Address Out Reg. PC R0 R1 Rn Shifter ALU Internal B Bus Datapath Internal A Bus Data Reg. Jan 21, 2008 SE-273@SERC 9

10 Instruction ADD R1, D2(B2) 5A R1 B2 D The second operand is added in the first The sum is placed in the first operand location The operand and the sum are treated as 16-bit signed binary integers The first operand is in the register specified by the R1 field The second operand is in the memory address is calculated by adding the displacement specified by the D2 field to the content of the base register specified by the B2 field Jan 21, 2008 SE-273@SERC 10

11 Execution Steps Steps for ADD instruction Execution 1. Fetch the first half word 2. Find ADD control word sequence 3. Fetch the remaining instruction word 4. Calculate the operand address 5. Fetch the operand 6. Add 7. Store the result Jan 21,

12 Execution Steps 1. Fetch the remaining instruction word 2. Calculate the operand address 3. Fetch the operand 4. Add 5. Store the result 6. Update the program counter 7. Fetch the first half word for the next instruction 8. Find the address of the next instructions control word sequence 9. Branch to the next instruction s control word Jan 21, 2008 SE-273@SERC 12

13 Execution Steps 1. Fetch the remaining instruction word One state to second half of the ADD instruction 2. Calculate the operand address One state to add D2 displacement and the content of the B2 register 3. Fetch the operand One state to fetch the data half word (put the address on the pads and wait for the operand half-word) 4. Add One state to add the operands 5. Store the result One state to store the result in Register R1 Jan 21,

14 Execution Steps 6. Update the program counter One state to increament PC One state to save the incremented value 7. Fetch the first half word for the next instruction One state to put the PC value on the pads and wait for the first half of the next instruction 8. Find the address of the next instructions control word sequence One state to put the next instruction into the instruction decoder 9. Branch to the next instruction s control word Zero state this step is accomplished as a part of the previous step Jan 21, 2008 SE-273@SERC 14

15 Processor - Block Diagram Clock-Phase Generator Reset & Power-On Logic Bus Controller Interrupt Logic Control Store Next State Control Branch Control unit IR Decoder Encoded Control Word Fields Control Word Decoder Decoded Datapath Control Instruction Prefetch Register Address Out Reg. PC R0 R1 Internal A Bus Rn Shifter ALU Internal B Bus Datapath Data Reg. Jan 21, 2008 SE-273@SERC 15

16 Thank You Jan 21,

CISC Processor Design

CISC Processor Design CISC Processor Hardware Flowchart Virendra Singh Indian Institute of Science Bangalore virendra@computer.orgorg Lecture 4 SE-273: Processor Processor - Block Diagram Clock-Phase Reset & Power-On Logic