Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26)

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1 Lecture Topics Today: Integer Arithmetic (P&H ) Next: continued 1 Announcements Consulting hours Introduction to Sim Milestone #1 (due 1/26) 2 1

2 Overview: Integer Operations Internal representation unsigned integers signed integers Operations arithmetic operations bitwise operations shift operations 3 Unsigned Integers Expressed in base 2, with leading zeroes Set of values starts at zero, limited by number of bits available for storage Example: 8-bit bytes min: max: (2 8 1) 4 2

3 Assuming 16 bits: Signed Integers Several different systems developed: Sign and magnitude (signed magnitude) One s complement Two s complement Half of the bit patterns are used to represent negative numbers 6 3

4 Two s Complement Negative representation formed by applying two s complement operation to all bits in positive representation (flip all bits, add 1) Example (assume 8 bits): Two s Complement Range (assume 8 bits): max (2 7 1) min (2 7 ) One representation of zero (assume 8 bits):

5 Assuming 16 bits: Example: -21 base 10 Internal representation (8 bits): +21: flip bits: add 1: 1-21:

6 Example: -22 base 10 Internal representation (8 bits): +22: flip bits: add 1: 1-22: Example: -0 base 10 Internal representation (8 bits): +0: flip bits: add 1: 1-0:

7 Comparison: Unsigned vs Signed unsigned twos comp Summary: Signed Integers Two's complement representation used on most microprocessors In C/C++, type "int" is typically 32 bits wide ~cse420/examples/example

8 Operations on Integers Arithmetic operations: addition, subtraction multiplication, division Bitwise (logical) operations: AND, OR, XOR, Shift operations: SLL, SRL, SRA, 15 Bitwise Operations Almost all processors support: AND OR XOR Some processors support additional ops: NAND, NOR ANDN, ORN, XORN 16 8

9 Ex: Assume 8-bit Operands AND OR XOR Ex: Assume 8-bit Operands A B NAND NAND A B NOR NOR

10 Other Bitwise Operations Some processors support versions of AND, OR, XOR where the second operand is inverted: P ANDN Q = P AND ~Q P ORN Q = P OR ~Q P XORN Q = P XOR ~Q Integer circuits usually already have logic to invert the second operand (for subtraction) 19 Ex: Assume 8-bit Operands A B ANDN ANDN A B ORN ORN

11 Bitwise Circuits Example: 8-bit AND A 7 B 7 R 7 A 6 B 6 R 6 A B R A 1 B 1 R 1 A 0 B 0 R 0 21 Shift Operations Almost all processors support: SLL (shift left logical) SRL (shift right logical) SRA (shift right arithmetic) Some processors support additional ops: ROL (rotate left) ROR (rotate right) 22 11

12 Shift Operations Shift operations move bit patterns to the left or the right within a register. Example (assuming 8 bits): SLL 2: Shift count: 0 to N-1 (where N is number of bits) 23 Shift Left Logical (SLL) Move bit pattern to the left, fill with zeroes on the right. Examples (assuming 8 bits): SLL 1: SLL 5:

13 Shift Right Logical (SRL) Move bit pattern to the right, fill with zeroes on the left. Examples (assuming 8 bits): SRL 1: SRL 5: Shift Right Arithmetic (SRA) Move bit pattern to the right, fill with copies of the sign bit on the left. Examples (assuming 8 bits): SRA 1: SRA 5: SRA preserves the original sign of the value

14 Shift Circuits Logarithmic shifter: for N bit register, use log 2 N levels of multiplexers Example: 8 bit register ==> 3 levels 1 st level shift 4 bits 2 nd level shift 2 bits 3 rd level shift 1 bit 27 8-bit Right Logical Shifter 28 14

15 Combined Shift Circuits Control signal (2 bits): No shift Shift left logical Shift right logical Shift right arithmetic 29 Rotate Operations Rotate operations move bit patterns to the left or the right within a register; bits are rotated to the other end of the register. Example (assuming 8 bits): ROL 2: Count: 0 to N-1 (where N is number of bits) 30 15

16 Rotate Left (ROL) Move bit pattern to the left; bits which move "off the end" are rotated to the right. Examples (assuming 8 bits): ROL 1: ROL 5: Rotate Right (ROR) Move bit pattern to the right; bits which move "off the end" are rotated to the left. Examples (assuming 8 bits): ROR 1: ROR 5:

17 8-bit Right Rotator 33 8-bit Right Shifter and Rotator 34 17

18 Arithmetic Operations Almost all processors support: Addition Subtraction Most processors support additional ops: Multiplication Division 35 Two s Complement Addition Addition of two s complement values is the same as addition of unsigned values One approach: ripple carry addition: carry bits

19 Full Adder Cin A B Cout S(um) A B Full Adder Cout S Cin 37 Ripple-Carry Adder (4 bits) A3 B3 A2 B2 A1 B1 A0 B0 A B A B A B A B Carry Cout FA Cin Cout FA Cin Cout FA Cin Cout FA Cin S S S S S3 S2 S1 S

20 Example: (+5) + (+6) (+5) (+6) (+11) Example: (+5) + (-6) (+5) (-6) (-1)

21 Example: (-5) + (-6) (-5) (-6) (-11) Example: (-5) + (+6) (-5) (+6) (+1)

22 Summary (+5) (+6) (+11) (+5) (-6) (-1) (-5) (-6) (-11) (-5) (+6) (+1) Overflow Overflow occurs when the result is too large Result would be OK if there were more bits available to store the sum

23 Detecting Overflow Human: sign of result is different than sign of operands (overflow cannot occur if signs of operands are different) Machine: carry into most significant bit (sign bit) is different than carry out of MSB Test: C n-2 XOR C n-1 45 Examples: overflow overflow

24 Examples: (+5) (+6) (+11) (+5) (-6) (-1) (-5) (-6) (-11) (-5) (+6) (+1) Two s Complement Subtraction One approach: circuit to perform ripple borrow subtraction Alternative: use existing ripple carry adder A - B = A + (-B) = A + (~B + 1) Negate B by flipping all the bits, adding

25 Ex: (+5) - (+6) = (+5) + (~6+1) (+5) (~6) (-1) Ex: (-5) - (+6) = (-5) + (~6) (-5) (~6) (-11)

26 Combined Adder/Subtractor (4 bits) B3 B2 B1 B0 SUB A3 A2 A1 A0 A B A B A B A B Carry Cout FA Cin Cout FA Cin Cout FA Cin Cout FA Cin S S S S S3 S2 S1 S0 SUB control signal: 0 means Add, 1 means Subtract 51 Arithmetic Operations Assume two s complement for signed integers Addition: ripple-carry adder (or faster alternative) Subtraction: variation on addition Multiplication: sequential logic Division: sequential logic 52 26

27 Integer Circuits Math unit: addition and subtraction bitwise operations Shift unit: shift operations Multiply and Divide unit: multiplication and division 53 MIPS Math Unit Inputs: 32-bit operands 4-bit operation code Outputs: 32-bit result 1-bit zero flag 1-bit overflow flag 54 27