Department of Electrical and Computer Engineering Introduction to Computer Engineering I (ECSE-221) Assignment 3: Sequential Logic

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1 Available: February 16, 2009 Due: March 9, 2009 Department of Electrical and Computer Engineering (ECSE-221) Assignment 3: Sequential Logic Information regarding submission and final deposition time can be found on the WebCT site. Question 1 This question will investigate properties of the basic flip-flop types encountered in Module 3. a. Implement a J-K edge-triggered flip-flop using the S-R edge-triggered model shown on Page 24 of the notes as the starting point. Using Logicworks, empirically determine Tsu, Th, and Tpd for this design. b. Convert the J-K edge-triggered flip-flop to a D. Using the same approach as in Part a, determine Tsu, Th, and Tpd for this flip-flop. c. Implement a master-slave D flip-flop starting with S-R master-slave in the notes. Repeat Part b and determine Tsu, Th, and Tpd. d. What are the essential differences between the edge-triggered and master-slave D flipflop designs? Question 2 It s now May, you ve passed the course and managed to land a job at a company that designs and builds digital control systems. They hand you a printed circuit board that was pulled out of a 35 year old system and ask you to re-implement the circuit using current technology. There is no question of replacing the entire system - it has a 50 year lifetime, but the circuit board they handed you is completely fried (literally) and has to be replaced. Unfortunately there are absolutely no replacement parts or documentation available (the manufacturer is out of business). Your job - reverse engineer the circuit so that a new one may be fabricated. The board is implemented using 7400 transistor-transistor logic (TTL). You manage to find a TTL data book and determine that the circuit is comprised of J-K flip-flops and a variety of logic gates.. After poring over the board for a day you trace out the circuit diagram shown below in Figure 2.1. You are now ready to reverse engineer the circuit. a. The first step is to determine the 6 flip-flop equations corresponding to J0, K0, J1, K1, J2, and K2 respectively. This is accomplished by tracing through the schematic. Next derive the next-state equation corresponding to each flip-flop, and use these equations to fill in the state transition table corresponding to the circuit. Also produce the corresponding state diagram. b. The state transition table describes the logical behaviour of the circuit, but does not provide any information about timing. You look up the specifications for the circuit components and determine that the flip-flops have set-up, hold, and propagation delay 1/23

2 times of 1nS, 1nS, and 5 ns respectively. Tpd for AND gates is 1 ns and Tpd for OR is 3 ns; inverter bubbles add 0.5 ns to Tpd. Use this information to determine the maximum operating frequency of the circuit and to produce a detailed timing diagram showing the relationship of the Q0, Q1, and Q2 outputs to the clock and M inputs. Question 3 Figure 2.1 Now that you have completed your analysis of the circuit, re-implementation can be pursued. Two approaches will be considered, one involving a hardware solution and the other a software solution. a) Design an implementation of the circuit using a PROM and register. Prove that your implementation is correct by devising a LogicWorks simulation that drives the circuit through all transitions in the state transition table (i.e. show the correct sequences of states for input M=0 and M=1). Assuming that your register has identical timing parameters to the J-K flip-flops used in the circuit, what should the access time be for the PROM so that the circuit has the same maximum operating frequency? b) Even though the circuit is capable of switching in excess of 10 Mhz, the actual clock is fixed at 10 Khz. At this rate the entire circuit can easily be replaced by a $1.00 microcontroller chip. Write a "C" function that implements the state machine corresponding to the circuit according to the following prototype. void StateMachine (char M, char *Q2, char *Q1, char *Q0); You may assume that this routine is called periodically every 100 us. Show that your code implements the state machine correctly by writing a suitable test routine that shows the correct sequence of states for M=0 and M=1. 2/23

3 Question 4 (Bonus) The circuit shown below computes the sum of integers from 1 to N, i.e., N " i. i=1 counter register Figure 4.1 Operation is as follows. The counter is loaded with a value of N in the range [1,15] and proceeds to count down to 0. So if, for example, the counter was loaded with 6, the sequence 6,5,4,3,2,1,0 would be generated. To accumulate the sequence, an 8-bit full-adder and an 8 bit register are connected to the counter as shown in the figure. 8-bits are required since the maximum sum for N=15 is 120. a) The counter serves to generate the number sequence and to control the datapath (full adder + register). Design an appropriate counter module using the LogicWorks standard 4-bit counter. Hint: the enable input can be used to stop the counter when it reaches zero; the load input can be used to start the count off by loading a non-zero value in the range [1,15]. Show that this module works with a LogicWorks simulation. b) The data path can be fabricated using the built-in 8-bit full adder along with an 8-bit register. There is a subtlety here, however. Every time a new number is loaded into the counter, we want the register to be cleared to 0. Unfortunately you cannot use the clear input of the register to do so (recall it can only be used to initialize the register on power on). In connecting the output of the adder to the register, you need to add some combinational logic that can force the inputs to 0 every time the counter is loaded. Taking all of this into account, implement your circuit and verify correct operation with a LogicWorks simulation. c) Assuming all register inputs have Tsu = 1nS, Th = 0nS, Tpd = 3nS and that all combinational logic gates have Tpd = 0.5nS, estimate the maximum operating frequency of your implementation assuming the full adder is implemented according to the notes in Module 2. FPF/February 16, /23

4 Question 1a The J-K version of the edge-triggered flip-flop is shown below. To fully evaluate Tsu and Th for this circuit, we would have to test for all 8 cases outlined in the state transition table. Because toggle mode involves the longest feedback path, we approximate by considering J=K=1 for Q=0 and Q=1. Important Note: All gate delays should be set to the identical Tg. Here we chose 10nS, largely for convenience in displaying the traces. For example, a delay of 30nS corresponds to 3Tg. Set-up time Tsu: Start off with Tsu = 3 Tg and decrease from 3 to 1. The first simulation shows transitions from Q=0 to Q=1, and the second from Q=1 to Q=0. 4/23

5 Question 1 cont. Timing file, Tsu, Q: 0 1 Simulation, Tsu, Q: 0 1 Observations: The simulation works for Tsu = 3 Tg, but fails for Tsu = 2 Tg, Here 1 Tg is 10 nanoseconds. 5/23

6 Question 1 cont. Timing file, Tsu, Q: 1 0 Observations: Simulation, Tsu, Q: 1 0 The behaviour is symmetric with respect to the first test. A similar failure with Tsu = 2 Tg is observer. Based on these results we conclude that Tsu = 3 Tg. 6/23

7 Hold Time Th: A similar strategy as used for set-up time is followed here. We start with Th = 2 Tg and decrease to 0. Timing file, Th, Q: 0 1 Observations: No failures for any value of Th. Simulation, Th, Q: 0 1 7/23

8 Timing file, Th, Q: 1 0 Simulation, Th, Q: 1 0 Observations: No failures for any value of Th. Based on these results we conclude that Th = 0 Tg. Propagation Delay Tpd: Tpd can be read off any of the working transitions. From the above timing diagram, Tpd = 3 Tg. 8/23

9 Question 1b The test circuit for this question is shown below. T su T pd In the upper timing diagram above, T h is set to span most of the clock period, so that it is effectively guaranteed to exceed the minimum. T su is then varied from 4 T g to 2 T g for both D=1 and D=0. Notice that the flip-flop breaks down with T su = 3 T g with D=0. Hence T su = 4 T g. T pd = 3 T g as read from the diagram. 9/23

10 T h is verfied in the second simulation above. Here T su is held fixed at 4 T g and T h varied from 3 T g to 0. Since the device is still functional at 0, we may conclude that T h = 0. The corresponding timing files are shown below, (L) for the upper simulation and (R) for the lower one. $T $D $I Clr $I C $I D $T $D $I Clr $I C $I D /23

11 Question 1c The test circuit for this question is shown below. T h T pd T su The upper timing diagram shows operation of the master-slave D-FF with T su = 2 T g and T h = 0. Correct operation is expected since T su is the hold time for a latch which is 2 T g ; hold time for the master-slave is 0, which is verified in the timing diagram. The lower timing diagram shows what happens when T su is violated in this case reduced to 1 T g. T pd can be read off the upper timing diagram - it has a worst cast value of 4 T g. 3 is the expected value, but this is for the case of an inverter with 0 delay. Since the inverted used in the circuit has a 1 T g propagation delay, T pd for the master-slave is increased by 1. The corresponding timing files are shown below for the upper (L) and lower (R). 11/23

12 $T $D $I Clr $I C $I D $T $D $I Clr $I C $I D Question 1d Aside from differences in values of T su, T h, and T pd, there is no way to tell a MS D-FF from an ET D-FF. In fact, both implementations can be simplified into the same equivalent circuit. 12/23

13 13/23

14 14/23

15 15/23

16 16/23

17 Question 3a ROM program = RHS of state transition table {4, 5, 6, 0, 2, 7, 1, 3, 3, 6, 4, 7, 0, 1, 2, 5}. 17/23

18 Question 3a cont. Timing File 18/23

19 Question 3b /* */ /* Software implementation of a state machine. */ /* */ /* A state machine can be implemented in software just as easily */ /* as hardware. The basic constraint is speed! In hardware the */ /* clocking interval is the sum of the register set-up time, */ /* propagation delay, and combinational logic delay. In software */ /* this interval is determined by the execution speed of the program. */ /* For example, an 8051 microcontroller running at 12Mhz could */ /* probably implement the state machine in Question 2c at several */ /* Mhz depending on the compiler and/or assembly code. */ /* */ #include <stdio.h> void StateMachine(char M, char *Q2, char *Q1, char *Q0); void main(int argc, char *argv[]) { char M, Q2, Q1, Q0, i; printf("demonstration of a state machine implemented in software.\n\n"); printf("operation with M=0\n\n"); printf(" M Q2 Q1 Q0 Q2^ Q1^ Q0^\n\n"); M=0; Q2=0; Q1=0; Q0=0; for (i=0;i<8;i++) { printf(" %1d %1d %1d %1d", M, Q2, Q1, Q0); StateMachine(M,&Q2,&Q1,&Q0); printf(" %1d %1d %1d\n",Q2,Q1,Q0); } printf("\n\noperation with M=1\n\n"); printf(" M Q2 Q1 Q0 Q2^ Q1^ Q0^\n\n"); M=1; Q2=0; Q1=0; Q0=0; } for (i=0;i<8;i++) { printf(" %1d %1d %1d %1d", M, Q2, Q1, Q0); StateMachine(M,&Q2,&Q1,&Q0); printf(" %1d %1d %1d\n",Q2,Q1,Q0); } 19/23

20 /* */ /* The actual state machine code is noting more than a table lookup. */ /* */ void StateMachine(char M, char *Q2, char *Q1, char *Q0) { static char Q2table[] = {1,1,1,0,0,1,0,0,0,1,1,1,0,0,0,1}; static char Q1table[] = {0,0,1,0,1,1,0,1,1,1,0,1,0,0,1,0}; static char Q0table[] = {0,1,0,0,0,1,1,1,1,0,0,1,0,1,0,1}; int index; index = (M<<3)+(*Q2<<2)+(*Q1<<1)+*Q0; } *Q2=Q2table[index]; *Q1=Q1table[index]; *Q0=Q0table[index]; Demonstration of a state machine implemented in software. Operation with M=0 M Q2 Q1 Q0 Q2^ Q1^ Q0^ Operation with M=1 M Q2 Q1 Q0 Q2^ Q1^ Q0^ /23

21 Question 4 a) Control using programmable counter Counter implementation is straightforward using the standard LogicWorks programmable counter. The counter counts down as long as EN=1. The 4-input NOR is used to decode [0,0,0,0] which subsequently sets EN=0, halting the count. The only tricky part is synchronizing the keypad to the clock. This is accomplished with an edge-triggered D flip-flop and shows a use of the asynchronous inputs other than initializing the flip-flop on power on. When a key is pressed, the Str signal goes high momentarily, setting LD=0 until T pd beyond the next rising clock edge. Timing Diagram: 21/23

22 Question 4 b) System implementation The datapath follows directly from the block diagram in the assignment sheet. The only trick involves clearing the accumulator register every time a new argument is read in. This is accomplished using the LD signal and the 2-port, 8-bit register in a3lib. When LD=0, S=1 which selects from Port B. The counter needs only to count down to zero and remain. Further clock pulses only add 0 to the sum. 22/23

23 Question 4 Timing diagram showing input = 15. A timing file was used to clock the circuit and produce the keyboard strobe so that the output could be recorded. The result, 0x78, is produced after 16 clock pulses. The timing file is on the next page. 23/23

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