Chapter 3 Part 1 Combinational Logic Design

Size: px

Start display at page:

Download "Chapter 3 Part 1 Combinational Logic Design"

Christal Boyd
5 years ago
Views:

1 Universit of Wisconsin - Madison EE/omp Sci 352 igital Sstems undamentals Kewal K. Saluja and Yu Hen Hu Spring 22 hapter 3 Part ombinational Logic esign Originals b: harles R. Kime and Tom Kamisnski Modified for course use b: Kewal K. Saluja and Yu Hen Hu esign Hierarch ombinatorial ircuits combinatorial logic circuit has: set of moolean inputs, set of noolean outputs, and n switching functions mapping the 2 n input combinations to a output such that the current output depends onl on the current inputs. block diagram: m oolean Inputs ombinatorial Logic ircuit n oolean Outputs hapter 3-2 Hierarchical esign The function mapping inputs to outputs ma be ver comple To control compleit, we decompose the function into smaller pieces called blocks The blocks are subdivided into finer blocks The "leaves in the hierarch are called primitive blocks Eample: 6 input parit tree Top Level: 6 inputs, one output 2nd Level: ive 4-bit parit trees in two levels 3rd Level: Three 2-bit eclusive-or functions Primitive level: our 2-input NNs The design requires = 6 two-input NN gates Reusable unctions and esign Whenever possible, we tr to decompose a comple design into common, reusable function blocks These blocks are tested and well documented omputer-aided design () tools might include them in libraries omputer-aided manufacturing (M) tools might know how to manufacture and test them Other tools: Schematic apture Logic Simulators Timing Verifiers Hardware escription Languages (HL) hapter 3-3 hapter 3-4 Top-own verses ottom-up nalsis Procedure Top-owndesign proceeds from an abstract, high level specification to a more and more detailed design b decomposition and successive refinement ottom-updesign starts with detailed primitive elements and combines them into larger and larger and more comple functions esigns usuall proceed from both directions simultaneousl Top-owndesign answers: What are we building? ottom-updesign answers: How do we build it? Top-own controls compleit while ottom-up "sweats" the details hapter 3-5 Switching unctions from Logic iagrams Given a logic diagram, the analsis process provides a set of oolean equations, a truth table, or a verbal eplanation of circuit behavior. Procedure:.etermine that the circuit is combinational (no feedback loops), then: 2.Identif and label all gate outputs that are a function of the input variables. Obtain the oolean functions for these labeled gate outputs. 3.Identif and label all gate outputs that are a function of inputs or previousl labeled gates. Obtain oolean functions for them. 4.Repeat Step 2 until all outputs are completed. 5.ack substitute until all functions are specified in terms of inputs onl. hapter 3-6

2 nalsis Eample nalsis (ontinued) Step 2: Label all outputs of gates near inputs. Write oolean equations for them: T = + T 2 = E E E T T2 T E T2 Step 3: Identif and label all gate outputs that are a function of inputs or previousl labeled gates. Obtain oolean functions for them. T3 = + T2 Step 4: Repeat Step 3 until all done T4 = T T3 = + T4 T3 T4 hapter 3-7 hapter 3-8 nalsis (ontinued) nalsis Eample: ode onverter T T2 E Step 4: ack substitute until all functions are specified in terms of inputs onl = + T4 T4 = T T 3 = + T2 T2 = E T = + Substituting: T3 = + ( E) T4 = ( + ) (+ ( E)) = + ( + ) ( + ( E)) T3 T4 hapter w Step 2: Label gates derived from inputs and develop oolean functions. Step 3: Label the net stage of gates and develop oolean functions. z hapter 3- ode onverter nalsis (ont.) The process terminates with all gate outputs defined. Proceeding with Step 4, substituting, Truth Tables from Logic iagrams. etermine the number of input variables, n. There will be 2**n input vectors from zero to (2**n) -. Enter them in the table. 2. Label the outputs of selected gates with smbols and enter a column for each one in the table. 3. Obtain the truth table for the outputs of those gates that are a function of onl input variables. 4. Proceed to fill in the outputs of all gates that are derived from inputs and previousl calculated terms. hapter 3- hapter 3-2 2

3 Truth Tables from Logic iagrams Procedure: etermine the number of input variables, n. There will be 2 n input vectors from zero to 2 n. Enter them in the table. Label the outputs of selected gates with smbols and enter a column for each one in the table. Obtain the truth table for the outputs of those gates that are a function of onl input variables. Proceed to fill in the outputs of all gates that are derived from inputs and previousl calculated terms. Eample: ind the function table for the code converter. ode onverter Truth Table our inputs give 6 input vectors. Start with, and z. 2 w z hapter 3-3 hapter 3-4 Truth Table ill-in omplete Entries Now we can calculate,, and 2. 2 w z inall we can fill in w to complete the table: 2 w z hapter 3-5 hapter 3-6 What oes the ircuit o? inal Note (and warning) inspection, the output variable vector (w,,,z) is just the input variable vector (,,,) plus three. The function(s) (,,,) = (w,,,z) are: " THREE TO THE INPUT VETOR unction has the meaning: " ONE TO THE UPPER TWO ITS Similarl, function 2 has the meaning: " ONE TO THE UPPER IT" Generall, it is not this obvious to figure out what the functions mean! hapter 3-7 The use of "on't ares" in the original specification can cloud the analsis. Note that the functions for the "w" bit differ from the implementation in E. 3-2 of the book. The book used "on't ares" to simplif the logic. The eample here did not. This can be seen w b inspecting the two K-maps for the function w: ook ig. 4-8 w Notes Eample hapter 3-8 3

4 Logic esign: unctional locks nalsis: rom a design to a specification of the behavior Logic diagram to equations Logic diagram to function table "Word description" of circuit operation esign and Snthesis: rom a specification to design implementation efine the problem Generate function table or equations Minimize the oolean function Implement the circuit hapter 3-9 ombinatorial Logic Implementation combinatorial logic circuit has: set of moolean inputs, set of n oolean outputs, and function mapping inputs to outputs. We think of the function as n separate oolean functions of m inputs Procedure: Treat each output as a separate function Minimize the equations for each function Implement each function independentl Sometimes an implementation can share product or sum logic terms to arrive at a lower literal cost solution. hapter 3-2 esign Procedure ode onverter esign Eample irst, start with the specification of the circuit to be designed. Note: this can sometimes require a lot of work to complete the specification process, especiall if it is poorl specified initiall. Second, follow these steps: We will stud the design of a code converter to see these steps. Identif the inputs and outputs erive truth table Obtain simplified oolean equations raw the logic diagram heck our work to verif correctness. hapter 3-2 code converter transforms one internal representation of data to another We will start with a table of the desired conversion and minimize the resulting multiple output oolean function Sometimes terms can be shared to minimize the implementation cost The Problem: esign a to Ecess-3 code converter Specification: code -- 4-bit patterns "" to "" for digits to 9 base Ecess-3 -- code plus binar "" for digits to 9 base hapter 3-22 Eample: to Ecess 3 Eample (ont.): to Ecess 3 unction table: Note: Input Output Ecess-3 w z Map functions and find minimum cost SOP equations for each z w ll codes greater than "9" can be assigned "on't ares" in the K-Map. Such codes are never possible. hapter 3-23 hapter

5 Eample (ont.): to Ecess 3 Net, we will manipulate the equations to epose some shared terms: n lternative: to Ecess 3 nother pproach: Ecess-3 is defined as plus 3. dding 3 to to Ecess-3: The term ( + ) can be used more than once to simplif the implementation See ig. 3- in Mano and Kime for the implementation hapter w z Here H is a Half-dder and is a ull-dder (We will discuss these later in the chapter). hapter 3-26 "" "" o i H S o H S o i S o H w z S unctional lock: ecoders 2-to-4 Line ecoder ecoder converts n binar bits to a maimum of 2n unique output lines. This device takes: n=2 input lines n m-to-n line decoder, where m < 2 n, can be used to: Generate 2 n (or fewer) minterms, and decodes minterms for: m=2 n = 4 output lines. Select one-of 2 n items ecoders are sometimes known as demultipleers when enabled with a separate data-in line. hapter 3-27 hapter to-4 Line emultipleer Eample: 7438 emultipleer This device takes: n=2 input lines and decodes minterms for: m=22 =4 output lines where each output is: Ned with an input,. If is viewed as an Enable, all outputs are for = and one output is for =. If is viewed as ata, then this data is sent to one or the outputs. Enables Inputs 7438 truth table: E E2 E3 z Outputs Note: This "Truth Table" uses the (or - )to mean "this could be either or ". Thus, it "compacts" some of 2 6 = 64 lines. hapter 3-29 hapter 3-3 5

6 Implementing Logic with ecoders Eample : (,) = m(,3) ecoders provide minterms directl. Simpl "OR" the appropriate minterm outputs to make an logic function desired. ctive low decoders behave as the first NN gate in a NN-NN, Sum of Products implementation. or this we use a 2-to-4 line decoder and sum minterms and 3 with an OR gate: m3 ctive high decoders behave as first stage N gates in a N-OR Sum of Products implementation. Two or more active high decoders driven from different bits of a binar code can be used to form minterms b "NING" their outputs. Similarl, active low decoders can be used to form minterms b "ORING" their outputs. m hapter 3-3 hapter 3-32 Eample : (,Y,Z) = m(,3,5,6) Implementing Larger Minterms Minterm m5 is formed b "NING" the 3 outputs of each decoder. Similarl m is formed b "NING" the outputs of each decoder. S S S S What minterm is formed b "NING" (upper) and 2 (lower) outputs? This works best with widel scattered, sparse minterms. m5 m?? m hapter 3-33 hapter 3-34 unctional lock: Encoders Encoder Eample Encoders perform the "inverse" operation of decoders, taking a code in one format and encoding it into another format. Man encoders consist of just OR gates. or eample an 8- to-3 binar encoder consists of three 4-input OR gates, OR2,OR and OR. Input Ii, i =,,7 is connected to an input on ORj if the binar representation of i has a in position j. priorit encoder is used to generate a code for the "most significant" bit set in a string of bits. This can be used to find the first one in a word, or to select eternal events in priorit order. n eample of a MSI priorit encoder is the 7448, 8 line to 3 line priorit encoder. It can be cascaded to encode higher numbers of bits. hapter 3-35 Encode 4 lines,, 2, 3 into the corresponding binar codes. hapter

7 Review: ecoders and Encoders Multipleers ecoder converts n binar bits to a maimum of 2 n unique output lines. ecoders are sometimes know as demultipleers when enabled with a separate data-in line. ecoders implement minterms directl. Use a decoder and an OR gate to form Sum-of- Minterms directl. Encoders perform the "inverse" operation of decoders, taking a code in one format and encoding it into another format. Multipleer (MU) is another common functional block. Multipleer uses n binar select bits to choose from a maimum of 2 n unique input lines. Like a decoder, it decodes minterms internall. Unlike a decoder, it has onl one output line. The decoded minterms are used to select data from one of up to 2 n unique data input lines. The output of the multipleer is the data input whose inde is specified b the n bit code. hapter 3-37 hapter 3-38 Eample: 4-to- multipleer Multipleer Versus ecoder The 4-to- line Multipleer uses the same minterm decoder core. It is like a demultipleer with individual data input lines (instead of just one) and an output OR gate. I3 I2 I I S S I3 I2 I I S S Note how similar the two are internall. hapter 3-39 hapter 3-4 unctions with Multipleers Eample: Gra to inar ode It is possible to implement an oolean function of n variables with a 2 n input multipleer. Simpl tie each input to the "" or "" line as desired. It is also possible to implement an n+ variable function with a 2 n multipleer. Simpl use the (n+)st variable in true or complement form depending upon what the truth table requires. oolean function of more than n variables can be partitioned into several easil implemented sub-functions defined on a subset of the variables. The multipleer will then select among these sub-functions. The Gra code has adjacent elements separated b onl one bit change. We wish to convert a 3-bit Gra code to a binar code. The function table on the right documents the required conversion. Gra inar z The Gra to inar ode onverter requires us to implement three separate, three-input oolean functions. hapter 3-4 hapter

8 Gra to inar (ontinued) Gra to inar (ontinued) irst step: Let's get the function table into a logical order b reordering the input Gra code values in binar sequence: inspection: = (,,) = m(, 3, 5, 7) = G(,,) = m(, 2, 5, 6) z = H(,,) = m(, 2, 4, 7) Gra inar z The K-Maps Z Y Note: (,,) =, is an eas function to implement. (No logic gates needed!) unction (,,) = ' + ' is a bit harder to implement. unction z(,,) looks familiar. What is it? hapter 3-43 hapter 3-44 Gra to inar (ontinued) Other MU Implementations We know that 2n to Multipleers can be used to implement arbitrar functions of n bits. We simpl connect the inputs to "" or "" 7 as needed. 7 Use two eight-input multipleers to implement functions for and z: S2 S S Out 8-to- MU In this case, the MU elements are acting like a "Read Onl Memor" (ROM). Z S2 S S Out 8-to- MU Y We can also use two 4-to- MU blocks and implement and z. Suppose we factor out and use and as the select inputs to the multipleers Y Z hapter 3-45 hapter 3-46 MU Implementations (ont.) MU: (ont.) actoring Out actoring out variable leads to the following implementation with two, 4-to- Multipleers: ' ' 3 2 S S Out 4-to- MU s before, =. Z 3 2 S S Out 4-to- MU Y We could have factored out other variables. s in the book, we will factor out and appl to the select inputs: Gra inar z = = = = = ' = ' 2 = 2 = 2 = ' 3 = 3 = ' 3 = This is slightl larger than selecting to factor out. hapter 3-47 hapter

9 MU: (ont.) actoring out MU: (ont.) actoring out Gra inar z = "" = z = = "" = ' z = ' = "" = z = ' = "" = ' z = Note: We re-arranged the table (fiing and and varing from to in each cell) to simplif this procedure. It still looks like factoring was better. Gra inar z = = = = = = ' 2 = 2 = 2 = ' 3 = 3 = 3 = Note: We re-arranged the table (fiing and and varing from to in each cell) to simplif this procedure. actoring is best! Note also that = holds. hapter 3-49 hapter 3-5 Summar nalsis orward backward trace through the circuit to obtain output equations or truth table Vice versa will also find the equations and truth table Know the functions performed b the following functional blocks: ecoders, emultipleers, Encoders, Multipleers Know how to implement oolean functions using: Multipleers ecoders hapter 3-5 9

Functional Block: Decoders

Functional Block: Decoders University of Wisconsin - Madison EE/omp Sci 352 Digital Systems Fundamentals harles R. Kime Section 2 Fall 2 hapter 3 ombinational Logic Design Part 2 Tom Kaminski & harles R. Kime harles Kime & Thomas