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2 When the signs of A and B are same, add the two magnitudes and attach the sign of result is that of A. When the signs of A and B are not same, compare the magnitudes and subtract the smaller number from the larger. Choose the sign of the result to be the same as A, if A > B or the complement of the sign of A if A < B. If the two magnitudes are equal, subtract B from A and make the sign of the result will be positive. Figure: Hardware Architecture for Addition and Subtraction of Signed-Magnitude Numbers Figure: Flowchart 2. Multiplication

3 With Signed 2 s Complement Data: Signed-Magnitude complements: Multiplication of two fixed-point binary numbers in signed magnitude representation is done with paper and pencil by a process of successive shift and adds operations. This process is best illustrated with a numerical example: This process looks at successive bits of the multiplier, least significant bit first. If the multiplier bit is 1, the multiplicand is copied as it is; otherwise, we copy zeros. Now we shift numbers copied down one position to the left from the previous numbers. Finally, the numbers are added and their sum produces the product. When multiplication is implemented in a digital computer, we change the process slightly. Here, instead of providing registers to store and add simultaneously as many binary numbers as there are bits in the multiplier, it is convenient to provide an adder for the summation of only two binary numbers, and successively accumulate the partial products in a register. Second, instead of shifting the multiplicand to left, the partial product is shifted to the right, which results in leaving

4 the partial product and the multiplicand in the required relative positions. Now, when the corresponding bit of the multiplier is 0, there is no need to add all zeros to the partial product since it will not alter its value. The hardware for multiplication consists of the equipment given in below Figure. Multiplicand B = E A Q SC Multiplier in Q Q n = 1; add B First partial product Shift right EAQ Q n = 1; add B Second partial product Shift right EAQ Q n = 0; shift right EAQ Q n = 0; shift right EAQ Qn = 1; add B Fifth partial product Shift right EAQ Final product in AQ = Table: Numerical Example for Binary Multiplier Booth s Multiplication Algorithm (signed-2 s complement): If the numbers are represented in signed 2 s complement then we can multiply them by using Booth algorithm. In fact the strings of 0's in the multiplier need no addition but just

5 shifting, and a string of l's in the multiplier from bit weight 2 k to weight 2 m can be treated as 2 k+1-2 m. For example, the binary number (+15) has a string of 1's from 2 3 to 2 0 (k = 3, m = 0). The hardware architecture for Signed 2 s Complement as shown below The Flowchart for Signed 2 s Complement as shown below The number can be represented as 2 k+1 2 m = = 16-1 = 15. Therefore, the multiplication M x 14, where M is the multiplicand and 14 the multiplier may be computed as M x M x 2 1. That is, the product can be obtained by shifting the binary multiplicand M four times to the left and subtracting M shifted left once. Booth algorithm needs examination of the multiplier bits and shifting of the partial product. Prior to the shifting, the multiplicand added to the partial product, subtracted from the partial product, or left unchanged by the following rules: 1. The multiplicand is subtracted from the partial product when we get the first least significant 1 in a string of 1's in the multiplier. 2. The multiplicand is added to the partial product when we get the first Q (provided that there was a previous 1) in a string of 0's in the multiplier. 3. The partial product does not change when the multiplier bit is the same as the previous multiplier bit.

6 The algorithm applies to both positive and negative multipliers in 2's complement representation. This is because a negative multiplier ends with a string of l's and the last operation will be a subtraction of the appropriate weight. For example, a multiplier equal to -14 is represented in 2's complement as and is treated as = -14. A numerical example of Booth algorithm is given in Table for n = 5. It gives the multiplication of (-9) x (-13) = BR = BR + 1 = AC QR Qn+1 SC 1 0 Initial Subtract BR ashr ashr Add BR ashr ashr Subtract BR ashr Table: Example of Multiplication with Booth Algorithm 3. Division Algorithms Division of two fixed-point binary numbers in signed magnitude representation is performed with paper and pencil by a process of successive compare, shift and subtract operations. Binary division is much simpler than decimal division because here the quotient digits are either 0 or 1 and there is no need to estimate how many times the dividend or partial remainder fits into the divisor. The division process is described in Figure. The divisor B has five bits and the dividend A had ten bits. Division: Quotient = Q B = Dividend = A bits of A < B, quotient has 5 Bits bits of A VVB Shift right B and subtract; enter 1 in Q bits of remainder V B Shift right B and subtract; enter 1 in Q Remainder < B; enter 0 in Q; shift right B; Remainder V B Shift right B and subtract; enter 1 in Q Remainder < B; enter 0 in Q Final remainder Figure : Example of Binary Division The devisor is compared with the five most significant bits of the dividend. Since the 5-bit number is smaller than B, we again repeat the same process. Now the 6-bit number is greater than B, so we place a 1 for the quotient bit in the sixth position above the dividend. Now we shift thedivisor once to the right and subtract it from the dividend. The difference is known as a partial remainder because the division could have stopped here to obtain a quotient of 1 and a remainder

7 equal to the partial remainder. Comparing a partial remainder with the divisor continues the process. If the partial remainder is greater than or equal to the divisor, the quotient bit is equal to 1. The divisor is then shifted right and subtracted from the partial remainder. If the partial remainder is smaller than the divisor, the quotient bit is 0 and no subtraction is needed. The divisor is shifted once to the right in any case. Obviously the result gives both a quotient and a remainder. Hardware Implementation for Signed-Magnitude Data In hardware implementation for signed-magnitude data in a digital computer, it is convenient to change the process slightly. Subtraction is achieved by adding A to the 2's complement of B. End carry gives the information about the relative magnitudes. Register EAQ is now shifted to the left with 0 inserted into Qn and the previous value of E is lost. The example is given in Figure to clear the proposed division process. The divisor is stored in the B register and the double-length dividend is stored in registers A and Q. The dividend is shifted to the left and the divisor is subtracted by adding its 2's complement value. E keeps the information about the relative magnitude. A quotient bit 1 is inserted into Qn and the partial remainder is shifted to the left to repeat the process when E = 1. If E = 0, it signifies that A < B so the quotient in Qn remains a 0 (inserted during the shift). Figure: Example of Binary Division with Digital Hardware Below is a flowchart of the hardware multiplication algorithm. In the beginning, the multiplicand is in B and the multiplier in Q. Their corresponding signs are in Bs and Qs respectively. We compare the signs of both A and Q and set to corresponding sign of the product since a double-length product will be stored in registers A and Q. Registers A and E are cleared and the sequence counter SC is set to the number of bits of the multiplier. Since an operand must

8 be stored with its sign, one bit of the word will be occupied by the sign and the magnitude will consist of n-1 bits. Now, the low order bit of the multiplier in Qn is tested. If it is 1, the multiplicand (B) is added to present partial product (A), 0 otherwise. Register EAQ is then shifted once to the right to form the new partial product. The sequence counter is decremented by 1 and its new value checked. If it is not equal to zero, the process is repeated and a new partial product is formed. When SC = 0 we stops the process. The hardware divide algorithm is given in Figure. A and Q contain the dividend and B has the divisor. The sign of the result is transferred into Q. A constant is set into the sequence counter SC to specify the number of bits in the quotient. As in multiplication, we assume that operands are transferred to registers from a memory unit that has words of n bits. Since an operand must be stored with its sign, one bit of the word will be occupied by the sign and the magnitude will haven-1 bit. Fig: Signed- Magnitude Division

9 An overflow may occur in the division operation, which may be easy to handle if we are using paper and pencil but is not easy when using hardware. This is because the length of registers is finite and will not hold a number that exceeds the standard length. To see this, let us consider a system that has 5-bit registers. We use one register to hold the divisor and two registers to hold the dividend. From the example of Figure, the quotient will consist of six bits if the five most significant bits of the dividend constitute a number greater than the divisor. The quotient is to be stored in a standard 5-bit register, so the overflow bit will require one more flip-flop for storing the sixth bit. This divide-overflow condition must be avoided in normal computer operations because the entire quotient will be too long for transfer into a memory unit that has words of standard length, that is, the same as the length of registers. Provisions to ensure that this condition is detected must be included in either the hardware or the software of the computer, or in a combination of the two. When the dividend is twice as long as the divisor, we can understand the condition for overflow as follows: A divide-overflow occurs if the high-order half bits of the dividend makes a number greater than or equal to the divisor. Another problem associated with division is the fact that a division by zero must be avoided. The divide-overflow condition takes care of this condition as well. This occurs because any dividend will be greater than or equal to a divisor, which is equal to zero. Overflow condition is usually detected when a special flip-flop is set. We will call it a divideoverflow flip-flop and label it DVF. Signed-2 s Complement Division Algorithm as Examples:

10 4. Floating-point Arithmetic operations In many high-level programming languages we have a facility for specifying floating-point numbers. The most common way is by a real declaration statement. High level programming languages must have a provision for handling floating-point arithmetic operations. The operations are generally built in the internal hardware. If no hardware is available, the compiler must be designed with a package of floating-point software subroutine. Although the hardware method is more expensive, it is much more efficient than the software method. Therefore, floating- point hardware is included in most computers and is omitted only in very small ones. Basic Considerations: There are two part of a floating-point number in a computer - a mantissa m and an exponent e. The two parts represent a number generated from multiplying m times a radix r raised to the value of e. Thus m x r e The mantissa may be a fraction or an integer. The position of the radix point and the value of the radix r are not included in the registers. For example, assume a fraction representation and a radix 10. The decimal number is represented in a register with m = and e = 3 and is interpreted to represent the floating-point number x 10 3 A floating-point number is said to be normalized if the most significant digit of the mantissa in nonzero. Biased exponents have the advantage that they contain only positive numbers. Now it becomes simpler to compare their relative magnitude without bothering about their signs. Another advantage is that the smallest possible biased exponent contains all zeros. The floating-point representation of zero is then a zero mantissa and the smallest possible exponent. Register Configuration: The register configuration for floating-point operations is shown in figure. As a rule, the same registers and adder used for fixed-point arithmetic are used for processing the mantissas. The difference lies in the way the exponents are handled. The register organization for floating-point operations is shown in Fig. Three registers are there, BR, AC, and QR. Each register is subdivided into two parts. The mantissa part has the same uppercase letter symbols as in fixed-point representation. The exponent part may use corresponding lower-case letter symbol. Figure: Registers for Floating Point arithmetic operations The AC has a mantissa whose sign is in As, and a magnitude that is in A. The diagram shows the most significant bit of A, labelled by A1. The bit in his position must be a 1 to normalize

12 Figure: Addition and Subtraction of floating point numbers Multiplication of Floating Point Numbers: The procedure for multiplication is divided in to below things: 1. Check for zeros. 2. Add the exponents. 3. Multiply the mantissas 4. Normalize the result The procedure is as showed in below flowcharts.

13 Fig: Flowchart for floating-point multiplication Division of Floating Point Numbers: The procedure for division is divided in to below things: 1. Check for zeros. 2. Subtract the exponents. 3. Divide the mantissas 4. Normalize the result The procedure is as showed in below flowcharts.

14 Fig: Flowchart for floating-point division

18 Fig: Decimal Arithmetic adders Where A,B,Q are the Register, Ae, Be, are Extension decimals, QLis the Last decimal in Q register. Fig: Registers for Decimal Arithmetic Multiplication and Division

19 Fig: Flowchart Decimal Arithmetic Multiplication Fig: Flowchart Decimal Arithmetic Division

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