Appendix A. Mk14 Instruction Set Summary

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1 Appendix A Mk14 Instruction Set Summary - SC/MP Instruction Set Summary (by function) - Instruction Execution Times - Opcode index of instruction (numeric-order) - Mnemonic index of instructions (alphabetical-order) 201

2 Symbols and Notations Used to Express Instruction Execution SYMBOL AND NOTATION AC CY/l data disp EA E i IE m OV PC ptr ptr n:m SIN SOUT SR ( ) [ /\ V ~ > = MEANING 8-bit Accumulator. Carry/Link Flag in the Status Register. Signed 8-bit immediate data field. Displacement; represents an operand in a non memory reference instruction or an address modifier field in a memory reference instruction. It is a signed twos-complement number. Effective Address as specified by the instruction. Extension Register; provides for temporary storage variable displacements and separate serial input/output port. Unspecified bit of a register. Interrupt Enable Flag. Mode bit used in memory reference instructions. Blank parameter sets m = sets m = 1. Overflow Flag in the Status Register. Program Counter (Pointer Register 0); during address formation PC points to the last byte of the instruction being executed. Pointer Register (ptr = 0 through 3). The register specified in byte 1 of the instruction. Pointer register bits; n:m = 7 through 0 or 15 through 8. Serial Input pin. Serial Output pin. 8-bit Status Register. Means "contents of." For example (EA) is contents of Effective Address. Means optional field in the assembler instruction format. Ones complement of value to right of Means "replaces." Means "is replaced by." Means "exchange" When used in the operand field of the instruction sets the mode bit (m) to 1 for auto-incrementing/auto-decrementing indexing. Modulo 10 addition. AND operation Inclusive-OR operation. Exclusive-OR operation. Greater than or equal to. Equals. Does not equal. 202

3 Instruction Execution Times READ WRITE TOTAL i READ WRITE INSTRUCTION CYCLES CYCLES MICROCYCLES INSTRUCTION CYCLES CYCLES MICROCYCLES ADD JP for Jump ADE I JZ for Jump ADI I LD AND LDE ANE LDI ANI NOP CAD OR CAE ORE CAl ORI I CAS RR CCL RRL CSA SCL DAD SIO I DAE SR DAI I SRL DINT ST OLD XAE DLY XOR HALT XPAH len XPAL ILD XPPC JMP XRE JNZ for Jump XRI I I

4 OPCODE INDEX OF INSTRUCTIONS Opcode Mnemonic Operation cycles 00 HALT Pulse H-flag 8 01 XAE Exchange AC and Extension 7 02 CCL Clear Carry/Link 5 03 SCL Set Carry/Link 5 04 DINT Disable Interrupts 6 05 len Enable Interrupts 6 06 CSA Copy Status to AC 5 07 CAS Copy AC to Status 6 08 NOP No Operation 5 19 SIO Serial Input/Output 5 1C SR Shift Right 5 10 SRL Shift Right with CY /L 5 1E RR Rotate Right 5 1F RRL Rotate Right with CY /L 5 30 XPAL Exchange Pointer Low 8 34 XPAH Exchange Pointer High 8 3C XPPC Exchange Pointer with PC 7 40 LDE Load from Extension 6 50 ANE AND Extension 6 58 ORE OR Extension 6 60 XRE Exclusive-OR Extension 6 68 DAE Decimal Add Extension ADE Add Extension 7 78 CAE Complement and Add Extension 8 8F DLY Delay JMP Jump JP Jump If Positive JZ Jump If Zero 911 9C JNZ Jump If Not Zero 911 A8 ILD I ncrement and Load 22 B8 DLD Decrement and Load 22 C0 LD Load 18 C4 LDI Load Immediate 10 C8 ST Store 18 D0 AND AND 18 D4 ANI AND Immediate 10 D8 OR OR 18 DC ORI OR Immediate 10 E0 XOR Exclusive-OR 18 E4 XRI Exclusive-OR Immediate 10 E8 DAD Decimal Add 23 EC DAI Decimal Add Immediate 15 F(;J ADD Add 19 F4 ADI Add Immediate 11 F8 CAD Complement and Add 20 FC CAl Complement and Add Immediate

5 MNEMONIC INDEX OF INSTRUCTIONS Mnemonic Opcode Description cycles ADD F0 Add 19 ADE 70 Add Extension 7 ADI F4 Add Immediate 11 AND D0 AND 18 ANE 5121 AND Extension 6 ANI D4 AND Immediate 10 CAD F8 Complement and Add 20 CAE 78 Complement and Add Extension 8 CAl FC Complement and Add Immediate 12 CAS 07 Copy AC to Status 6 CCl 02 Clear Carry/Link 5 CSA 06 Copy Status to AC 5 DAD E8 Decimal Add 23 DAE 68 Decimal Add Extension 11 DAI EC Decimal Add Immediate 15 DINT 04 Disable Interrupts 6 DlD B8 Decrement and Load 22 DLY 8F Delay HALT 00 Pulse H-flag 8 len 05 Emable Interrupts 6 ILD A8 Increment and Load 22 JMP 90 Jump 11 JNZ 9C Jump If Not Zero 911 JP 94 Jump If Positive 911 JZ 98 Jump If Zero 911 LD C0 Load 18 LDE 40 Load from Extension 6 LDI C4 Load Immediate 10 NOP 08 No Operation 5 OR D8 OR 18 ORE 58 OR Extension 6 ORI DC OR Immediate 10 RR 1E Rotate Right 5 RRL 1F Rotate Right with Link 5 SCL 03 Set Carry/Link 5 SIO 19 Serial Input/Output 5 SR 1C Shift Right 5 SRl 10 Shift Right with Link 5 ST C8 Store 18 XAE 01 Exchange AC and Extension 7 XOR E() Exclusive-OR 18 XPAH 34 Exchange Pointer High 8 XPAl 3~ Exchange Pointer Low 8 XPPC 3C Exchange Pointer with PC 7 XRE 60 Exclusive-OR Extension 6 XRI E4 Exclusive-OR Immediate 1!J 205

6 APPENDIX B THE HI-LO GAME This appendix includes a complete listing of the Hi-lo program developed in Chapter 13 0F20 C406 0F22 C901 0F F F F27 EC 01 0F F2A C101 0F2C E4 FF 0F2E 98 F5 0F F31 CA 12 0F33 C400 0F35 8F 14 0F37 C101 0F39 E4 FF 0F3B 9C F8 0F3D C400 0F3F CA0D 0F41 CA0C 0F43 C400 0F45 CA00 0F47 CA01 0F49 C START: LOOP: WAIT: NUMRT: GUESS ;Hi-lo Game ;To start game Press '1' to generate random num ;ber from 0 to 99. Enter guess at keyboard - keys ;A to F are read as digit 9. Mk14 compares guess ;with random number when command key is ;pressed. ;ABORT key terminates game. ;When guess is correct Mk 14 shows number of ;guesses and correct number. Next key pressed ;starts game again.. = 0F20 ;First section generates random number 0 to 99. LDI 06 ST 1 (1) XAE LDE Cel DAI +1 XAE LD 1 (1) XRI FF JZ LOOP LDE ST DATA (2) LDI 00 DLY 14 LD 1 (1) XRI FF JNZ WAIT ;Segment code for digit 1 ;liluminate digit ;Initialise count ; Load count ;Increment count ;Test key '1' ;Jump if not pressed ;Store random number ;Clear AC for delay ;Wait 10 ms ;Test key '1' ;Wait if still pressed ;Random number stored in DATA (2) ;Section to initialise display LDI FF ST DDTA (2) LDI 00 ST WORD (2) ST ADL (2) LDI 00 ST DL (2) ST DH (2) LDI 00 ;strictly necessary to ensure ; operation ;Clear Guess Count ;Clear Guess ;Clear Data Field in ;Display

7 0F4B CA0E ST ADH (2) ;Clear high byte address 0F4D C40137 JS 3DISPA ;Monitor subroutine 0F50 C F53 3F ;Section to update guess with digit entered 0F JMP TEST ;Command key return 0F56 40 LDE ; Load digit 0F57 03 SCL 0F58 FC0A CAl 0A ;Subtract 0A 0F5A 9402 JP NBCD ;Not BCD 0F5C 9003 JMP CaNT 0F5E C409 NBCD: LDI 09 ;Replace with 9 0F60 01 XAE 0F61 C CaNT: JS 3ADR ;Update Guess 0F64 C41A33 0F67 3F 0F JMP NUMRT ;Display Guess ; Intermediate jump to preserve PC-relative ;addressing!ilf6a 9!il A4 START 1: JMP START ;Section to compare Guess in ADL (2) ;with random number.in DATA (2) 0F6C C4 FF TEST: LDI FF 0F6E CA0F ST DDTA (2) ;Set new address flag 0F70 C20D LD WORD (2) 0F72 EC 01 DAI +1 0F74 CA0D ST WORD (2) ;Increment Guess Count 0F76 03 SCL 0F77 C20C LD ADL (2) ;Add DATA and ADL 0F79 EA 12 DAD' DATA (2j 0F7B 9817 JZ EQUAL ;Equal if zero 0F7C 06 CSA 0F7E 940A JP LOW ;Carry = f2i if positive 0F80 C476 HIGH: LDI 'H' ; Load message Hi 0F82 CA 01 ST DH (2) 0F84 C404 LDI 'i' QJF86 CA 0QJ ST DL (2) QJF88 90 BF JMP GUESS 0F8A C438 LOW: LDI 'L' ; Load message Lo 0F8C CA01 ST DH (2) 0F8E C45C LDI '0' 0F90 CA 00 ST DL (2) 0F JMP GUESS 0F94 C400 EQUAL: LDI f2if2i 0F96 CA0E ST ADH (2) ;Clear high-order address field 207

8 0F98 C F9B C4 3F 33 0F9E 3F 0F9F 90 C9 0FA1 90 C7 JS 3DISPD JMP START 1 JMP START 1 ;Begin again ;Definition of address offsets for data storage DL 00 DH 01 ADL 0C WORD 00 ADH 0E DDTA 0F DATA 12 ;Initialise Pointer Registers. = 0FF9. DBYTE 0000 ;Dispiay Pointer.DBYTE 0F00 ;RAM Pointer.END 208

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(2) Explain the addressing mode of OR What do you mean by addressing mode? Explain diff. addressing mode for 8085 with examples.

(2) Explain the addressing mode of OR What do you mean by addressing mode? Explain diff. addressing mode for 8085 with examples. (1) Explain instruction format and Opcode format of 8085 μp with example. OR With help of examples, explain the formation of opcodes of 8085 OR What is an instruction? List type of instruction based on