# APPENDIX A SHORT QUESTIONS AND ANSWERS

Size: px
Start display at page:

Transcription

1 APPENDIX A SHORT QUESTIONS AND ANSWERS Unit I Boolean Algebra and Logic Gates Part - A 1. Define binary logic? Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0. There are three basic logic operations: AND, OR, and NOT. 2. What are the basic digital logic gates? The three basic logic gates are AND gate OR gate NOT gate 3. What is a Logic gate? Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function. 4. Give the classification of logic families 5. Which gates are called as the universal gates? What are its advantages? The NAND and NOR gates are called as the universal gates. These gates are used to perform any type of logic application.

2 6. Classify the logic family by operation? The Bipolar logic family is classified into Saturated logic Unsaturated logic. The RTL, DTL, TTL, I 2 L, HTL logic comes under the saturated logic family. The Schottky TTL, and ECL logic comes under the unsaturated logic family. 7. Define Fan-out? Fan out specifies the number of standard loads that the output of the gate can drive without impairment of its normal operation. 8. Define power dissipation? Power dissipation is measure of power consumed by the gate when fully driven by all its inputs. 9. What is propagation delay? Propagation delay is the average transition delay time for the signal to propagate from input to output when the signals change in value. It is expressed in ns. 10. Define noise margin? It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts. 11. Define fan in? Fan in is the number of inputs connected to the gate without any degradation in the voltage level. 12. What is Operating temperature? All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which the performance of the IC is effective is called as operating temperature. Operating temperature of the IC vary from 0 0 C to 70 0 c. 13. What is High Threshold Logic? Some digital circuits operate in environments, which produce very high noise signals. For operation in such surroundings there is available a type of DTL gate which possesses a high threshold to noise immunity. This type of gate is called HTL logic or High Threshold Logic. 14. Which gate is equal to AND-invert Gate? NAND gate.

3 15. Which gate is equal to OR-invert Gate? NOR gate. 16. Bubbled OR gate is equal to NAND gate 17. Bubbled AND gate is equal to NOR gate 18. Define the term digital. The term digital refers to any process that is accomplished using discrete units 19. What is meant by bit? A binary digit is called bit 20. What is the best example of digital system? Digital computer is the best example of a digital system. 21. Define byte? A group of 8 bits. 22. List the number systems? i) Decimal Number system ii) Binary Number system iii) Octal Number system iv) Hexadecimal Number system 23. State the sequence of operator precedence in Boolean expression? i) Parenthesis ii) NOT iii) AND iv) OR 24. What is the abbreviation of ASCII and EBCDIC code? ASCII-American Standard Code for Information Interchange. EBCDIC-Extended Binary Coded Decimal Information Code. 25. What are the different types of number complements? i) 1 scomplement (r-1 s complement) ii) 2 s Complement (r s complement) 26. Why complementing a number representation is needed? Complementing a number becomes as in digital computer for simplifying the subtraction operation and for logical manipulation complements are used.

4 27. How to represent a positive and negative sign in computers? Positive (+) sign by 0 Negative (-) sign by What is meant by Map method? The map method provides a simple straightforward procedure for minimizing Boolean function. 29. What is meant by two variable map? Two variable map have four minterms for two variables, hence the map consists of four squares, one for each minterm 30. What is meant by three variable map? Three variable map have 8 minterms for three variables, hence the map consists of 8 squares, one for each minterm 31. What is the use of Don t care conditions? Any digital circuit using this code operates under the assumption that these unused combinations will never occur as long as the system 32. Express the function f(x, y, z)=1 in the sum of minterms and a product of maxterms? Minterms= (0,1,2,3,4,5,6,7) Maxterms=Nomaxterms. 33. What is the algebraic function of Exclusive-OR gate and Exclusive-NOR gate? F=xy +x y F=xy +x y 34. What are the methods adopted to reduce Boolean function? i) Karnaugh map ii) Tabular method or Quine mccluskey method iii) Variable entered map technique. 35. Why we go in for tabulation method? This method can be applied to problems with many variables and has the advantage of being suitable for machine computation.

5 36. State the limitations of Karnaugh map. i) Generally it is limited to six variable map (i.e.) more than six variable involving expressions are not reduced. ii) The map method is restricted in its capability since they are useful for simplifying only Boolean expression represented in standard form. 37. What is tabulation method? A method involving an exhaustive tabular search method for the minimum expression to solve a Boolean equation is called as a tabulation method. 38. What are prime-implicants? The terms remained unchecked are called prime-implicants. They cannot be reduced further. 40. Explain or list out the advantages and disadvantages of K-map method? The advantages of the K-map method are i. It is a fast method for simplifying expression up to four variables. ii. It gives a visual method of logic simplification. iii. Prime implicants and essential prime implicants are identified fast. iv. Suitable for both SOP and POS forms of reduction. The disadvantages of the K-map method are i. It is not suitable for computer reduction. ii. K-maps are not suitable when the number of variables involved exceed four. iii. Care must be taken to fill in every cell with the relevant entry, such as a 0, 1 (or) don t care terms. 41. List out the advantages and disadvantages of Quine-Mc Cluskey method? The advantages are, a. This is suitable when the number of variables exceed four. b. Digital computers can be used to obtain the solution fast. c. Essential prime implicants, which are not evident in K-map, can be clearly seen in the final results. The disadvantages are, a. Lengthy procedure than K-map. b. Requires several grouping and steps as compared to K-map. c. It is much slower. d. No visual identification of reduction process. e. The Quine Mc Cluskey method is essentially a computer reduction method.

6 42. Define Positive Logic. When high voltage or more positive voltage level is associated with binary 1 and while the low or less positive level is associated with binary 0 then the system adhering to this is called positive logic. 43. Define Negative Logic. When high voltage level is associated with binary 0 and whiles the low level is associated with binary 1 then the system adhering to this is called negative logic. 44. List the characteristics of digital Ics i) propagation delay ii) power dissipation iii) Fan-in iv) Fan-out v) Noise margin 45. Why parity checker is needed? Parity checker is required at the receiver side to check whether the expected parity is equal to the calculated parity or not. If they are not equal then it is found that the received data has error. 46. What is meant by parity bit? Parity bit is an extra bit included with a binary message to make the number of 1 s either odd or even. The message, including the parity bit is transmitted and then checked at the receiving and for errors. 47. Why parity generator necessary? Parity generator is essential to generate parity bit in the transmitter. 48. What is IC? An integrated circuit is a small silicon semiconductor crystal called a chip containing electrical components such as transistors, diodes, resistors and capacitors. The various components are interconnected inside the chip to form an electronic circuit. 49. What are the needs for binary codes? a. Code is used to represent letters, numbers and punctuation marks. b. Coding is required for maximum efficiency in single transmission. c. Binary codes are the major components in the synthesis (artificial generation) of speech and video signals. d. By using error detecting codes, errors generated in signal transmission can be detected. e. Codes are used for data compression by which large amounts of data are transmitted in very short duration of time.

7 50. Mention the different type of binary codes? The various types of binary codes are, a. BCD code (Binary Coded decimal). b. Self-complementing code. h. The excess-3 (X s-3) code. i. Gray code. c. Binary weighted code. d. Alphanumeric code. e. The ASCII code. f. Extended binary-coded decimal interchange code (EBCDIC). g. Error-detecting and error-correcting code. h. Hamming code. 51. List the advantages and disadvantages of BCD code? The advantages of BCD code are a. Any large decimal number can be easily converted into corresponding binary number b. A person needs to remember only the binary equivalents of decimal number from 0 to 9. c. Conversion from BCD into decimal is also very easy. The disadvantages of BCD code are a. The code is least efficient. It requires several symbols to represent even small numbers. b. Binary addition and subtraction can lead to wrong answer. c. Special codes are required for arithmetic operations. d. This is not a self-complementing code. e. Conversion into other coding schemes requires special methods. 52. What is meant by self-complementing code? A self-complementing code is the one in which the members of the number system complement on themselves. This requires the following two conditions to be satisfied. a. The complement of the number should be obtained from that number by replacing 1s with 0s and 0s with 1s. b. The sum of the number and its complement should be equal to decimal 9. Example of a self-complementing code is i code. ii. Excess-3 code. 53. Mention the advantages of ASCII code? The following are the advantages of ASCII code a. There are 2 7 =128 possible combinations. Hence, a large number of symbols, alphabets etc.., can be easily represented. b. There is a definite order in which the alphabets, etc.., are assigned to each code word. c. The parity bits can be added for error-detection and correction.

8 54. What are the disadvantages of ASCII code? The disadvantages of ASCII code are a. The length of the code is larger and hence more bandwidth is required for transmission. b. With more characters and symbols to represent, this is not completely sufficient. 55. What is the truth table? A truth table lists all possible combinations of inputs and the corresponding outputs. 56. Define figure of merit? Figure of merits is defined as the product of speed and power. The speed is specified in terms of propagation delay time expressed in nano seconds. Figure of merits=propagation delay time (ns)* Power (mw). It is specified in pico joules (ns*mw=pj). Part - B 1. Simplify the following Boolean function by using Tabulation method F (w, x, y, z) =Σ(0,1,2,8,10,11,14,15) Determination of Prime Implicants Selection of prime Implicants 2. Simplify the following Boolean functions by using K Map in SOP & POS. F (w, x, y, z) =Σ(1,3,4,6,9,11,12,14) Find the Number of variable map Draw the Map Simplification of SOP & POS 3. Simplify the following Boolean functions by using K-Map in SOP & POS. F (w, x, y, z) =Σ(1,3,7,11,15) + d(0,2,5) Find the Number of variable map Don t care treat as variable X. Draw the Map Simplification of SOP & POS 4. Reduce the given expression. [(AB) + A +AB] using Boolean algebra Laws and theorems. Use Boolean laws and theorems to simplify the expression Use De-Morgan s theorem Use associative law of Boolean function

9 5. Reduce the given function minimum number of literals. (ABC) 1 + A 1 +AC Reduce the expression using Boolean algebra Laws and theorems Use Boolean laws and theorems to simplify the expression Use three variable De-Morgan s theorem Use associative law of Boolean function 6. Simplify the following Boolean expression using Quine McCluskey method: F = Σm (0, 9,15, 24, 29, 30) + d (8,11, 31). (16) The don t care minterms are included Find minterms, binary A,B,C,D,No of 1 s, minterms group, index, binary A,B,C,D All the terms which remain unchecked are PIs,Moreover one of two same combinations is eliminated. Prepare a PI chart to determine EPIs. All the minterms have been covered by EPIs. Unit II Combinational Logic Part - A 1. Define Combinational circuit. A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination of inputs without regard to previous inputs. 2. Explain the design procedure for combinational circuits The problem definition Determine the number of available input variables & required O/P variables. Assigning letter symbols to I/O variables Obtain simplified Boolean expression for each O/P. Obtain the logic diagram. 3. What is a half-adder? The combinational circuit that performs the addition of two bits is called a halfadder.

10 4. What is a full-adder? The combinational circuit that performs the addition of three bits is called a halfadder. 5. What is half-subtractor? The combinational circuit that performs the subtraction of two bits is called a halfsub tractor. 6. What is a full-subtractor? The combinational circuit that performs the subtraction of three bits is called a halfsub tractor. 7. What is Binary parallel adder? A binary parallel adder is a digital function that produces the arithmetic sum of two binary numbers in parallel. 8. What is BCD adder? A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD. 9. Give the truth table for a half adder. Input Output X Y Sum ( S ) Carry ( C ) Give the truth table for a half Subtractor. Input Output X Y Difference (D) Borrow ( B ) From the truth table of a half adder derive the logic equation S =X Y C = X. Y

11 12. From the truth table of a half subtractor derive the logic equation D = X Y B =X. Y 13. From the truth table of a full adder derive the logic equation S =X Y Z C = XY + YZ + XZ 14. What is code conversion? If two systems working with different binary codes are to be synchronized in operation, then we need digital circuit which converts one system of codes to the other. The process of conversion is referred to as code conversion. 15. What is code converter? It is a circuit that makes the two systems compatible even though each uses a different binary code. It is a device that converts binary signals from a source code to its output code. One example is a BCD to Excess3 converter. 16. What do you mean by analyzing a combinational circuit? The reverse process for implementing a Boolean expression is called as analyzing a combinational circuit. (ie) the available logic diagram is analyzed step by step and finding the Boolean function 17. Give the truth table for a full Subtractor. Input Output X Y B in Difference (D) Borrow ( B )

12 18. Give the truth table for a full adder. Input Output X Y C in Sum ( S ) Carry ( C ) From the truth table of a full subtractor derive the logic equation S =X Y Z C = X Y + YZ + X Z 20. What are the two types of logic circuits for digital systems? Combinational Logic circuit and Sequential Logic circuit 21. Draw the logic diagram for half adder. 22. Draw the logic diagram for the Boolean expression ((A + B) C) D using NAND gates.

13 23. With block diagram show how a full adder can be designed by using two half adders and one OR gate. 24. List the modeling techniques available in HDL. Structural Modeling Dataflow Modeling Behavioural Modeling 25. Realize the half adder using equal number of OR and AND gates. In half adder Sum Carry =A XOR B=(AB +BA ) = (A +B ) PART B 1. Design a combinational logic circuit to convert the Gray code into Binary code Draw the truth table for Gray code to binary code For Each and every output draw the Karnaugh map Simplify the Karnaugh map and get the output Boolean function Draw the Logic Diagram

15 Unit III Design With MSI Devices Part - A 1. Give the function of Multiplexer. Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. 2. What is priority encoder? A priority encoder is an encoder that includes the priority function. The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. 3. Mention the uses of Demultiplexer. i) It finds its application in Data transmission system with error detection. ii) One simple application is binary to Decimal decoder. 4. Give the function of Demultiplexer. Demultiplexer is used in computers when a same message has to be sent to different receivers. Not only in computers, but any time information from one source can be fed to several places. 5. What is the function of the enable input in a Multiplexer? The function of the enable input in a MUX is to control the operation of the unit. 6. Can a decoder function as a Demultiplexer? Yes. A decoder with enable can function as a Demultiplexer if the enable line E is taken as a data input line A and B are taken as selection lines. 7. List out the applications of multiplexer? The various applications of multiplexer are a. Data routing. b. Logic function generator. c. Control sequencer. d. Parallel-to-serial converter. 8. List out the applications of decoder? The applications of decoder are a. Decoders are used in counter system. b. They are used in analog to digital converter. c. Decoder outputs can be used to drive a display system.

16 9. List out the applications of comparators? The following are the applications of comparator a. Comparators are used as a part of the address decoding circuitry in computers to select a specific input/output device for the storage of data. b. They are used to actuate circuitry to drive the physical variable towards the reference value. c. They are used in control applications. 10. What are the applications of seven segment displays? The seven segment displays are used in a. LED displays b. LCD displays 11. List the types of ROM. i) Programmable ROM (PROM) ii) Erasable ROM (EPROM) iii) Electrically Erasable ROM (EEROM) 12. Differentiate ROM & PLD s ROM (Read Only Memory) PLD s (Programmable Logic Array) 1.It is a device that includes both the decoder and the OR gates within a single IC package 2. It is a device that includes both AND and OR gates within a single IC package 3.ROM does not full decoding of the variables and does generate all the minterms 4. PLD s does not provide full decoding of the variable and does not generate all the minterms 13. What are the different types of RAM? The different types of RAM are a. NMOS RAM (Nitride Metal Oxide Semiconductor RAM) b. CMOS RAM (Complementary Metal Oxide Semiconductor RAM) c. Schottky TTL RAM d. ELL RAM. 14. What are the types of arrays in RAM? RAM has two type of array namely, a. Linear array b. Coincident array

17 15. Explain DRAM? The dynamic RAM (DRAM) is an operating mod, which stores the binary information in the form of electric charges on capacitors. The capacitors are provided inside the chip by MOS transistors. DRAM cell Storage capacitor Column (sense line) Row (control line) 16. Explain SRAM? Static RAM (SRAM) consists of internal latches that store the binary information. The stored information remains valid as long as the power is applied to the unit. SRAM is easier to use and has shorter read and write cycle. The memory capacity of a static RAM varies from 64 bit to 1 mega bit. 17. What are the terms that determine the size of a PAL? The size of a PLA is specified by the a. Number of inputs b. Number of products terms c. Number of outputs 18. What are the advantages of RAM? The advantages of RAM are a. Non-destructive read out b. Fast operating speed c. Low power dissipation d. Compatibility e. Economy 19. What is VHDL? VHDL is a hardware description language that can be used to model a digital system at many level of abstraction, ranging from the algorithmic level to the gate level. The VHDL language as a combination of the following language. a. Sequential language b. Concurrent language c. Net-list language d. Timing specification e. Waveform generation language. 20. What are the features of VHDL? The features of VHDL are a. VHDL has powerful constructs. b. VHDL supports design library. c. The language is not case sensitive.

18 21. Define entity? Entity gives the specification of input/output signals to external circuitry. An entity is modeled using an entity declaration and at least one architecture body. Entity gives interfacing between device and others peripherals. 22. List out the different elements of entity declaration? The different elements of entity declaration are: 1. entity_name 2. signal_name 3. mode 4. in: 5. out: 6. input 7. buffer 8. signal_type 23. Give the syntax of entity declaration? ENTITY entity_name is PORT (signal_name: mode signal_type; signal_names: mode signal_type; signal_names: mode signal_type; END entity_name; 24. What do you meant by concurrent statement? Architecture contains only concurrent statements. It specifies behavior, functionality, interconnections or relationship between inputs and outputs. 25. What are operates used in VDHL language? There are different types of operators used in VHDL language Logical operators: AND, OR, NOT, XOR, etc., Relational operator : equal to, <less than etc., Shift operators : SLL- Shift Left Logical, ROR- Rotate Right Logical etc., Arithmetic operators: Addition, subtraction etc., Miscellaneous operators: <= assign to etc., 26. Define VHDL package? A VHDL, package is a file containing definitions of objects which can be used in other programs. A package may include objects such as signals, type, constant, function, procedure and component declarations

19 27. What is meant by memory decoding? The memory IC used in a digital system is selected or enabled only for the range of addresses assigned to it. 28. What is access and cycle time? The access time of the memory is the time to select word and read it. The cycle time of a memory is a time required to complete a write operation. 29. Give other name for Multiplexer and Demultiplexer. Multiplexer is otherwise called as Data selector. Demultiplexer is otherwise called as Data distributor. 30. What is Magnitude Comparator? A Magnitude Comparator is a combinational circuit that compares two numbers, A and B and determines their relative magnitudes. 31. What is decoder? A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. 32. What is encoder? A decoder is a combinational circuit that converts binary information from 2nInput lines to a maximum of n unique output lines. 33. List basic types of programmable logic devices. Read only memory Programmable logic Array Programmable Array Logic 34. Explain ROM A read only memory (ROM) is a device that includes both the decoder and the OR gates within a single IC package. It consists of n input lines and m output lines. Each bit combination of the input variables is called an address. Each bit combination that comes out of the output lines is called a word. The number of distinct addresses possible with n input variables is 2 n.

20 35. Define address and word: In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word. 36. State the types of ROM Masked ROM. Programmable Read only Memory Erasable Programmable Read only memory. Electrically Erasable Programmable Read only Memory. 37. What is programmable logic array? How it differs from ROM? In some cases the number of don t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM. 38. Explain PROM. PROM (Programmable Read Only Memory) It allows user to store data or program. PROMs use the fuses with material like nichrome and polycrystalline. The user can blow these fuses by passing around 20 to 50 ma of current for the period 5 to 20µs.The blowing of fuses is called programming of ROM. The PROMs are one time programmable. Once programmed, the information is stored permanent. 39. Explain EPROM. EPROM (Erasable Programmable Read Only Memory) EPROM use MOS circuitry. They store 1 s and 0 s as a packet of charge in a buried layer of the IC chip. We can erase the stored data in the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip can be reprogrammed.

21 40. Explain EEPROM. EEPROM (Electrically Erasable Programmable Read Only Memory) EEPROM also use MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating gate in the device. EEPROM allows selective erasing at the register level rather than erasing all the information since the information can be changed by using electrical signals. 41. List the major differences between PLA and PAL PLA: Both AND and OR arrays are programmable and Complex Costlier than PAL PAL AND arrays are programmable OR arrays are fixed Cheaper and Simpler 42. Define PLD. Programmable Logic Devices consist of a large array of AND gates and OR gates that can be programmed to achieve specific logic functions. 43. Give the classification of PLDs. PLDs are classified as PROM (Programmable Read Only Memory), Programmable Logic Array (PLA), Programmable Array Logic (PAL), and Generic Array Logic (GAL) 44. Give the comparison between PROM and PLA. PROM PLA 1. And array is fixed and OR Array is programmable. Both AND and OR Arrays are Programmable. 2. Cheaper and simple to use. Costliest and complex than PROMS.

22 PART B 1. Implement the following function using PLA. A (x, y, z) =Σm (1, 2, 4, 6) B (x, y, z) =Σm (0, 1, 6, 7) C (x, y, z) =Σm (2, 6) Simplify all the expression using Karnaugh map Draw the PLA table containing all the minterms From the PLA table draw the logic diagram of the function 2. Implement the following function using PAL. W (A, B, C, D) =Σm (2, 12, 13) X (A, B, C, D) =Σm (7, 8, 9, 10, 11, 12, 13, 14, 15) Y (A, B, C, D) =Σm (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) Z (A, B, C, D) =Σm (1, 2, 8, 12, 13) Simplify all the expression using Karnaugh map Draw the PAL table containing all the minterms From the PAL table draw the logic diagram of the function 3. Implement the given function using multiplexer F(A,B,C,D)= (1,3,5,6) Draw the truth table of the given function Convert the truth table as Implementation table Select the required type of multiplexer. Multiplexer Implementation 4. Explain about Encoder and Decoder? Define the encoder and decoder Draw the truth table of encoder and decoder Draw the Logic Diagram of encoder and decoder Types of encoder Applications of encoder and decoder 6. Explain in detail about PLA and PAL. Logic difference between PROM & PLA Logic diagram implementing a function Logic difference between PROM & PAL Logic diagram implementing a function

23 8. Implement F(A,B,C,D)= (1,3,4,11,12,13,14,15) using multiplexer. Draw the truth table of the given function Convert the truth table as Implementation table Select the required type of multiplexer. Multiplexer Implementation 9. Implement W(A,B,C,D) = Σ (2,12,13) X(A,B,C,D) = Σ (7,8,9,10,11,12,13,14,15) Y(A,B,C,D) = Σ(0,2,3,4,5,6,7,8,10,11,15) Z (A,B,C,D) = Σ (1,2,8,12,13) using PAL Simplify all the expression using Karnaugh map Draw the PAL table containing all the minterms From the PAL table draw the logic diagram of the function

24 Unit IV Synchronous Sequential Logic Part - A 1. What is sequential circuit? Sequential circuit is a broad category of digital circuit whose logic states depend on a specified time sequence. A sequential circuit consists of a combinational circuit to which memory elements are connected to form a feedback path. 2. List the classifications of sequential circuit. i) Synchronous sequential circuit. ii) Asynchronous sequential circuit. 3. What is Synchronous sequential circuit? A Synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signal at discrete instants of time. 4. What is a clocked sequential circuit? Synchronous sequential circuit that use clock pulses in the inputs of memory elements are called clocked sequential circuit. One advantage as that they don t cause instability problems. 5. What is called latch? Latch is a simple memory element, which consists of a pair of logic gates with their inputs and outputs inter connected in a feedback arrangement, which permits a single bit to be stored. 6. List different types of flip-flops. i) SR flip-flop ii) Clocked RS flip-flop iii) D flip-flop iv) T flip-flop v) JK flip-flop vi) JK master slave flip-flop 7. What do you mean by triggering of flip-flop. The state of a flip-flop is switched by a momentary change in the input signal. This momentary change is called a trigger and the transition it causes is said to trigger the flipflop

25 8. What is an excitation table? During the design process we usually know the transition from present state to next state and wish to find the flip-flop input conditions that will cause the required transition. A table which lists the required inputs for a given chance of state is called an excitation table. 9. Give the excitation table of a JK flip-flop Present State Next State Flip Flop Inputs Q n Q n+1 J K X X 1 0 X X Give the excitation table of a SR flip-flop Present State Next State Flip Flop Inputs Q n Q n+1 R S 0 0 X X 11. Give the excitation table of a D flip-flop Present State Next State Flip Flop Inputs Q n Q n+1 D Give the excitation table of a T flip-flop Present State Next State Flip Flop Inputs Q n Q n+1 T

26 13. What is a characteristic table? A characteristic table defines the logical property of the flip-flop and completely characteristic its operation. 14. Give the characteristic equation of a SR flip-flop. Q(t+1)=S+R Q 15. Give the characteristic equation of a D flip-flop. Q(t+1)=D 16. Give the characteristic equation of a JK flip-flop. Q(t+1)=JQ +K Q 17. Give the characteristic equation of a T flip-flop. Q(t+1)=TQ +T Q 18. What is the difference between truth table and excitation table? i) An excitation table is a table that lists the required inputs for a given change of state. ii) A truth table is a table indicating the output of a logic circuit for various input states. 19. What is counter? A counter is used to count pulse and give the output in binary form. 20. What is synchronous counter? In a synchronous counter, the clock pulse is applied simultaneously to all flip-flops. The output of the flip-flops change state at the same instant. The speed of operation is high compared to an asynchronous counter 21. What is Asynchronous counter? In a Asynchronous counter, the clock pulse is applied to the first flip-flops. The change of state in the output of this flip-flop serves as a clock pulse to the next flip-flop and so on. Here all the flip-flops do not change state at the same instant and hence speed is less. 22. What is the difference between synchronous and asynchronous counter? Synchronous counter 1. Clock pulse is applied simultaneously Clock pulse is applied to the first flip-flop, the change of output is given as clock to next flip-flop. 2. Speed of operation is low.

27 Asynchronous counter 1. Clock pulse is applied to the first flip-flop, the change of output is given as clock to next flip-flop 2. Speed of operation is high. 23. Name the different types of counter. a) Synchronous counter b) Asynchronous counter i) Up counter ii) Down counter iii) Modulo N counter iv) Up/Down counter 24. What is up counter? A counter that increments the output by one binary number each time a clock pulse is applied. 25. What is down counter? A counter that decrements the output by one binary number each time a clock pulse is applied. 26. What is up/down counter? A counter, which is capable of operating as an up counter or down counter, depending on a control lead. 27. What is a ripple counter? A ripple counter is nothing but an asynchronous counter, in which the output of the flip-flop changes state like a ripple in water. 28. What are the uses of a counter? i) The digital clock ii) Auto parking control iii) Parallel to serial data conversion. 29. What is meant by modulus of a counter? By the term modulus of a counter we say it is the number of states through which a counter can progress. 30. What is meant by natural count of a counter? By the term natural count of a counter we say that the maximum number of states through which a counter can progress.

28 31. The number of flip-flops required for modulo-18 counter is Ans: n 2 T. Therefore 5 flip flops required. 32. What is a ring counter? A counter formed by circulating a bit in a shift register whose serial output has been connected to its serial input. 33. What is BCD counter? A BCD counter counts in binary coded decimal from0000 to 1001 and back to0000. Because of the return to0000 after a count of 1001, a BCD counter does not have a regular pattern as in a straight binary counter. 34. What is a register? Memory elements capable of storing one binary word. It consists of a group of flipflops, which store the binary information. 35. What is a shift register? In digital circuits, data are needed to be moved into a register (shift in) or moved out of a register (shift out). A group of flip-flops having either or both of these facilities is called a shift register. 36. What is serial shifting? In a shift register, if the data is moved 1 bit at a time in a serial fashion, then the technique is called serial shifting. 37. Define state of sequential circuit? The binary information stored in the memory elements at any given time defines the state of sequential circuits. 38. Define state diagram. A graphical representation of a state table is called a state diagram. 39. What is the use of state diagram? i) Behavior of a state machine can be analyzed rapidly. ii) It can be used to design a machine from a set of specification. 40. What is state table? A table, which consists time sequence of inputs, outputs and flip-flop states, is called state table. Generally it consists of three section present state, next state and output.

29 41. What are the different types of shift type? There are five types. They are, Serial In Serial Out Shift Register Serial In Parallel Out Shift Register Parallel In Serial Out Shift Register Parallel In Parallel Out Shift Register Bidirectional Shift Register 42. Give the comparison between combinational circuits and sequential circuits. Combinational circuits Memory unit is not required Parallel adder is a combinational Sequential circuits Memory unity is required Serial adder is a sequential circuit circuit PART B 1. Design a counter with the following repeated binary sequence:0, 1, 2, 3, 4, 5, 6. Use JK Flip-flop. Draw the State diagram from the given specifications Draw the Excitation State table from state diagram Using K Map, Simplify the output and state equation Draw the Logic diagram of the obtained Boolean function 2. Describe the operation of SR flip-flop Draw the Logic Diagram of SR flip flop Draw the Graphical Symbol of SR flip flop Draw the Characteristics table of SR flip flop Write the Characteristics equation of SR flip flop Explain the function of SR flip flop 3. The count has a repeated sequence of six states, with flip flops B and C repeating the binary count 00, 01, 10 while flip flop A alternates between 0 and 1 every three counts. Designs with JK flip-flop Draw the State diagram from the given specifications Draw the Excitation State table from state diagram Using K Map, Simplify the output and state equation Draw the Logic diagram of the obtained Boolean function

30 4. Design a 3-bit T flip-flop counter Draw the State diagram from the given specifications Draw the Excitation State table from state diagram Using K Map, Simplify the output and state equation Draw the Logic diagram of the obtained Boolean function 5. Explain the working of BCD Ripple Counter with the help of state diagram and logic diagram. BCD Ripple Counter Count sequence Truth Table State diagram representing the Truth Table Truth Table for the J-K Flip Flop Logic Diagram 6. Design a sequential detector which produces an output 1 every time the input sequence 1011 is detected. Construct state diagram Obtain the flow table Obtain the flow table & output table Transition table Select flip flop Excitation table Logic diagram 7. Explain in detail about serial in serial out shift register. Block diagram Theoretical explanation Logic diagram Working principle Unit V Asynchronous Sequential Logic Part - A 1. What is flow table? During the design of asynchronous sequential circuits, it is more convenient to name the states by letter symbols without making specific reference to their binary values. Such table is called Flow table. 2. What is primitive flow table? A flow table is called Primitive flow table because it has only one stable state in each row. 3. Define race condition. A race condition is said to exist in asynchronous sequential circuit when two or more binary state variables change, the race is called non-critical race.

31 4. Define critical & non-critical race with example. The final stable state that the circuit reaches does not depend on the order in which the state variables change, the race is called non-critical race. The final stable state that the circuit reaches depends on the order in which the state variables change, the race is called critical race. 5. How can a race be avoided? Races can be avoided by directing the circuit through intermediate unstable states with a unique state variable change. 6. Define cycle and merging? When a circuit goes through a unique sequence of unstable states, it is said to have a cycle. The grouping of stable states from separate rows into one common row is called merging. 7. Give state reduction procedure. The state reduction procedure for completely specified state tables is based on the algorithm that two states in a state table can be combined in to one if they can be shown to be equivalent. 8. Define hazards. Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delays. 9. Does Hazard occur in sequential circuit? If so what is the problem caused? Yes, Hazards occur in sequential circuit that is Asynchronous sequential circuit. It may result in a transition to a wrong state. 10. Give the procedural steps for determining the compatibles used for the purpose of merging a flow table. The purpose that must be applied in order to find a suitable group of compatibles for the purpose of merging a flow table can be divided into 3 procedural steps. i. Determine all compatible pairs by using the implication table. ii. Find the maximal compatibles using a Merger diagram iii. Find a minimal collection of compatibles that covers all the states and is closed. 11. What are the types of hazards? 1) Static 0 hazards 2) Static 1 hazard 3) Dynamic hazards

32 12. What is mealy and Moore circuit? Mealy circuit is a network where the output is a function of both present state and input. Moore circuit is a network where the output is function of only present state. 13. Differentiate Moore circuit and Mealy circuit? Moore circuit a. It is output is a function of present state only. b. Input changes do not affect the output. c. Moore circuit requires more number of states for implementing same function. Mealy circuit a. It is output is a function of present state as well as the present input. b. Input changes may affect the output of the circuit. c. It requires less numbers of states for implementing same function. 14. How can the hazards in combinational circuit be removed? Hazards in the combinational circuits can be removed by covering any two min terms that may produce a hazard with a product term common to both. The removal of hazards requires the addition of redundant gates to the circuit. 15. How does an essential hazard occur? An essential hazard occurs due to unequal delays along two or more paths that originate from the same input. An excessive delay through an inverter circuit in comparison to the delay associated with the feedback path causes essential hazard. 16. What is Timing diagram? Timing diagrams are frequently used in the analysis of sequential network. These diagrams show various signals in the network as a function of time. 17. What is setup and hold time? The definite time in which the input must be maintained at a constant value prior to the application of the pulse is setup time. The definite time is which the input must not change after the application of the positive or negative going transition of the pulse based on the triggering of the pulse. 18. Define equivalent state. If a state machine is started from either of two states and identical output sequences are generated from every possible set of sequences, then the two states are said to be equivalent.

33 19. What is gate delay? If the change in output is delayed by a time ε with respect to the input. We say that the gate has a propagation delay of ε. normally propagation delay for 0 to 1 output (ε1) may be different than the delay for 1 to 0 changes (ε2). 20. Define state reduction algorithm. State reduction algorithm is stated as Two states are said to be equivalent if, for each member of the set of inputs they give the same output and send the circuit either to the same state or to an equivalent state. When two states are equivalent, one of them can be removed without altering the input-output relation. 21. What is meant by level triggering? In level triggering the output of the flip-flop changes state or responds only when the clock pulse is present. 22. What are the problems involved in asynchronous circuits? The asynchronous sequential circuits have three problems namely, a. Cycles b. Races c. Hazards 23. Give t h e c o mp a r i s o n b e t w e e n s y n c h r o n o u s & s y n c h ro n o u s s e q u e n t i a l circuits? Synchronous sequential circuits Memory elements are clocked flip- Flops Easier to design Asynchronous sequential circuits. Memory elements are either unlocked flip - flops or time delay elements. More difficult to design 24. What is fundamental mode sequential circuit? 25. What is pulse mode circuit? input variables changes if the circuit is stable inputs are levels, not pulses only one input can change at a given time inputs are pulses widths of pulses are long for circuit to respond to the input pulse width must not be so long that it is still present after the new state is reached

34 26. What is the significance of state assignment? In synchronous circuits-state assignments are made with the objective of circuit reduction. Asynchronous circuits-its objective is to avoid critical races 27. What is SM chart? Just as flow charts are useful in software design, flow charts are useful in the hardware design of digital systems. These flow charts are called as State Machine Flow Charts or SM charts. SM charts are also called as ASMC (Algorithmic State machine chart). ASM chart describes the sequential operation in a digital system. 28. What are the three principal components of SM charts? The 3 principal components of SM charts are state box, decision box & Conditional output box. 29. What is decision box? A diamond shaped symbol with true or false branches represents a decision box. The condition placed in the box is a Boolean expression that is evaluated to determine which branch to take in SM chart. 30. What is link path? How many entrance paths & exit paths are there in SM block? A path through an SM block from entrance to exit is referred to as link path. An SM block has one entrance and exit path. 31. Differentiate ASM chart and conventional flow chart? A conventional Flow chart describes the sequence of procedural steps and decision paths for an algorithm without concern for their time relationship. The ASM chart describes the sequence of events as well as the timing relationships between the states of a sequential controller and the events that occur while going from one state to the next. PART B 1. Design an Asynchronous sequential circuit using SR latch with two inputs A and B and one output y. B is the control input which, when equal to 1, transfers the input A to output y. when B is 0, the output does not change, for any change in input. State Table Primitive Flow Table Formal Reduction (Implication Method) Merging Reduced Table K Map Simplification Logic Diagram

35 2. Give hazard free relation for the following Boolean function. F (A, B, C, D) =Σm (0, 2, 6, 7, 8, 10, 12) K Map simplification Create Hazard free link 3. Explain about Hazards? Explain Static Hazard Explain Dynamic Hazard 4. Explain about Races? Explain Critical Race Explain Non-Critical Race 5. Design T Flip flop from Asynchronous Sequential circuit? State Table Primitive Flow Table Formal Reduction (Implication Method) Merging Reduced Table K Map Simplification Logic Diagram 6. Explain with neat diagram the different hazards and the way to eliminate them. Classification of hazards Static hazard & Dynamic hazard definitions K map for selected functions Method of elimination Essential hazards 7. State with a neat example the method for the minimization of primitive flow table. Consider a state diagram Obtain the flow table Using implication table reduce the flow table Using merger graph obtain maximal compatibles Verify closed & covered conditions Plot the reduced flow table 8. Design a asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1 when T = 1 & c moves from 1 to 0. Otherwise the output is 0. Obtain the state diagram Obtain the flow table Using implication table reduce the flow table Using merger graph obtain maximal compatibles Verify closed & covered conditions Plot the reduced flow table

36 Obtain transition table Excitation table Logic diagram 9. Explain in detail about Races. Basics of races Problem created due to races Classification of races Remedy for races cycles 10. Explain the different methods of state assignment Three row state assignment Shared row state assignment Four row flow table Multiple row state assignment Prevention of races. ADDITIONAL QUESTIONS Unit I Boolean algebra and Logic Gates Part A 1. Find the hexadecimal equivalent of the decimal number Find the octal equivalent of the decimal number What is meant by weighted and non-weighted coding? 4. Convert A3BH and 2F3H into binary and octal respectively. 1. Find the decimal equivalent of (123)9. 2. Find the octal equivalent of the hexadecimal number ABC.D 3. Encode the ten decimal digits in the 2 out of 5 code. 4. Show that the Excess 3 code is self complementing. 5. Find the hexadecimal equivalent of the octal number Find the decimal equivalent of (346)7. 7. A hexadecimal counter capable of counting up to at least (10,000)10 is to be constructed.what is the minimum number of hexadecimal digits that the counter must have? 8. Convert the decimal number 214 to hexadecimal. 9. Convert to base Give an example of a switching function that contains only cyclic prime implicant. 11. Give an example of a switching function that for which the MSP from is not unique. 12. Express x+yz as the sum of minterms. 13. What is prime implicant? 14. Find the value of X = A B C (A+D) if A=0; B=1; C=1 and D= What are minterms and maxterms? 16. State and prove Demorgan s theorem. 17. Find the complement of x+yz. 18. Define the following: minterm and term. 19. State and prove Consensus theorem.

### VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD

### SHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI

SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL

### COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA

### KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL

### DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many

### (ii) Simplify and implement the following SOP function using NOR gates:

DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be

### BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS

BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS FREQUENTLY ASKED QUESTIONS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES

### VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201- DIGITAL PRINCIPLE AND SYSTEM DESIGN

### Injntu.com Injntu.com Injntu.com R16

1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

### UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)

SUBJECT NAME: DIGITAL LOGIC CIRCUITS YEAR / SEM : II / III DEPARTMENT : EEE UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. What is variable mapping? 2. Name the two canonical forms for Boolean algebra.

### SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented

### VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Academic Year 2018 19 III SEMESTER CS8351-DIGITAL PRINCIPLES AND SYSTEM DESIGN Regulation

### HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)

### B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don

www.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL

NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni-625531 Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering

### DIGITAL ELECTRONICS. Vayu Education of India

DIGITAL ELECTRONICS ARUN RANA Assistant Professor Department of Electronics & Communication Engineering Doon Valley Institute of Engineering & Technology Karnal, Haryana (An ISO 9001:2008 ) Vayu Education

### CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)

CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...

### END-TERM EXAMINATION

(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum

### CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES.

CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES. 1) Simplify the boolean function using tabulation method. F = (0, 1, 2, 8, 10, 11, 14, 15) List all

### R10. II B. Tech I Semester, Supplementary Examinations, May

SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31

### R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method

SET - 1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove de-morgan laws c) Implement two input EX-OR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

### Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)

### II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.

Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science

INDEX Absorption law, 31, 38 Acyclic graph, 35 tree, 36 Addition operators, in VHDL (VHSIC hardware description language), 192 Algebraic division, 105 AND gate, 48 49 Antisymmetric, 34 Applicable input

### R07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April

SET - 1 II B. Tech II Semester, Supplementary Examinations, April - 2012 SWITCHING THEORY AND LOGIC DESIGN (Electronics and Communications Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions

### 10EC33: DIGITAL ELECTRONICS QUESTION BANK

10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function

### INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester

### Code No: 07A3EC03 Set No. 1

Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,

### Scheme G. Sample Test Paper-I

Sample Test Paper-I Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable

### INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500043 Course Name : DIGITAL LOGIC DESISN Course Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : 2018 2019

### SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech

### R07

www..com www..com SET - 1 II B. Tech I Semester Supplementary Examinations May 2013 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, EIE, BME, ECC) Time: 3 hours Max. Marks: 80 Answer any FIVE Questions

### R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai

L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai- 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT - I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

### 3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0

1. The number of level in a digital signal is: a) one b) two c) four d) ten 2. A pure sine wave is : a) a digital signal b) analog signal c) can be digital or analog signal d) neither digital nor analog

### MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s. 2. Why the decimal number system is also called as positional number system?

MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s Unit-1 Number Systems 1. What does a decimal number represents? A. Quality B. Quantity C. Position D. None of the above 2. Why the

### Digital logic fundamentals. Question Bank. Unit I

Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative

Get Free notes at Module-I One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)

### SECTION-A

M.Sc(CS) ( First Semester) Examination,2013 Digital Electronics Paper: Fifth ------------------------------------------------------------------------------------- SECTION-A I) An electronics circuit/ device

### Model EXAM Question Bank

VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI Department of Information Technology Model Exam -1 1. List the main difference between PLA and PAL. PLA: Both AND and OR arrays are programmable

### PART B. 3. Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).

II B. Tech II Semester Regular Examinations, May/June 2015 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, ECC, EIE.) Time: 3 hours Max. Marks: 70 Note: 1. Question Paper consists of two parts (Part-A

### Hours / 100 Marks Seat No.

17333 13141 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Illustrate your answers with neat sketches wherever necessary. (4)

### DE Solution Set QP Code : 00904

DE Solution Set QP Code : 00904 1. Attempt any three of the following: 15 a. Define digital signal. (1M) With respect to digital signal explain the terms digits and bits.(2m) Also discuss active high and

### PROGRAMMABLE LOGIC DEVICES

PROGRAMMABLE LOGIC DEVICES Programmable logic devices (PLDs) are used for designing logic circuits. PLDs can be configured by the user to perform specific functions. The different types of PLDs available

### Computer Logical Organization Tutorial

Computer Logical Organization Tutorial COMPUTER LOGICAL ORGANIZATION TUTORIAL Simply Easy Learning by tutorialspoint.com tutorialspoint.com i ABOUT THE TUTORIAL Computer Logical Organization Tutorial Computer

### COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic

### CS8803: Advanced Digital Design for Embedded Hardware

CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883

### KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class

### Reference Sheet for C112 Hardware

Reference Sheet for C112 Hardware 1 Boolean Algebra, Gates and Circuits Autumn 2016 Basic Operators Precedence : (strongest),, + (weakest). AND A B R 0 0 0 0 1 0 1 0 0 1 1 1 OR + A B R 0 0 0 0 1 1 1 0

### Logic design Ibn Al Haitham collage /Computer science Eng. Sameer

DEMORGAN'S THEOREMS One of DeMorgan's theorems stated as follows: The complement of a product of variables is equal to the sum of the complements of the variables. DeMorgan's second theorem is stated as

### Boolean Algebra and Logic Gates

Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can

### UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable

UNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination

### Switching Theory & Logic Design/Digital Logic Design Question Bank

Switching Theory & Logic Design/Digital Logic Design Question Bank UNIT I NUMBER SYSTEMS AND CODES 1. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read from memory. What was

### Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition

Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition Table of Contents 1. Introduction to Digital Logic 1 1.1 Background 1 1.2 Digital Logic 5 1.3 Verilog 8 2. Basic Logic Gates 9

### D I G I T A L C I R C U I T S E E

D I G I T A L C I R C U I T S E E Digital Circuits Basic Scope and Introduction This book covers theory solved examples and previous year gate question for following topics: Number system, Boolean algebra,

### This tutorial gives a complete understanding on Computer Logical Organization starting from basic computer overview till its advanced architecture.

About the Tutorial Computer Logical Organization refers to the level of abstraction above the digital logic level, but below the operating system level. At this level, the major components are functional

### 1. Mark the correct statement(s)

1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another

### CHAPTER - 2 : DESIGN OF ARITHMETIC CIRCUITS

Contents i SYLLABUS osmania university UNIT - I CHAPTER - 1 : BASIC VERILOG HDL Introduction to HDLs, Overview of Digital Design With Verilog HDL, Basic Concepts, Data Types, System Tasks and Compiler

### SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: Sri A.M.K.KANNA

### Presentation 4: Programmable Combinational Devices

Presentation 4: Programmable Combinational Devices Asst. Prof Dr. Ahmet ÖZKURT DEUEEE Based on the Presentation by Prof. Kim, Young Ho Dept. of Information Computer Engineering E-mail : yhkim@hyowon.cs.pusan.ac.kr

### UNIT- V COMBINATIONAL LOGIC DESIGN

UNIT- V COMBINATIONAL LOGIC DESIGN NOTE: This is UNIT-V in JNTUK and UNIT-III and HALF PART OF UNIT-IV in JNTUA SYLLABUS (JNTUK)UNIT-V: Combinational Logic Design: Adders & Subtractors, Ripple Adder, Look

### DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER.

DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER 2015 2016 onwards DIGITAL ELECTRONICS CURRICULUM DEVELOPMENT CENTRE Curriculum Development

### Unit 6 1.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2.Programmable Logic

EE 200: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Unit 6.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2. Logic Logic and Computer Design Fundamentals Part Implementation

### Contents. Chapter 3 Combinational Circuits Page 1 of 34

Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4

### Digital Logic Design Exercises. Assignment 1

Assignment 1 For Exercises 1-5, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system

### UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I - NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal- Binary- Octal- Hexadecimal number systems-inter conversions-bcd code- Excess

### Course Batch Semester Subject Code Subject Name. B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits

Course Batch Semester Subject Code Subject Name B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits Part-A 1 Define De-Morgan's theorem. 2 Convert the following hexadecimal number to decimal

### Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 2-1 Binary Logic and Gates 2-2 Boolean Algebra 2-3 Standard Forms 2-4 Two-Level Circuit Optimization

### DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the

### BHARATHIDASAN ENGINEERING COLLEGE

BHARATHIDASAN ENGINEERING COLLEGE CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (FOR COMMON TO 2 SEM CSE & IT) Lecturer notes Prepared by L.Gopinath M.tech Assistant professor UNIT 1 BOOLEAN ALGEBRS AND

### GATE CSE. GATE CSE Book. November 2016 GATE CSE

GATE CSE GATE CSE Book November 2016 GATE CSE Preface This book is made thanks to the effort of GATE CSE members and Praneeth who made most of the latex notes for GATE CSE. Remaining work of completing

### Hours / 100 Marks Seat No.

17320 21718 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Figures to the right indicate full marks. (4) Assume suitable data,

### DLD VIDYA SAGAR P. potharajuvidyasagar.wordpress.com. Vignana Bharathi Institute of Technology UNIT 3 DLD P VIDYA SAGAR

DLD UNIT III Combinational Circuits (CC), Analysis procedure, Design Procedure, Combinational circuit for different code converters and other problems, Binary Adder- Subtractor, Decimal Adder, Binary Multiplier,

### TEACHING & EXAMINATION SCHEME For the Examination COMPUTER SCIENCE. B.Sc. Part-I

TEACHING & EXAMINATION SCHEME For the Examination -2015 COMPUTER SCIENCE THEORY B.Sc. Part-I CS.101 Paper I Computer Oriented Numerical Methods and FORTRAN Pd/W Exam. Max. (45mts.) Hours Marks 150 2 3

NOTIFICATION (Advt No. 1/2018) Syllabus (Paper III) Post Code - 302 Area: Instrumentation COMPUTER PROGRAMMING AND APPLICATION 1. OVERVIEW OF PROGRAMMING: Steps in program development, problem identification,

### ii) Do the following conversions: output is. (a) (101.10) 10 = (?) 2 i) Define X-NOR gate. (b) (10101) 2 = (?) Gray (2) /030832/31034

No. of Printed Pages : 4 Roll No.... rd 3 Sem. / ECE Subject : Digital Electronics - I SECTION-A Note: Very Short Answer type questions. Attempt any 15 parts. (15x2=30) Q.1 a) Define analog signal. b)

### Presented By :- Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak

Presented By :- Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak Content - Introduction -2 Feature -3 Feature of BJT -4 TTL -5 MOS -6 CMOS -7 K- Map - Introduction Logic IC ASIC: Application Specific

### Lecture (05) Boolean Algebra and Logic Gates

Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either

### NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary

### Written exam for IE1204/5 Digital Design Thursday 29/

Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when

### QUESTION BANK FOR TEST

CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

### MLR Institute of Technology

MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad 500 043 Course Name Course Code Class Branch ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK : DIGITAL DESIGN

### Chapter 3. Gate-Level Minimization. Outlines

Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level

### Chapter 2. Boolean Algebra and Logic Gates

Chapter 2. Boolean Algebra and Logic Gates Tong In Oh 1 Basic Definitions 2 3 2.3 Axiomatic Definition of Boolean Algebra Boolean algebra: Algebraic structure defined by a set of elements, B, together

### Combinational Circuits

Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables

### 2.1 Binary Logic and Gates

1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary

### St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad

St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad-500 014 Subject: Digital Design Using Verilog Hdl Class : ECE-II Group A (Short Answer Questions) UNIT-I 1 Define verilog HDL? 2 List levels of

### INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad ELECTRONICS AND COMMUNICATIONS ENGINEERING

INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 00 0 ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK Course Name : DIGITAL DESIGN USING VERILOG HDL Course Code : A00 Class : II - B.

### Question No: 1 ( Marks: 1 ) - Please choose one A SOP expression is equal to 1

ASSALAM O ALAIKUM all fellows ALL IN ONE Mega File CS302 Midterm PAPERS, MCQz & subjective Created BY Farhan& Ali BS (cs) 3rd sem Hackers Group Mandi Bahauddin Remember us in your prayers Mindhacker124@gmail.com

### 1. Draw general diagram of computer showing different logical components (3)

Tutorial 1 1. Draw general diagram of computer showing different logical components (3) 2. List at least three input devices (1.5) 3. List any three output devices (1.5) 4. Fill the blank cells of the

### Boolean Algebra. BME208 Logic Circuits Yalçın İŞLER

Boolean Algebra BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com 5 Boolean Algebra /2 A set of elements B There exist at least two elements x, y B s. t. x y Binary operators: +

### Chap.3 3. Chap reduces the complexity required to represent the schematic diagram of a circuit Library

3.1 Combinational Circuits 2 Chap 3. logic circuits for digital systems: combinational vs sequential Combinational Logic Design Combinational Circuit (Chap 3) outputs are determined by the present applied

### Combinational Logic with MSI and LSI

1010101010101010101010101010101010101010101010101010101010101010101010101010101010 1010101010101010101010101010101010101010101010101010101010101010101010101010101010 1010101010101010101010101010101010101010101010101010101010101010101010101010101010