Pearson Education Limited Edinburgh Gate Harlow Essex CM20 2JE England and Associated Companies throughout the world

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2 Pearson Education Limited Edinburgh Gate Harlow Essex M2 2JE England and Associated ompanies throughout the world Visit us on the World Wide Web at: Pearson Education Limited 24 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without either the prior written permission of the publisher or a licence permitting restricted copying in the United Kingdom issued by the opyright Licensing Agency Ltd, Saffron House, 6 Kirby Street, London EN 8TS. All trademarks used herein are the property of their respective owners. The use of any trademark in this text does not vest in the author or publisher any trademark ownership rights in such trademarks, nor does the use of such trademarks imply any affiliation with or endorsement of this book by such owners. ISBN : ISBN 3: British Library ataloguing-in-publication Data A catalogue record for this book is available from the British Library Printed in the United States of America

3 25. Define the domain of each SOP expression in Problem 23 and convert the expression to standard SOP form. 26. onvert each SOP expression in Problem 24 to standard SOP form. 27. Determine the binary value of each term in the standard SOP expressions from Problem Determine the binary value of each term in the standard SOP expressions from Problem onvert each standard SOP expression in Problem 25 to standard POS form. 3. onvert each standard SOP expression in Problem 26 to standard POS form. Section 7 Boolean Expressions and Truth Tables 3. Develop a truth table for each of the following standard SOP expressions: (a) (b) Y Z YZ YZ YZ YZ 32. Develop a truth table for each of the following standard SOP expressions: (a) D D D A B D (b) WYZ WYZ WYZ WYZ WYZ 33. Develop a truth table for each of the SOP expressions: (a) A (b) YZ WZ YZ 34. Develop a truth table for each of the standard POS expressions: (a) (b) (A B )(A B )(A B ) (A B D)(A B D)(A B D)(A B D) 35. Develop a truth table for each of the standard POS expressions: (a) (A B)(A )(A B ) (b) (A B)(A B )(B D)(A B D) 36. For each truth table in Table, derive a standard SOP and a standard POS expression. TLE A B D A B D A B A B (a) (b) (c) (d) Section 8 The Karnaugh Map 37. Draw a 3-variable Karnaugh map and label each cell according to its binary value. 38. Draw a 4-variable Karnaugh map and label each cell according to its binary value. 39. Write the standard product term for each cell in a 3-variable Karnaugh map. 233

4 Section 9 Karnaugh MAP SOP Minimization 4. Use a Karnaugh map to find the minimum SOP form for each expression: (a) A B A B (b) A(B ) (c) A(B B) A(B B) (d) A B 4. Use a Karnaugh map to simplify each expression to a minimum SOP form: (a) A B (b) A3B B(B ) 4 (c) DEF DEF D E F 42. Expand each expression to a standard SOP form: (a) (b) A B (c) D AD BD D (d) D D BD D 43. Minimize each expression in Problem 42 with a Karnaugh map. 44. Use a Karnaugh map to reduce each expression to a minimum SOP form: (a) A B D (b) A B D A B D D D (c) ( D D) ( D D) D (d) (A B )(D D) (e) A B D D 45. Reduce the function specified in truth Table to its minimum SOP form by using a Karnaugh map. 46. Use the Karnaugh map method to implement the minimum SOP expression for the logic function specified in truth Table Solve Problem 46 for a situation in which the last six binary combinations are not allowed. TLE TLE 2 INPUTS A B OUTPUT INPUTS OUTPUT A B D Section Five-Variable Karnaugh Maps 48. Plot the expression DE A BDE and simplify if possible. 49. Minimize the following SOP expression using a Karnaugh map: DE A B DE DE D E DE DE A B D E A BDE DE DE 234

5 5. Apply the Karnaugh map method to minimize the following SOP expression: A VWYZ VWYZ VWYZ VWYZ VWYZ V W Y Z V W YZ V WY Z VW Y Z Section Describing Logic with an HDL 5. Write a VHDL program for the logic circuit in Figure 57. FIGURE 57 A B D E F G H I 52. Write a program in VHDL for the expression Y A B System Application Activity 53. If you are required to choose a type of digital display for low light conditions, will you select LED or LD 7-segment displays? Why? 54. Explain the purpose of the invalid code detector. 55. For segment c, how many fewer gates and inverters does it take to implement the minimum SOP expression than the standard SOP expression? 56. Repeat Problem 55 for the logic for segments d through g. Special Design Problems 57. The logic for segments b and c in Figure 49 produces LOW outputs to activate the segments. If a type of 7-segment display is used that requires a HIGH to activate a segment, modify the logic accordingly. 58. Redesign the logic for segment a in the application activity to include the letter F in the display. 59. Repeat Problem 58 for segments b through g. 6. Design the invalid code detector. Multisim Troubleshooting Practice 6. Open file P4-6 on apply input signals, and observe the operation of the logic circuit. Determine whether or not a fault exists. 62. Open file P4-62, apply input signals, and observe the operation of the logic circuit. Determine whether or not a fault exists. 63. Open file P4-63, apply input signals, and observe the operation of the logic circuit. Determine whether or not a fault exists. ANSWERS SETION HEKUPS Section Section 2 Boolean Operations and Expressions. A 2. A, B, ; A B 3. A, B, ; Laws and Rules of Boolean Algebra. A (B D) (A B ) D 2. A(B D) A AD 235

6 Section 3 DeMorgan s Theorems. (a) (D E) A B DE (b) (c) A B DE A B D E (A B) A B Section 4 Section 5 Section 6 Boolean Analysis of Logic ircuits. ( D)B A 2. Abbreviated truth table: The expression is a when A is or when B and are s or when B and D are s. The expression is for all other variable combinations. Simplification Using Boolean Algebra. (a) A A (b) (A B) (A B) (c) (BD DE) A A( BDE) 2. (a) Original: 2 AND gates, OR gate, inverter; Simplified: No gates (straight connection) (b) Original: 2 OR gates, 2 AND gates, inverter; Simplified: OR gate, AND gate, inverter (c) Original: 5 AND gates, 2 OR gates, 2 inverters; Simplified: 2 AND gates, OR gate, 2 inverters Standard Forms of Boolean Expressions. (a) SOP (b) standard POS (c) standard SOP (d) POS 2. (a) D D D D D D A BD D (c) Already standard 3. (b) Already standard (d) (A B )(A B )(A B )(A B ) Section 7 Boolean Expressions and Truth Tables WYZ 3. W Y Z Section 8 Section 9 Section Section The Karnaugh Map. (a) upper left cell: (b) lower right cell: (c) lower left cell: (d) upper right cell: 2. (a) upper left cell: Y Z (b) lower right cell: YZ (c) lower left cell: Y Z (d) upper right cell: YZ 3. (a) upper left cell: (b) lower right cell: (c) lower left cell: (d) upper right cell: 4. (a) upper left cell: W Y Z (b) lower right cell: WYZ (c) lower left cell: W Y Z (d) upper right cell: W YZ Karnaugh Map SOP Minimization. 8-cell map for 3 variables; 6-cell map for 4 variables 2. B A B 3. (a) A B (b) A B A B (c) A B D A B D D D D D D D (d) A B D D D D D D D A BD D D D Five-Variable Karnaugh Maps. There are 32 combinations of 5 variables (2 5 32). 2. because the function is for all possible combinations of 5 variables. Describing Logic with an HDL. An HDL is a hardware description language for programmable logic. 2. Entity and architecture 236

7 3. The entity specifies the inputs and outputs of a logic function. 4. The architecture specifies operation of a logic function. RELATED PROBLEMS FOR EAMPLES A B when A and B. 2 A B when A and B. 3 YZ 4 W Y Z 5 D E 6 (A B D)E 7 D A B D 8 Results should be same as example. 9 D A A B 2 A B 3 Results should be same as example. 4 A B 5 6 WYZ WYZ WYZ W YZ WYZ WY Z,,,,. Yes 7 (A B )(A B )(A B )(A B ) 8,,,,. Yes 9 SOP and POS expressions are equivalent. 2 See Table 3. 2 See Table 4. TLE 3 A B TLE 4 A B 22 The SOP and POS expressions are equivalent. 23 See Figure See Figure See Figure See Figure No other ways 28 B A AD D 29 D B 3 Q Y 3 Q Y Z WZ WYZ D D FIGURE 58 FIGURE 59 FIGURE 6 FIGURE 6 237

Digital Electronics A Practical Approach with VHDL William Kleitz Ninth Edition

Digital Electronics A Practical Approach with VHDL William Kleitz Ninth Edition Pearson Education Limited Edinburgh Gate Harlow Essex CM20 2JE England and Associated Companies throughout the world Visit