Schematic design. Gate level design. 0 EDA (Electronic Design Assistance) 0 Classical design. 0 Computer based language

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1 1 / /11/20 0 EDA (Electronic Design Assistance) 0 Computer based language 0 HDL (Hardware Description Language) 0 Verilog HDL 0 Created by Gateway Design Automation Corp. in 1983 First modern hardware description language 0 Adopted by IEEE as standard 1364 in 1995: Verilog 95, Verilog 2001, and Verilog VHDL (Very high speed integrated circuit Hardware Description Language) 0 Originally developed in Adopted by IEEE as standard 1076 in Could be used to describe digital circuits at a Register Transfer Level (RTL) 0 Specify how the data flows between registers and how the design processes the data 0 Logic synthesis tools can be used to produce gate level netlist from the RTL description automatically 0 Classical design Gate level design Schematic design

2 2 / /11/20 Line Termination and Grouping 0 Why HDL? 0 Most Importantly 0 The ability to use Logic Synthesis tools to translate HDL code into logic gates for chosen target library 0 Mostly automated process 0 Designer sets goals for timing (speed) or area (gate count) 0 Read and write data from file for effective simulations 0 Ability to use real world stimulus (ucode, test patterns) 0 Why Verilog? 0 Easy to learn and use 0 Syntax is similar to "C" software language (VHDL is similar to PASCAL) 0 Most popular logic synthesis tools support Verilog 0 Allows different levels of abstraction to be mixed in the same model 0 In terms of switches, gates, RTL, or behavioral code 0 Need to learn only for stimulus and hierarchical design 0 A ";" is used for line termination. Continuation or wrapping over multiple lines is allowed except for file writing 0 A group of statements can be put or grouped together with "begin" and "end" statement 0 Comments 0 "//" single line comment until end of line // This is a comment until the end of the line 0 "/* */" multi line comments beginning with /* and ending with */ /* This is a multi line comment */ 0 Variable naming 0 First character must begin with "a z" "A Z" "_" 0 The remaining characters can use "a z" "A Z" "_" "0 9" "$" 0 There is a list of reserved keywords in Verilog Guidelines 0 Keywords are in lower case 0 There is no practical limit to Verilog naming, but most FPGA/ASIC tools put some limit of about 16 characters 0 Upper and Lower case names (BER & ber) may get mapped to same name, so highly suggested not to use both in coding!!! 0 Verilog consists of only four basic values. Almost all Verilog data type store all these values 0 0 logic 0 / false condition 0 1 logic 1 / true condition 0 X unknown logic value 0 Z high impedance state

3 3 / /11/20 Strength Level Type Specification Keyword Degree 7 supply Driving supply0 supply1 Strongest 6 strong Driving strong0 strong1 5 pull Driving pull0 pull1 4 large Storage Large 3 weak Driving weak0 weak1 2 medium Storage medium 1 small Storage small 0 highz High Impedance highz0 highz1 Weakest Modeling of weak transistor Simple Latch Circuit 0 Logic value can have 8 strength level 0 4 driving, 3 storage, and high impedance 0 A net with multiple drivers can have a combination of strengths, represented as a pair of octal numbers, plus the value (e.g. 65X) 0 Signal strength are used by the Verilog simulator in two main situations 0 Modeling of weak (resistive) transistors 0 Resolving signal contention 0 If two signals of unequal strength combine in a wired net configuration, the stronger signal is the result 0 Two signals of equal strength and opposite value combine, the result has a value of x and the strength levels of both signals and all the smaller strength levels

4 4 / /11/20 0 Nets 0 Connects between hardware elements 0 Must be continuously driven by 0 Continuous assignment (assign) 0 Module or gate instantiation (output ports) 0 Define initial value for a wire is 'Z' (and for a trireg is 'X') 0 A net does not store a value (except for the trireg net) 0 Registers 0 Represent data storage elements 0 Retain value until another value is placed on to them 0 Similar to 'variables' in other high level language 0 Different to edge triggered flip flip in real circuits 0 Do not need clock 0 Default initial value for a reg is 'X' wire 0 Verilog has two major data type classes: 0 Net data types 0 Used to make connections between parts of a design 0 Nets reflect the value and strength level of the drivers of the net or the capacitance of the net, and do not have a value of their own 0 Variable data types 0 Used as temporary storage of programming data 0 Variables can only be assigned a value form within an initial procedure, an always procedure, a task or a function 0 Variables can only store logic; they cannot store logic strength 0 The most common and important net types 0 wire : single driver 0 Represents a physical wire in a circuit and is used to connect gates or modules 0 The value of a wire can be read, but not assigned to, in a function or block 0 A wire does not store its value but must be driven by a continuous assignment statement or by connecting it to the output od a gate or module 0 wand (wire AND): the value of a wand depend on logical AND of all the drivers connected to it 0 wor (wire OR): the value of a wor depend on logical OR of all the drivers connected to it

5 5 / /11/20 tri 0 For multiple driver that are wired together 0 tri (Three state): all drivers connected to a tri must be z, except on (which determines the value of the tri) 0 triand (tri AND) 0 trior (tri OR) 0 tri0: pull down 0 tri1: pull up 0 trireg (tri register): for net with capacitive storage 0 If all drivers at z, previous value is retained 0 Two states: 0 Driven state: at least one driver drives 0, 1, x 0 Capacitive state: 0 All driver have high impedance "z" 0 Strength: small, medium, large; default is medium An Example for wire, tri0, and tri1 Results:? 0 Syntax 0 wire [msb:lsb] wire_variable_list; 0 wand [msb:lsb] wand_variable_list; 0 wor [msb:lsb] wor_variable_list; 0 tri [msb:lsb] tri_variable_list; 0 reg 0 Any size, unsigned 0 Represents register or data storage element 0 Can hold values depending on conditions 0 It can represent registers, latches, memory (RAM or ROM), and asynchronous combinatorial logic 0 Can be scalar (single bit), vector (n bit wide), or 2 D array (RAM/ROM) 0 Cannot be used for input port declaration 0 Can be used in two types of assignment blocks 0 initial 0 always

6 6 / /11/20 0 integer 0 integet a, b; // declaration 0 32 bit signed (2's complement) 0 time 0 64 bit unsigned, behaves like a 64 bit reg 0 #display("at %t, value=%d", $time, val_now); 0 real 0 real c, d; // declaration 0 64 bit real number 0 Default to an initial value of 0 Examples Size Sign Radix Binary Equivalent 10 'o7 1'b1 8'sHc5 6'hF0 6'hA 6'shA 6'bz Verilog Operators 0 Sized numbers 0 <size>'<signed><base_format><number> 0 <size> is in decimal and specifies the number of bits 0 '<signed> is: 's signed number are interpreted as 2's complement values 0 <base_format> is: d D h H b B o O 0 The <number> digits are 0~f, uppercase may be used 0 Unsized numbers the <size> is not specified (default is simulator/compiler specific, >= 32bits) 0 Number without a base are decimal by default

7 7 / /11/20 Verilog Operators 0 Concatenation operator {,} 0 Provides a way to append busses or wire to make busses 0 The operands must be sized 0 Expressed as operands in braces separated by commas 0 assign a1 = (3+2) % 2; // a1 = 0 assign a2 = 4>>1; assign a3 = 1<<2; // a2 = a3= 0 assign ax = (1==1'bx); // ax = 0 assign bx = (1'bx!= 1'bz); // bx = 0 assign d0 = (1==0); // d0 = 0 assign d1 = (1==1); // d1 = 0 assign e0 = (1===1'bx); // e0 = 0 assign e1 = (4'b01xz===4'b01xz); // e1 = 0 assign f0 = (4'bxxxx===4'bxxxx); // f0 = 0 assign x0 =a? b : c ; // Verilog Operators 0 Replication Operator { { } } 0 Repetitive concatenation of the same number 0 Operands are number of repetitions, and the bus or wire

8 8 / /11/20 0 Gate level modeling 0 Dataflow modeling 0 Behavioral modeling 0 The following gates are built in types in the simulator 0 and, nand, nor, or, xor, xnor 0 First terminal is output, followed by inputs 0 and a1 (out1, in1, in2); 0 nand a2 (out2, in21, in22, in23, in24); 0 buf, not 0 One or more outputs first, followed by one input 0 not N1 (OUT1, OUT2, OUT3, OUT4, INA); 0 buf B1 (BO1, BIN); not in out x x z x buf in out x x z x 0 bufif0, bufif1, notif0, notif1: three state drivers 0 Output terminal first, then input, then control 0 bufif1 BF1 (OUTA,INA,CTRLA); 0 pullup, pulldown 0 Put 1 or 0 on all terminals 0 pullup PUP (PWRA, PWRB, PWRC); 0 Instance names are optional 0 ex: not (QBAR, Q)

9 9 / /11/20 Gate Level Modeling Example: 2 to 1 Decoder by using Buffer Example: 4 to 1 Mux 0 Dataflow Style 0 Higher level than gate level 0 Design circuit in terms of the data flow between register 0 Can be viewed as part of RTL 0 RTL=behavior modeling + data flow modeling 0 Assign a value to a net using continuous assignment

10 10 / /11/20 net_type [size] net_name; assign #(delay) net_name = expression; 0 Continuous assignment drive net types with the result of an expression 0 The result is automatically updated anytime a value on the right hand side changes 0 net_type may be any of the net data types except trireg 0 expression may include any data type, any operator, and calls to functions 0 Continuous assignment are declared outside of procedural blocks 0 Automatically become active at time zero, and are evaluated concurrently with procedural blocks, module instances, and primitive instances Continuous Assignment Example

11 11 / /11/20 0 Procedural blocks: 0 initial block: executes only once 0 always block: executes in a loop 0 Block execution is triggered based on user specified conditions 0 (posedge clk) 0 All procedural blocks are automatically activated at time 0 0 All procedural blocks are executed concurrently 0 reg is the main data type that is manipulated within a sequential block 0 It holds its value until assigned a new value 0 Executes continuously; must be used with some form of timing control 0 always (timing_control) statements 0 Four forms of event expressions are often used 0 An OR of several identifiers (comb/seq logic) 0 The rising edge of a identifier (for clock signal of a register) 0 The falling edge of a identifier (for clock signal of a register) 0 Delay control (for waveform generator) 0 Multiple always block operate in parallel, not in sequence or order 0 Any number of initial and always statements may appear within a module 0 Initial and always statements are all executed in parallel D Flip flop example with asynchronous reset 0 All initial blocks start execution in parallel at zero time (0ns) 0 This always a parallel programming method to have multiple signals in a test bench to be independently controlled 0 An initial block is only executed once in a Verilog simulation 0 All of the time references occur at the same time 0 Only used in testbench 0 The assignment statements that can be used inside an alwaysor initial block 0 The target must be a register or integer type 0 Two types of procedural assignment statement 0 Non blocking procedural assignment 0 Blocking procedural assignment

12 12 / /11/20 Procedural Assignment Statement Blocking Procedural 0 Variable = expression; 0 Blocking procedural assignment 0 Expression is evaluated and assigned when the statement is encountered 0 In a begin~end sequential statement group, execution of the next statement is blocked until the assignment is complete Procedural Assignment Statement Non blocking Procedural 0 Variable <= expression; 0 Non blocking procedural assignment 0 Expression is evaluated when the statement is encountered, and assignment is postponed until the end of the simulation time step 0 In a begin~end sequential statement group, execution of the next statement is not blocked; and will be evaluated before the assignment is complete

13 13 / /11/20 Non blocking Procedural Assignment This is wrong!! Non blocking Procedural Assignment This is correct!!

14 14 / /11/20 0 Simple sequential pipeline register 0 Simple sequential pipeline register Bad blocking assignment sequential coding #1 Good non blocking assignment sequential coding #1 0 Simple sequential pipeline register 0 To avoid potential simulation race conditions in zero delay models 0 Use blocking assignments (=) to model combinational logic 0 Use non blocking assignment (<=) to model sequential logic Bad blocking assignment sequential coding #2 but it works!

15 15 / /11/20 Mixed Blocking and Non blocking Assignment Procedural Programming Statements 0 Verilog permits blocking and non blocking assignments to be freely mixed inside of an always block 0 In general, mixing blocking and non blocking assignments in the same always block is a poor coding style, even if Verilog permits it Blocking and non blocking assignment in the same always block generally a bad idea! Procedural Programming Statements 0 Behavioral Style 0 It specifies the circuit in terms of its expected behavior 0 It is the closest to a natural language description of the circuit functionality, but also the most difficult to synthesize