ECE 645: Lecture 1. Basic Adders and Counters. Implementation of Adders in FPGAs

Transcription

1 ECE 645: Lecture Basic Adders and Counters Implementation of Adders in FPGAs

2 Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 5, Basic Addition and Counting, Sections , pp

3 Required Reading Spartan-3 Generation FPGA User Guide Chapter 9, Using Carry and Arithmetic Logic

4 Half-adder c s HA x y 2 x + y = ( c s ) 2 x y c s

5 Half-adder Alternative implementations () a) c = xy s = x y b) c = x + y s = xy + xy

6 Half-adder Alternative implementations (2) c) c = xy s = xc + yc = xc yc

7 Full-adder x y c out s FA x + y + c in = ( c out s ) 2 2 x y c out s c in c in

8 a) Full-adder Alternative implementations (2) c out = xy + xc in + yc in s = x y c in = xyc in + xyc in + xyc in + xyc in

9 Full-adder Alternative implementations () b) s = (x y) c in c out = xy + c in (x y) c c s

10 Full-adder Alternative implementations (3) c) x y c out s c in c in c in c in c in c in

11 Full-adder Alternative implementations (4) Implementation used to generate fast carry logic in Xilinx FPGAs x y c out y c in c in y p = x y g = y x y A2 A XOR D p g C out C in S s= p c in = x y c in

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15 Latency of a k-bit ripple-carry adder d RCA (k) = d FA (x,y c out ) + + (k-2) d FA (c in c out ) + + d FA (c in s) Latency = a k + b

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17 Unsigned addition vs. signed addition weight carry + = X Y S Machine Unsigned mind Programmer Signed mind x 7 y 7 x 6 y 6 x 5 y 5 x 4 y 4 x 3 y 3 x 2 y 2 x y x y c 8 FA c 7 FA c 6 FA c 5 FA c 4 FA c 3 FA c 2 FA c FA s 7 s 6 s 5 s 4 s 3 s 2 s s

18 Out of range flags Carry flag - C out-of-range for unsigned numbers C = if result > MAX_UNSIGNED or result < otherwise where MAX_UNSIGNED = for 8-bit operands for 6-bit operands Overflow flag - V out-of-range for signed numbers V = if result > MAX_SIGNED or result < MIN_SIGNED otherwise where MAX_SIGNED = for 8-bit operands for 6-bit operands MIN_SIGNED = -2 7 for 8-bit operands -2 5 for 6-bit operands

19 Overflow for signed numbers Indication of overflow Positive + Positive = Negative Negative + Negative = Positive Formulas Overflow 2 s complement = x k- y k- s k- + x k- y k- s k-

20 Addition of Signed and Unsigned Numbers C= and V= C= and V=

21 Addition of Signed and Unsigned Numbers C= and V= C= and V=

22 Two s complement representation of signed integers

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24 Overflow for signed numbers () Indication of overflow Positive + Positive = Negative Negative + Negative = Positive Formulas Overflow 2 s complement = x k- y k- s k- + x k- y k- s k- = = c k c k-

25 Overflow for signed numbers (2) x k- y k- c k- c k s k- overflow c k c k-

26 Implementation of Adders in FPGAs

27 Xilinx FPGA Devices Technology Low- cost High- performance 22 nm Spartan II Virtex 2/5 nm Virtex II, II Pro 9 nm Spartan 3 Virtex 4 65 nm Virtex 5 45 nm Spartan 6 4 nm Virtex 6 28 nm Ar<x 7 Virtex 7

28 Altera FPGA Devices Technology Low- cost Mid- range High- performance 3 nm Cyclone Stra<x 9 nm Cyclone II Stra<x II 65 nm Cyclone III Arria I Stra<x III 4 nm Cyclone IV Arria II Stra<x IV 28 nm Cyclone V Arria V Stra<x V

29 General structure of an FPGA Programmable interconnect Programmable logic blocks The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 24 Mentor Graphics Corp. ( 29

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31 Xilinx Spartan 3 FPGAs Configurable logic block (CLB) Slice Slice CLB CLB Logic cell Logic cell Logic cell Logic cell Slice Slice CLB CLB Logic cell Logic cell Logic cell Logic cell The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 24 Mentor Graphics Corp. ( 3

32 CLB Slice Structure Each slice contains two sets of the following: Four-input LUT Any 4-input logic function, or 6-bit x sync RAM (SLICEM only) or 6-bit shift register (SLICEM only) Carry & Control Fast arithmetic logic Multiplier logic Multiplexer logic Storage element Latch or flip-flop Set and reset True or inverted inputs Sync. or async. control 32

33 33 COUT D Q CK S R EC D Q CK R EC O G4 G3 G2 G Look-Up Table Carry & Control Logic O YB Y F4 F3 F2 F XB X Look-Up Table F5IN BY SR S Carry & Control Logic CIN CLK CE SLICE Carry & Control Logic

34 Carry & Control Logic in Xilinx FPGAs x y COUT y CIN CIN y x y Propagate = x y Generate = y Sum= Propagate CIN = x y CIN

35 Carry & Control Logic in Spartan 3 FPGAs x y LUT Hardwired (fast) logic

36 x y Simplified View of Spartan-3 FPGA Carry and Arithmetic Logic in One Logic Cell

37 Simplified View of Carry Logic in One Spartan 3 Slice

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39 Critical Path for an Adder Implemented Using Xilinx Spartan 3 FPGAs

40 Number and Length of Carry Chains for Spartan 3 FPGAs

41 Bottom Operand Input to Carry Out Delay T OPCYF.9 ns for Spartan 3

42 .2 ns for Spartan 3 Carry Propagation Delay t BYP

43 Carry Input to Top Sum Combinational Output Delay T CINY.2 ns for Spartan 3

44 Critical Path Delays and Maximum Clock Frequencies (taking into account surrounding registers)

45 Major Differences between Xilinx Families Look-Up Tables Spartan 3 Virtex 4 4-input Virtex 5, Virtex 6, Spartan 6 6-input Number of CLB slices per CLB Number of LUTs per CLB slice Number of adder stages per CLB slice

46 Altera Cyclone III Logic Element (LE) Normal Mode

47 Altera Cyclone III Logic Element (LE) Arithmetic Mode

48 Altera Stratix III, Stratix IV Adaptive Logic Modules (ALM) Normal Mode

49 Altera Stratix III, Stratix IV Adaptive Logic Modules (ALM) Arithmetic Mode

50 Addition of a Constant

51 Addition of a constant () + x k- x k-2... x x y k- y k-2... y y s k- s k-2... s s variable constant + x k- x k-2... x h+ x h x h-... x y k- y k-2... y h+... variable constant s k- s k-2... s h+ x h x h-... x

52 Addition of a constant (2) x k- x k-2... x h+2 x h+ x h x h-... x c k HA/ MHA HA/ MHA.. HA/ MHA HA/ MHA... s k- s k s h+2 s h+ x h x h- x If y i = y i = Half-adder (HA) Modified half-adder (MHA)

53 Modified half-adder c s MHA x y 2 x + y + = ( c s ) 2 x y c s

54 Incrementer x k- x k-2... x 2 x x c k HA HA.. HA HA Decrementer s k- s k-2... s 2 s x x k- x k-2... x 2 x x c k MHA MHA.. MHA MHA s k- s k-2... s 2 s x

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57 Bit-Serial & Digit-Serial Adders

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59 x i y i c i+ Bit-serial adder c start clk s i

60 x i y i d d c i+ Digit-serial adder c start clk d s i

61 Asynchronous Adders

62 Possible solutions to the carry propagate problem. Detect the end of propagation rather than wait for the worst-case time 2. Speed-up propagation via look-ahead carry skip carry select, etc 3. Limit carry propagation to within a small number of bits 4. Eliminate carry propagation through the redundant number representation

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64 Analysis of carry propagation Probability of carry generation = (x i y i = ) 4 Probability of carry propagation = (x i y i = or ) 2 Probability of carry anihilation = (x i y i = or ) 2 j j i+ i or or Probability of carry propagating from position i to position j = 2 j i probability of propagation 2 = probability of anihilation 2 j i

65 Expected length of the carry chain that starts at position i () Expected length(i, k) = j k = i ( j + i) 2 j i + ( k i) 2 k i Length of the carry chain Probability of the given length Distance till the end of adder Probability of propagation till the end of adder

66 Expected length of the carry chain that starts at position i (2) Expected length(i, k) = 2 2 ( k i ) For i << k Expected length of the carry propagation is 2