MASSEY UNIVERSITY PALMERSTON NORTH CAMPUS

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1 MASSEY UNIVERSITY PALMERSTON NORTH CAMPUS EXAMINATION FOR COMPUTER SYSTEMS Semester One June 2008 Time allowed: THREE (3) hours This exam contains THREE (3) questions ANSWER ALL THREE (3) QUESTIONS THIS IS A CLOSED BOOK EXAMINATION CALCULATORS ARE NOT PERMITTED Page 1 of 11

2 1. (a) In the context of assembler programming on the 8051 family of processors, give a short description or explanation detailing (i) the effect of EQU and ORG (ii) the difference and # (iii) what effect the LCALL and RET instructions have on the stack (iv) what advantage there is in restricting the use of indirect addressing to r0 and r1 instead of any of the eight registers r0-r7 (v) how multiplication and division can sometimes be implemented without using the MUL or DIV instructions (vi) why, if a byte is stored to the SBUF register and then SBUF is immediately read, the value returned will almost certainly be different from that stored (vii) how, in assembler, parameters are passed to subroutines and results returned (viii) what memory-mapped means, giving examples and a explanation of why it is used (ix) how you could implement a greater-than or equal-to comparison for unsigned eight bit numbers (x) why a UART adds start and stop bits when sending and receiving data asynchronously [20 marks] (b) For numbers larger than eight bits, multiple bytes must be used to store each number. Write a subroutine in 8051 assembler to perform multi-byte subtraction. The format of the numbers is a little unusual in that the data stored includes not just the usual 16, 24, bits encoding the numeric value but also an extra byte indicating the number of bytes doing the encoding. Multi-byte numbers are stored in successive bytes with the byte-count at the lowest memory address followed by the numerically significant bytes, least significant byte first. e.g. the 32 bit (4 byte) number $E1DCA6B7 is stored as 04,$B7,$A6,$DC,$E1 and the 16 bit (2 byte) number $AB7F is stored as $02,$7F,$AB On entry to the subroutine: r0 contains the address of (the byte-count of) N1- the first number r1 contains the address of (the byte-count of) N2 - second number r2 contains the address at which the result is to be stored. If the numbers pointed at by r0 and r1 contain differing numbers of bytes, the subroutine should return immediately with the carry bit set, otherwise it should perform the subtraction and return with the carry bit clear, ensuring that the result is stored in the same format as the original numbers. [7 marks] Question 1 continued over Page 2 of 11

3 Question 1 continued (c) (d) Write three short fragments of assembler code each showing a different way of implementing looping that will cause a subroutine called beep to be called five times. [3 marks] Describe what interrupts are and why they might be desirable. Include in your discussion: a description of the steps that are necessary to set up a device to work under interrupt a description of what happens when an interrupt occurs and a list of the precautions that are needed when writing interrupt handlers that are not required for ordinary subroutines. [4 marks] 2. (a) Define the term Instruction Set Architecture, explain where it fits in the levels of abstraction that are used to describe computer architectures, and explain why it is a useful concept. (b) (c) (d) Draw a diagram of a cross-section of a CMOS transistor and explain how it works. Draw up a table of characteristics of the CISC and RISC architectures and explain why RISC processor architectures have largely replaced CISC processor architectures. Draw a diagram showing two different field layouts that are used in the instruction word for a MIPS processor. For each layout, explain what the information in each of the fields is used for. Page 3 of 11

4 3. (a) Why does the MIPS processor add 4 to the contents of the PC when preparing to access the next instruction in memory? [2 marks] (b) (c) (d) (e) Assuming the following register allocations: $19 i (a variable) $20 j (a variable) $21 k (a variable) $10 4 (a constant) rewrite the following MIPS assembly language code in a high level language such as C. loop: mult $9, $19, $10 # convert index to bytes lw $8, start($9) # start is base of this array bne $8, $21, exit add $19, $19, $20 j loop exit: What is meant by the term bit-slice architecture? Draw a block diagram of a bit-slice ALU that is capable of logical AND and OR operations, addition and subtraction and equality detection on 32 bit numbers. You do not have to draw all the components, but you must draw enough for the general structure to be clear. Draw a diagram that shows how the jump destination is loaded into the PC in the single-cycle version of the MIPS processor, including an explanation of why the various fields have the sizes that they do. Explain what is illustrated by each of the three sections, A, B, and C of the diagram below, and explain what is happening in each of the three sections 1, 2, and 3 enclosed in round-cornered boxes in section C. instr reg ALU data reg instr A instr fetch reg ALU data B C Page 4 of 11

5 8051 Architecture Reference Program Memory (Code) Address 07FFFH (8051) Internal Memory (Data) Special Function Registers* 07FFH (89C2051) 7FH I/O registers accessed via memory locations Serial Port Timer 1 Ext Interrupt 1 Timer 0 Ext Interrupt 0 Reset 0023H 001BH 0013H 000BH 0003H 0000H Interrupt Vectors (location jumped to on Interrupt) Bank Select Bits in PSW 11 { 10 { 01 { 00 { Directly Addressable Bits 0-7F RB3* RB2* RB1* RB0* * Four banks of Registers addressable as R0-R7 2FH 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Reset value of Stack Pointer Program Counter: 16 bit register restricted to 0000H -> 07FFFH Special Function Registers (SFR) Space: Byte address Name Description Bits ("-" NOT bit addressable) 80H P0 Port 0 bit addressable: P0.7 -> P0.0 81H SP Stack Pointer - 82H DPL Low byte of DPTR - 83H DPH High byte of DPTR - 87H PCON Power control - 88H TCON Timer control TF1-TR1-TF0-TR0-IE1-IT1-IE0-IT0 89H TMOD Timer mode control - 8AH TL0 Timer 0 low byte - 8BH TL1 Timer 1 low byte - 8CH TH0 Timer 0 high byte - 8DH TH1 Timer 1 high byte - 90H P1 Parallel port 1 Bit Addressable P1.7 -> P1.0 98H SCON Serial control SM0-SM1-SM2-REN-TB8-RB8-TI -RI 99H SBUF Serial buffer - A0H P2 Port 2 Bit addressable: P2.7-P2.0 A8H IE Interrupt Enable EA - - -ES -ET1-EX1-ET0-EX0 B0H P3 Parallel port 3 Bit addressable: P3.7 -> P3.0 B8H IP Interrupt priority - - -PS -PT1-PX1-PT0-PX0 D0H PSW Program Status Word CY -AC -F0 -RS1-RS0-OV -F1 -P E0H ACC Accumulator ACC.7 -> ACC.0 F0H B B register B.7 -> B.0 Page 5 of 11

6 Interrupt control register IE: EA Global bit to enable interrupts ES,ETx Serial interrupt (either RI or TI), Clock interrupt on overflow Timer control and mode registers - 2 timers 0 and 1 TCON: TF0/TF1 Timer overflow flag timers 0/1 TR0/TR1 Timer run control bit. Set by software to switch timer ON TMOD: mode0-mode1 2 4-bit nibbles. Timer 1 high order nibble, Timer 0 low order. mode = 0 13 bit timer mode = 1 16 bit timer mode = 2 8 bit auto-reload timer. THx -> TLx on overflow. Used by Serial I/O as bit rate (*32). 0FDH in Thx gives 9600bps for Mhz clock Serial control register SCON: SM0-SM1-SM2-REN should be set to 0111 for normal operation TI set when the character has been transmitted RI set when a character is received Power control register PCON: set to 2 will stop the processor Addressing Modes: Rn Register R0 - R7 of the currently selected register bank. direct 8-bit internal data location's address. This could be an internal Data RAM location (0-127) or a 8-bit internal Data RAM location addressed indirectly via register R0 or R1 #data 8-bit constant included in instruction. #data16 16-bit constant included in instruction. addr11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K byte page of Program Memory as the first byte of the following instruction. addr16 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 2K byte Program Memory address space. rel Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the next instruction. bit Direct addressed bit in internal Data RAM or SFR. Page 6 of 11

7 Arithmetic operations: Byte Cycle C OV AC ADD A,Rn Add register to Accumulator 1 1 X X X ADD A,direct Add direct byte to Accumulator 2 1 X X X ADD A,@Ri Add indirect RAM to Accumulator 1 1 X X X ADD A,#data Add immediate data to Accumulator 2 1 X X X ADDC A,Rn Add register to Acc. with Carry 1 1 X X X ADDC A,direct Add direct byte to Acc. with Carry 2 1 X X X ADDC A,@Ri Add indirect RAM to Acc. with Carry 1 1 X X X ADDC A,#data Add immediate data to Acc. / Carry 2 1 X X X SUBB A,Rn Subtract reg. from Acc. with borrow 1 1 X X X SUBB A,direct Sub. direct byte from Acc. / borrow 2 1 X X X SUBB A,@Ri Sub. indirect RAM from Acc./ borrow 1 1 X X X SUBB A,#data Sub. imm. data from Acc. / borrow 2 1 X X X INC A Increment Accumulator 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 1 Increment indirect RAM 1 1 DEC A Decrement Accumulator 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 1 Decrement indirect RAM 1 1 INC DPTR Increment Data Pointer 1 2 MUL AB Multiply A and B X DIV AB Divide A by B X DA A Decimal adjust Accumulator 1 1 X Page 7 of 11

8 Logical operations: Byte Cycle C OV AC ANL A,Rn AND register to Accumulator 1 1 ANL A,direct AND direct byte to Accumulator 2 1 ANL A,@Ri AND indirect RAM to Accumulator 1 1 ANL A,#data AND immediate data to Accumulator 2 1 ANL direct,a AND Accumulator to direct byte 2 1 ANL direct,#data AND immediate data to direct byte 3 2 ORL A,Rn OR register to Accumulator 1 1 ORL A,direct OR direct byte to Accumulator 2 1 ORL A,@Ri OR indirect RAM to Accumulator 1 1 ORL A,#data OR immediate data to Accumulator 2 1 ORL direct,a OR Accumulator to direct byte 2 1 ORL direct,#data OR immediate data to direct byte 3 2 XRL A,Rn Exc-OR register to Accumulator 1 1 XRL A,direct Exc-OR direct byte to Accumulator 2 2 XRL A,@Ri Exc-OR indirect RAM to Accumulator 1 1 XRL A,#data Exc-OR immediate data to Acc. 2 1 XRL direct,a Exc-OR Accumulator to direct byte 2 1 XRL direct,#data Exc-OR imm. data to direct byte 3 2 CLR A Clear Accumulator 1 1 CPL A Complement Accumulator 1 1 RL A Rotate Accumulator left 1 1 RLC A Rotate Acc. left through Carry 1 1 X RR A Rotate Accumulator right 1 1 RRC A Rotate Acc. right through Carry 1 1 X SWAP A Swap nibbles within the Accumulator 1 1 Page 8 of 11

9 Data transfer: Byte MOV A,Rn Move register to Accumulator 1 1 MOV A,direct Move direct byte to Accumulator 2 1 MOV A,@Ri Move indirect RAM to Accumulator 1 1 MOV A,#data Move immediate data to Accumulator 2 1 MOV Rn,A Move Accumulator to register 1 1 MOV Rn,direct Move direct byte to register 2 2 MOV Rn,#data Move immediate data to register 2 1 MOV direct,a Move Accumulator to direct byte 2 1 MOV direct,rn Move register to direct byte 2 2 MOV direct,direct Move direct byte to direct byte 3 2 MOV direct,@ri Move indirect RAM to direct byte 2 2 MOV direct,#data Move immediate data to direct byte 3 2 Move Accumulator to indirect RAM 1 1 Move direct byte to indirect RAM 2 2 Move immediate data to indirect RAM 2 1 MOV DPTR,#data16 Load Data Pointer with 16-bit const 3 2 MOVC A,@A+DPTR Move Code byte rel. to DPTR to Acc. 1 2 MOVC A,@A+PC Move Code byte rel. to PC to Acc. 1 2 PUSH direct Push direct byte onto stack 2 2 POP direct Pop direct byte from stack 2 2 XCH A,Rn Exchange register with Accumulator 1 1 XCH A,direct Exchange direct byte with Acc. 2 1 XCH A,@Ri Exchange indirect RAM with Acc. 1 1 XCHD A,@Ri Exchange low order digit indirect RAM with Accumulator 1 1 Cycle C OV AC Number and String Formats: Numbers : Decimal - 34 Binary B Hexadecimal - a leading $ or a trailing h or H. e.g. $7F, 7Fh, 0FFH, $FF 0A8H Note: if not preceded by $ hex constants must start with 0-9. eg 0C7h Characters: 'A' - 'Abc' - A,00DH,00AH (mixed mode), "T" Strings : Only with DB directive for putting strings into CODE memory 'abc' or "abc" Operators : () + - / * MOD SHR SHL NOT AND OR XOR Page 9 of 11

10 Boolean variable manipulation: Byte Cycle C OV AC CLR C Clear Carry CLR bit Clear direct bit 2 1 SETB C Set Carry SETB bit Set direct bit 2 1 CPL C Complement Carry 1 1 X CPL bit Complement direct bit 2 1 ANL C,bit AND direct bit to Carry 2 2 X ANL C,/bit AND complement of dir. bit to Carry 2 2 X ORL C,bit OR direct bit to Carry 2 2 X ORL C,/bit OR complement of dir. bit to Carry 2 2 X MOV C,bit Move direct bit to Carry 2 1 X MOV bit,c Move Carry to direct bit 2 2 JC rel Jump if Carry is set 2 2 JNC rel Jump if Carry not set 2 2 JB bit,rel Jump if direct bit is set 3 2 JNB bit,rel Jump if direct bit is not set 3 2 JBC bit,rel Jump if dir. bit is set & clear bit 3 2 Program Branching: ACALL addr11 Absolute subroutine call 2 2 Byte Cycle C OV AC LCALL addr16 Long subroutine call 3 2 RET Return from subroutine 1 2 RETI Return from interrupt 1 2 AJMP addr11 Absolute jump 2 2 LJMP addr16 Long jump 3 2 SJMP rel Short jump (relative address) 2 2 Jump indirect relative to the DPTR 1 2 JZ rel Jump if Accumulator is zero 2 2 JNZ rel Jump if Accumulator is not zero 2 2 CJNE A,direct,rel Compare direct byte to Accumulator 3 2 X and jump if not equal CJNE A,#data,rel Compare immediate data to 3 2 X Accumulator and jump if not equal CJNE Rn,#data,rel Compare immediate data to register and jump if not equal 3 2 X Compare immediate data to indirect RAM and jump if not equal 3 2 X DJNZ Rn,rel Decr. register and jump if not zero 2 2 DJNZ direct,rel Decrement direct byte and jump if 3 2 not zero NOP No operation 1 1 Page 10 of 11

11 Assembler Directives and Controls ; Everything after a semicolon (;) on the same line is a comment Label: Must start in column 1 Defines a new Label - colon is optional. Controlling Memory Spaces and Code location ORG 56H Specify a value for the current segment's location counter. USE IRAM Makes the data space the currently selected segment USE ROM Makes the code space the currently selected segment Defining Byte and Bit values TEN EQU 10 EQUates 10 to symbol TEN, like #define in C, CONST in Delphi ON_FLAG BIT 6 Assigns BIT 6 (in data or SFR space) to the symbol ON_FLAG Allocating Memory SP_BUFFER: RMB 6 Reserves Memory Byte reserves 6 bytes of storage in current memory space (affected by most recent USE IRAM/ROM). Message: DB 'Hi' Define Byte(s): Store byte constants in code space. The following are all equivalent the string hello followed by a newline and a null. newline EQU 13 DB "H","E","L","L","O",13,0 DB "Hello",13,0 DB "Hello",newline,0 Page 11 of 11

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