Presented By : Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak


 Edmund Lamb
 4 years ago
 Views:
Transcription
1 Presented By : Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak
2 Content  Introduction 2 Feature 3 Feature of BJT 4 TTL 5 MOS 6 CMOS 7 K Map
3  Introduction Logic IC ASIC: Application Specific Integrated Circuits
4  Introduction IC digital logic families 炷Resistortransistor logic炸 DTL 炷Diodetransistor logic炸 TTL 炷Transistor transistor logic炸 ECL 炷Emittercoupled logic炸 MOS 炷Metaloxide semiconductor炸 CMOS 炷Complementary Metaloxide semiconductor炸 RTL
5 Positve logic and Negative logic Positive logic: H is set to be binary Negative logic: L is set to be binary
6 2 Feature The feature to be concerned of IC logic families: fanout The no. of standard loads can be connected to the output of the gate without degrading its normal operation Sometimes the term loading is used Power dissipation The power needed by the gate Expressed in mw Propagation delay The average transitiondelay time for the signal to propagate from input to output when the binary signal changes in value Noise margin The unwanted signals are referred to as noise Noise margin is the maximum noise added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output
7 Computing fanout I OH I OL Fan out min(, ) I IH I IL
8 Power dissipation I CCH I CCL I CC (avg) 2 PD (avg) I CC (avg) VCC For standard TTL I CCH ma, I CCL 3mA PD (avg)? Total PD (avg) in IC 74?
9 Propagation delay 5% VH 5% VH 5% VH For standard TTL t PHL 7ns, t PLH ns t P (avg)? 5% VH
10 Noise margin
11 Noise margin Highstate noise margin=.4 Lowstate noise margin=.4
12 3 Feature of BJT BJT npn or pnp Si or Ge Si is used mainly npn is most popular
13 Table  Typical npn Transistor Parameters Region VBE (V) VCE (V) Current Relation Cutoff <.6 Open circuit IB=IC= Active.6.7 >.8 IC =hfeib Saturation IB IC/hFE
14 Diode symbol and characteristic
15 5 TransistorTransistor Logic (TTL) The original basic TTL gate was a slight improvement over the DTL gate. There are several TTL subfamilies or series of the TTL technology. Eight TTL series appear in Table 2. Has a number start with 74 and follows with a suffix that identifies the series type, e.g 744, 74S86, 74ALS6. Three different types of output configurations:. opencollector output 2. Totempole output 3. Threestate (or tristate) output
16 Opencollector TTL Gate
17 WiredAND of Two OpenCollector
18 OpenCollector Gates Forming a Common Bus Line In this case Y=?
19 TTL Gate with TotemPole Output
20 Schottky TTL Gate
21 Threestate TTL Gate
22 Objectives Karnaugh Maps (KMaps) Learn to minimize a function using KMaps 2Variables 3Variables 4Variables Don t care conditions Important Definitions 5Variables KMaps
23 Simplification using Algebra F = X YZ + X YZ + XZ = X Y(Z+Z ) + XZ (id 4) = X Y. + XZ (id 7) = X Y + XZ (id 2) Simplification may mean different things here it means less number of literals
24 Simplification Revisited Algebraic methods for minimization is limited: No formal steps (id first, then id 4, etc?), need experience. No guarantee that a minimum is reached Easy to make mistakes Karnaugh maps (kmaps) is an alternative convenient way for minimization: A graphical technique Introduced by Maurice Karnaugh in 953 Kmaps for up to 4 variables are straightforward to build Building higher order Kmaps (5 or 6 variable) are a bit more cumbersome Simplified expression produced by Kmaps are in SOP or POS forms
25 Truth Table Adjacencies A B F A B F These minterms are adjacent in a gray code sense they differ by only one bit. We can apply XY+XY =X F = A B + A B = A (B +B) = A () = A Same idea: F = A B + AB = B Keep common literal only!
26 KMap A B F A different way to draw a truth table! Take advantage of adjacency B B A F = A B + AB = B A Keep common literal only! A B A B A B AB
27 Minimization with Kmaps Draw a Kmap 2. Combine maximum number of s following rules: Only adjacent squares can be combined All s must be covered Covering rectangles must be of size,,,, Check if all covering are really needed 4. Read off the SOP expression 3. n
28 2variable Kmap Given a function with 2 variables: F(X,Y), the total number of minterms are equal to 4: m, m, m2, m3 The size of the kmap is always equal to the total number of minterms. Each entry of the kmap corresponds to one minterm for the function: Row represents: X Y, X Y Row represents: XY, XY XY 2 3
29 Example Q. Simplify the function F X,Y = m,, Sol. This function has 2 variables, and three squares (three minterms where function is ) F = m + m2 + m3 XY Y is the common literal Note: The squares can be combined more than once in the adjacent squares X is the common literal Minimized expression: F = X + Y
30 2 variable KMaps (Adjacency) In an nvariable kmap, each square is adjacent to exactly n other squares Q: What if you have in all squares?
31 3variable Kmaps For 3variable functions, the kmaps are larger and look different. Total number of minterms that need to be accommodated in the kmap = 8 To maintain adjacency neighbors don t have more than different bit B AC m A m4 B m m3 m5 m7 C m2 m6
32 3variable Kmaps Note: You can only combine a power of 2 adjacent squares. For e.g. 2, 4, 8, 6 squares. You cannot combine 3, 7 or 5 squares Minterms mo, m2, m4, m6 can be combined as m and m2 are adjacent to each other, m4 and m6 are adjacent to each other mo and m4 are also adjacent to each other, m2 and m6 are also adjacent to each other
33 Example Simplify F = m,,,, using Kmap B BC A 3 4 A C
34 Example 2 Simplify F = m,,,, using Kmap B BC A F = A B + C 3 4 A C
35 3 variable KMaps (Adjacency) A 3variable map has 2 possible groups of 2 minterms They become product terms with 2 literals
36 3 variable KMaps (Adjacency) A 3variable map has 6 possible groups of 4 minterms They become product terms with literals
37 4variable Kmaps A 4variable function will consist of 6 minterms and therefore a size 6 kmap is needed Each square is adjacent to 4 other squares A square by itself will represent a minterm with 4 literals Combining 2 squares will generate a 3literal output Combining 4 squares will generate a 2literal output Combining 8 squares will generate a literal output
38 Example F(A,B,C,D) = Sm(,,2,5,8,9,) Solution: F = B D + B C + A C D CD AB C= B= A= D=
39 Example (POS) F(A,B,C,D) = Sm(,,2,5,8,9,) Write F in the simplified product of sums (POS) Two methods? You already know one! CD AB C= B= A= D=
40 Example (POS) F(A,B,C,D) = Sm(,,2,5,8,9,) Write F in the simplified product of sums (POS) Method 2: Follow same rule as before but for the ZEROs CD AB F = AB + CD + BD Therefore, F = F = A +B C +D B +D C= B= A= D=
41 Don t Cares In some cases, the output of the function ( or ) is not specified for certain input combinations either because The input combination never occurs (Example BCD codes), or We don t care about the output of this particular combination Such functions are called incompletely specified functions Unspecified minterms for these functions are called don t cares While minimizing a kmap with don t care minterms, their values can be selected to be either or depending on what is needed for achieving a minimized output.
42 Example F = m,, + d, B BC Circle the x s that help get bigger groups of s (or s if POS). A Don t circle the x s that don t help. X 4 A X C
43 Example F = m,, + d, B BC Circle the x s that help get bigger groups of s (or s if POS). A Don t circle the x s that don t help. X 4 A F=C X C
44 Example 2 F A, B, C, D = m,,,, + d,, Two possible solutions! Both acceptable. All s covered Src: Mano s Textbook
45 Definitions An implicant is a product term of a function Any group of s in a KMap A prime implicant is a product term obtained by combining the maximum possible number of adjacent s in a kmap Biggest groups of s Not all prime implicants are needed! If a minterm is covered by exactly one prime implicant then this prime implicant is called an essential prime implicant
46 Finding minimum SOP Find each essential prime implicant and include it in the solution 2. If any minterms are not yet covered, find minimum number of prime implicants to cover them (minimize overlap)..
47 Example 2 Simplify F A, B, C, D = m,, 2, 4, 5,,,3, 5) Note: Only A C is E.P.I For the remaining minterms: Choose and 2 (minimize overlap) For m2, choose either A B D or B CD F = A C + ABD + AB C + A B D Src: Mano s Textbook
48 5variable Kmaps 32 minterms require 32 squares in the kmap Minterms 5 belong to the squares with variable A=, and minterms 632 belong to the squares with variable A= Each square in A is also adjacent to a square in A (one is above the other) Minterm 4 is adjacent to 2, and minterm 5 is to 3
ELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More information2.1 Binary Logic and Gates
1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More informationDigital Fundamentals. Integrated Circuit Technologies
Digital Fundamentals Integrated Circuit Technologies 1 Objectives Determine the noise margin of a device from data sheet parameters Calculate the power dissipation of a device Explain how propagation delay
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationA B AB CD Objectives:
Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3
More informationDigital Logic Lecture 7 Gate Level Minimization
Digital Logic Lecture 7 Gate Level Minimization By Ghada AlMashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. Kmap principles. Simplification using Kmaps. Don tcare
More informationChapter 3. GateLevel Minimization. Outlines
Chapter 3 GateLevel Minimization Introduction The Map Method FourVariable Map FiveVariable Map Outlines Product of Sums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel
More informationChapter 2 Combinational
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationECE380 Digital Logic
ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8 Terminology For
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 2 Intro to Electrical and Computer Engineering Lecture 8 Minimization with Karnaugh Maps Overview Kmaps: an alternate approach to representing oolean functions Kmap representation can be used to
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is  Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationGate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
More informationCMPE223/CMSE222 Digital Logic
CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Terminology For a given term, each
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Minimization CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
More informationSpecifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 20062007) NOTES 5  page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More informationBoolean Algebra and Logic Gates
Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can
More informationBoolean Algebra. BME208 Logic Circuits Yalçın İŞLER
Boolean Algebra BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com 5 Boolean Algebra /2 A set of elements B There exist at least two elements x, y B s. t. x y Binary operators: +
More informationCombinational Logic Circuits
Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical
More informationGateLevel Minimization
MEC520 디지털공학 GateLevel Minimization JeeHwan Ryu School of Mechanical Engineering GateLevel MinimizationThe Map Method Truth table is unique Many different algebraic expression Boolean expressions may
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed ElSaied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationCONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)
CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows
More informationCombinational Logic Circuits Part III Theoretical Foundations
Combinational Logic Circuits Part III Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationGateLevel Minimization. BME208 Logic Circuits Yalçın İŞLER
GateLevel Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to
More informationLecture (05) Boolean Algebra and Logic Gates
Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either
More informationSlide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide
More informationKarnaugh Map (KMap) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using Kmap
Karnaugh Map (KMap) Ch. 2.4 Ch. 2.5 Simplification using Kmap A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or
More informationGraduate Institute of Electronics Engineering, NTU. CH5 Karnaugh Maps. Lecturer: 吳安宇教授 Date:2006/10/20 ACCESS IC LAB
CH5 Karnaugh Maps Lecturer: 吳安宇教授 Date:2006/0/20 CCESS IC L Problems in lgebraic Simplification The procedures are difficult to apply in a systematic way. It is difficult to tell when you have arrived
More informationCombinational Logic Circuits
Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 21 Binary Logic and Gates 22 Boolean Algebra 23 Standard Forms 24 TwoLevel Circuit Optimization
More informationDr. S. Shirani COE2DI4 Midterm Test #1 Oct. 14, 2010
Dr. S. Shirani COE2DI4 Midterm Test #1 Oct. 14, 2010 Instructions: This examination paper includes 9 pages and 20 multiplechoice questions starting on page 3. You are responsible for ensuring that your
More informationChapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More informationDIGITAL ELECTRONICS. Vayu Education of India
DIGITAL ELECTRONICS ARUN RANA Assistant Professor Department of Electronics & Communication Engineering Doon Valley Institute of Engineering & Technology Karnal, Haryana (An ISO 9001:2008 ) Vayu Education
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show
More informationDKT 122/3 DIGITAL SYSTEM 1
Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits
More informationComputer Organization
Computer Organization (Logic circuits design and minimization) KR Chowdhary Professor & Head Email: kr.chowdhary@gmail.com webpage: krchowdhary.com Department of Computer Science and Engineering MBM Engineering
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationDigital Logic Design. Outline
Digital Logic Design GateLevel Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR
More informationChapter 2. Boolean Algebra and Logic Gates
Chapter 2. Boolean Algebra and Logic Gates Tong In Oh 1 Basic Definitions 2 3 2.3 Axiomatic Definition of Boolean Algebra Boolean algebra: Algebraic structure defined by a set of elements, B, together
More informationUNIT II. Circuit minimization
UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.
More informationCopyright 2000 N. AYDIN. All rights reserved. 1
Electronic Circuits Prof. Nizamettin AYDIN naydin@yildiz.edu.tr http://www.yildiz.edu.tr/~naydin Dr. Gökhan Bilgin gokhanb@ce.yildiz.edu.tr Digital devices Introduction Gate characteristics Logic families
More informationCHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey
CHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input
More informationChapter 3 Simplification of Boolean functions
3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean
More informationSHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI
SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL
More informationReview: Standard forms of expressions
Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can be combined to form complex expressions, which can
More informationCD4023BC Buffered Triple 3Input NAND Gate
CD4023BC Buffered Triple 3Input NAND Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N and P channel enhancement mode transistors.
More informationSwitching Circuits & Logic Design
Switching Circuits & Logic Design JieHong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 23 5 Karnaugh Maps Kmap Walks and Gray Codes http://asicdigitaldesign.wordpress.com/28/9/26/kmapswalksandgraycodes/
More informationLiteral Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10
Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm
More information數位系統 Digital Systems 朝陽科技大學資工系. Speaker: FuwYi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷
數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: FuwYi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象,
More information3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0
1. The number of level in a digital signal is: a) one b) two c) four d) ten 2. A pure sine wave is : a) a digital signal b) analog signal c) can be digital or analog signal d) neither digital nor analog
More informationCombinational Circuits Digital Logic (Materials taken primarily from:
Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a
More informationR.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai
L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT  I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean
More informationENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.
Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to
More informationChap2 Boolean Algebra
Chap2 Boolean Algebra Contents: My name Outline: My position, contact Basic information theorem and postulate of Boolean Algebra. or project description Boolean Algebra. Canonical and Standard form. Digital
More informationGate Level Minimization
Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =
More informationChapter 6. Logic Design Optimization Chapter 6
Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Twolevel Optimization Manipulating a function until it is
More informationGet Free notes at ModuleI One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More informationENEL 353: Digital Circuits Midterm Examination
NAME: SECTION: L01: Norm Bartley, ST 143 L02: Steve Norman, ST 145 When you start the test, please repeat your name and section, and add your U of C ID number at the bottom of the last page. Instructions:
More informationGateLevel Minimization
GateLevel Minimization Mano & Ciletti Chapter 3 By Suleyman TOSUN Ankara University Outline Intro to GateLevel Minimization The Map Method 2345 variable map methods ProductofSums Method Don t care
More informationIncompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples
Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples Incompletely specified functions
More informationS1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017
S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017 Karnaugh Map Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and
More informationDate Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 04. Boolean Expression Simplification and Implementation
Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 04 Boolean Expression Simplification and Implementation OBJECTIVES: To understand the utilization
More informationLSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a
More informationStandard Forms of Expression. Minterms and Maxterms
Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 20152016 (ODD
More informationModule 7. Karnaugh Maps
1 Module 7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or SumofMinterms (SOM) 2.4 Canonical product of sum or ProductofMaxterms(POM)
More informationX Y Z F=X+Y+Z
This circuit is used to obtain the compliment of a value. If X = 0, then X = 1. The truth table for NOT gate is : X X 0 1 1 0 2. OR gate : The OR gate has two or more input signals but only one output
More information4 KARNAUGH MAP MINIMIZATION
4 KARNAUGH MAP MINIMIZATION A Karnaugh map provides a systematic method for simplifying Boolean expressions and, if properly used, will produce the simplest SOP or POS expression possible, known as the
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationNADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni625531 Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering
More informationOutcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps
.. Outcomes Unit I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate size and contents of a memory to implement any logic function (i.e. truth
More informationAssignment (36) Boolean Algebra and Logic Simplification  General Questions
Assignment (36) Boolean Algebra and Logic Simplification  General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationIT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationBOOLEAN ALGEBRA. Logic circuit: 1. From logic circuit to Boolean expression. Derive the Boolean expression for the following circuits.
COURSE / CODE DIGITAL SYSTEMS FUNDAMENTAL (ECE 421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE 422) BOOLEAN ALGEBRA Boolean Logic Boolean logic is a complete system for logical operations. It is used in countless
More informationPoints Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map
Points Addressed in this Lecture Lecture 4: Logic Simplication & Karnaugh Map Professor Peter Cheung Department of EEE, Imperial College London Standard form of Boolean Expressions SumofProducts (SOP),
More informationCombinational Logic & Circuits
WeekI Combinational Logic & Circuits Spring' 232  Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other
More informationDigital Techniques. Lecture 1. 1 st Class
Digital Techniques Lecture 1 1 st Class Digital Techniques Digital Computer and Digital System: Digital computer is a part of digital system, it based on binary system. A block diagram of digital computer
More informationGateLevel Minimization. section instructor: Ufuk Çelikcan
GateLevel Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to
More information74VHC132 Quad 2Input NAND Schmitt Trigger
74VHC132 Quad 2Input NAND Schmitt Trigger General Description The VHC132 is an advanced high speed CMOS 2input NAND Schmitt Trigger Gate fabricated with silicon gate CMOS technology. It achieves the
More information74VHC14 Hex Schmitt Inverter
74VHC14 Hex Schmitt Inverter General Description June 1993 Revised April 1999 The VHC14 is an advanced high speed CMOS Hex Schmitt Inverter fabricated with silicon gate CMOS technology. It achieves the
More information2.6 BOOLEAN FUNCTIONS
2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
More informationChapter 3. Boolean Algebra and Digital Logic
Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL
More informationDIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (KMAPS)
DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (KMAPS) 1 Learning Objectives 1. Given a function (completely or incompletely specified) of three to five variables, plot it on a Karnaugh map. The function
More informationCSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map
CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,
More informationPrinciples of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.
Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)
More informationTo write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map.
3.1 Objectives To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using. 3.2 Sum of Products & Product of Sums Any Boolean expression can be simplified
More informationMUX using TriState Buffers. Chapter 2  Part 2 1
MUX using TriState Buffers Chapter 2  Part 2 Systematic Simplification A Prime Implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map into a rectangle
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of
More informationSynthesis of combinational logic
Page 1 of 14 Synthesis of combinational logic indicates problems that have been selected for discussion in section, time permitting. Problem 1. A certain function F has the following truth table: A B C
More information2008 The McGrawHill Companies, Inc. All rights reserved.
28 The McGrawHill Companies, Inc. All rights reserved. 28 The McGrawHill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationDigital Design. Chapter 4. Principles Of. Simplification of Boolean Functions
Principles Of Digital Design Chapter 4 Simplification of Boolean Functions Karnaugh Maps Don t Care Conditions Technology Mapping Optimization, Conversions, Decomposing, Retiming Boolean Cubes for n =,
More informationBoolean Analysis of Logic Circuits
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem  IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 7 Lecture Title:
More informationCD4010C Hex Buffers (NonInverting)
Hex Buffers (NonInverting) General Description The CD4010C hex buffers are monolithic complementary MOS (CMOS) integrated circuits. The N and Pchannel enhancement mode transistors provide a symmetrical
More informationSwitching Theory And Logic Design UNITII GATE LEVEL MINIMIZATION
Switching Theory And Logic Design UNITII GATE LEVEL MINIMIZATION Twovariable kmap: A twovariable kmap can have 2 2 =4 possible combinations of the input variables A and B. Each of these combinations,
More information