Darshan Institute of Engineering & Technology for Diploma Studies Unit - 1

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1 Darshan Institute of Engineering & Technology for Diploma Studies Unit Draw and explain 4 bit binary arithmetic or adder circuit diagram. A binary parallel adder is digital function that produces the arithmetic sum of two binary numbers in parallel. It consists of full-adders connected in cascade, with output carry from one full-adder connected to input carry of the next full adder. Following figure shows the interconnections of four full adders to provide a four bit adder. Here the augends bits of A and the addend bits of B are designated by subscript numbers from right to the left with subscript 1 denoting the low order bit. The carries are connected in a chain through the full adder. The S outputs of the full adder generate the required sum bits. Below figure is for n- bit binary adder. The micro operation can be written in RTL as P: A <- A + B where a & B are two registers. 2. Explain register bus system data transfer. 1

2 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 1 A bus system is formed with multiplexer circuits. Above figure shows how the four registers are connected through multiplexer to form one set of common BUS. Each register has four bits. Each 4 by 1 multiplexer has four data input lines, two select lines, and one output line. First cell in each register is connected to one of the leftmost multiplexer, second cell to the second multiplexer and so on. The select lines are connected in parallel to input select variables S0 and S1. With S1S0=00, first multiplexer line selected and applied to the outputs that form the bus. The bus line receives data register A since register is connected to first line of the multiplexers. Similarly the register B is selected if select line S1S0=01, register C is selected is S1S0=10 and so on. Truth Table for source register selection S0 S1 Register selected 0 0 A 0 1 B 1 0 C 1 1 D In general, a bus system will multiplex p registers of n bits each to produce an n-line common bus. The number of multiplexers required to construct the bus is equal to n, the number of bits in each register. The size of each multiplexer must be p * 1 since it multiplexes p data lines. The transfer of data from a bus into one of the many destination registers can be done by connecting the bus lines to the inputs of all registers and activating the control function of the particular destination register selected. As shown in figure above, the bus lines are connected to the inputs of all the registers. Activating the load of the particular register will transfer the information from bus into that register. Truth Table for destination register selection Z W Register 0 0 R0 0 1 R1 1 0 R2 1 1 R3 For eg: the select control variable z=0 & w=1 then the register R1 will select from the transfer from bus (E must be enabled). In RTL we can write statement: BUS A, R1 BUS The content of register A is placed inside BUS & the content of BUS is loaded into register R1. 3. Define Micro Operations & explain Arithmetic & Logic Micro Operations. Micro Operation: - Micro operations are elementary operations performed on data stored in registers or in memory. There are four types of micro operations that are described below: 1. Transfer micro operations: This is an operation where data is transferred from one register to another. Data may also be transferred from a register to memory or from memory to a register. 2. Arithmetic micro operations: This is an operation that performs arithmetic on data in one or two registers. 3. Logic micro operations: This operation performs bit manipulation on data in one or two registers. 4. Shift micro operations: This operation shifts data in a register. 2

3 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 1 Arithmetic Micro Operation: - The basic arithmetic micro operations are addition, subtraction, increment, decrement complement. The basic arithmetic micro operations are addition, subtraction, increment, decrement complement. P: R1 <- R2 + R3 is the arithmetic micro operation. It states that the content of register R2 are added to the content of R3 and sum transferred to register R1. In arithmetic operation some extra circuit is needed in addition to source and destination register and path between them. Summary of Arithmetic Micro-Operations is below: R3 <- R1 + R2 Content of R1 plus R2 transferred to R3 R3 <- R1 - R2 Content of R1 minus R2 transferred to R3 R2 <- R2 Complement the content of R2 R2 <- R s complement the contents of R2(negate) R3 <- R1 + R2 + 1 Subtraction R3 <- R1 + 1 Increment R3 <- R1 1 Decrement Arithmetic circuit: Following figure shows the 4-bit arithmetic circuit, which can perform seven basic operations by controlling the input to the FA (full adder). FA circuit is the basic building block of this circuit. 3

4 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 1 Operations between register A and B are performed and the result (at register D) is generated at output of FA. During the operations content of register B is selected in ac controlled way. 0 inputs of the MUXs are bits of B and 1 input of MUXs are complimented of B. MUX are also given logic 0 and logic 1 at logic 2 and 3 inputs. Select signals S0 and S1 will select any of these four inputs and seven arithmetic operations are performed, as shown in following table. Logic micro operation: Logic micro operations specify binary operations for string of bits stored in register. In these operations each bit of register not treat as a number but treat them as a logic (binary variable). Any logic operation is performed bit by bit. Example: the exclusive-or micro operation with content of two register A and B is written as: P: C A + B It specify a logic micro operation to executed on the individual bits of the register (A and B) provided that the control function P=1 Example for XOR operation: content of A content of B content of C after P=1 Example for AND logic operation: content of A content of B content of C after P=1 There are 16 different logic micro operations that can be performed with two binary variables. Each of the 16 columns F0 to F15 represents a truth table of one possible Boolean function for the two variable x and y. We can implement the hardware for the logic micro operations, requires that logic gates be inserted for each bit or pairs of bits in the registers to perform the required logic function. Most computers use only four (AND, OR, XOR, NOT) from which others can be derived. 4

5 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 1 List of 16 logic operation: 5

6 Darshan Institute of Engineering & Technology for Diploma Studies Unit Draw and explain flowchart for instruction cycle. In a stored programmed concept computer data, the instructions are stored in main memory. Instructions & Data (operand) are read from the memory one by one starting from the beginning to the end of program. Temporary and final results are stored in the memory. Control unit undergoes a cycle for executing one instruction. This is known as instruction cycle. Four phases of instruction cycle:- 1. Fetching (Reading) the instruction code from the memory. 2. Decoding the instruction. 3. Second memory access to read the true address of operand if the address mode is indirect. (This phase is optional, called indirect phase). 4. Executing the instruction. The micro operation for the fetch & decode phase of the operation can be specified by RTL as: T0: AR PC (S0S1S2 = 010, T0 = 1) T1: IR M [AR], PC PC + 1 (S0S1S2 = 111, T1 = 1) T2: D0, D7 Decode IR (12-14), AR IR (0-11), I IR (15) Timing signal T3 is activated after the decoding. During time T3, the control unit determines the type of instruction that was read from memory. There are three type of instruction in the basic computer. 5

7 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 2 Output D7 of decoder is equal to 1 if the operation code is 111, we determine that if D7 = 1, the instruction must be a register reference or I/O type. If D7 = 0, the operation code must be Memory Reference type. D 7IT3: AR M [AR], memory reference indirect addressing mode. D 7I T3: Nothing, memory reference direct addressing mode. D7I T3: Execute a register reference instruction. D7IT3: Execute an input-output reference instruction. If I = 0, instruction will be memory reference, then not necessary to do anything, the effective address is already in AR. The sequence counter SC must be incremented when D7 T3 = 1, so that the execution of memory reference can be continued with timing signal T4. A register reference or I/O reference instruction can be executed with clock timing signal T3. After that the sequence counter SC will clear to 0 and control returns to the next fetch phase with T0=1. 5. Draw and explain Control unit of basic computer. The block diagram below shows the control unit. Control unit has two decoders, a counter, and a number of control logic gates. An instruction read from memory is placed in the instruction register (IR). IR has three parts 1 bit for mode (15 bit), operation code (14-12 bit), and 0 to 11 positions for operation or address. The 8 outputs of decoder are D0 through D7, bit 15 of the instruction is transferred to flip-flop, symbol I. 0 to 11 bits applied to control logic gates. The outputs of four-bit counter are decoded into 16 timing signals T0 through T15. 6

8 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 2 The timing diagram below shows the relationship of the control signals. The sequence counter SC activated at the positive transition of the clock. Initially the CLR input of SC is active. First transition of the clock clears SC to 0, which activates the timing signal T0 for one clock cycle. SC is incremented with every clock, unless its CLR input is active. This generates the sequence of timing signals T0, T1, T2, T3, and so on. If SC is not cleared, the timing signals ill continue with T5, T6,..., T15 and back to T0. The SC can be incremented or cleared Example: T0, T1, T2, T3, T4, T0, T1,... Assume: At time T4, SC is cleared to 0 if decoder output D3 is active. D3 T4: SC < Explain memory reference instruction & ADD LDA BUN instructions in detail. Fetching of all the instruction is common and it require three t-states T0 to T2 as already discussed before. After fetching the instruction it is executed in one, two or three T-states. Below table list the seven memory reference instructions. The decoded output Di for i = 0, 1, 2, 3, 4, and 6 from the operation decoder. The effective address of the instruction is in AR and was placed there during timing signal T2 when I = 0, during timing signal T3 when I = 1. Memory cycle is assumed to be short enough to complete in a CPU cycle. The execution of MR instruction starts with T4. The actual execution of the instruction in the bus system will require a sequence of micro operations. The data stored in memory cannot process directly. The data must read from memory to register where they can be operated on wit logic circuits. ADD (add with AC): D1 T4: DR <- M [AR] Read operand 7

9 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 2 D1 T5: AC <- AC + DR, E <- COUT, SC <- 0 (Add to AC and store carry in E). This instruction performs the addition of content of AC with content of memory word specified by the effective address. The sum is transferred to AC and carry to the E flip-flop. LDA (load AC): D2 T4: DR<- M [AR] D2 T5: AC <- DR, SC <- 0 This instruction transfers the memory word specified by the effective address to the AC. The adder & logic circuit receive the information from DR which can be transferred to AC. Here first read the memory word into DR & then transfer the content of DR into AC. BUN (branch unconditionally): D4 T4: PC <- AR, SC <- 0 Transfer the program to the instruction specified by the effective address. PC holds the address of the instruction to be read from memory in the next instruction cycle. PC is incremented at time T1 to prepare for the address of the next instruction in the program sequence. It allows the user to specify an instruction out of sequence & jump unconditionally. It requires only one micro operation. The address from AR is transferred through the common bus to PC. And set SC to 0 transfer control to T0 & next instruction is then fetched & executed from the memory address at new value in PC. 8

10 Darshan Institute of Engineering & Technology for Diploma Studies Unit List types of computer instruction. Explain any one in detail. Instruction Types: 1. Functional Instructions: Arithmetic logic & shift instructions ADD, CMA, INC, CIR, CIL, AND, CLA 2. Transfer Instructions: Data transfers between the main memory and the processor registers LDA, STA 3. Control Instructions: Program sequencing & control BUN, BSA, ISZ 4. Input / Output Instructions: Input & Output In, Out Transfer Instructions: LDA (load AC): D2 T4: DR <- M [AR] D2 T5: AC <- DR, SC <- 0 This instruction transfers the memory word specified by the effective address to the AC. The adder & logic circuit receive the information from DR which can be transferred to AC. Here first read the memory word into DR & then transfer the content of DR into AC. STA (store to AC): D3 T4: M [AR] <- AC, SC <- 0 This instruction stores the content of AC into the memory word specified by the effective address. Here output of AC is put into bus & the data input of memory is connected to the bus. 8. Draw and explain flowchart for interrupt cycle. The interrupt enable flip-flop IEN can be set and cleared with two instructions. When IEN = 0, the flag cannot interrupt the computer. When IEN = 1, the computer can be interrupted. With these two options the programmer can make a decision as to whether or not to use the interrupt. With above flowchart we can see what actually happened when interrupt occurs. An interrupt flip-flop R is included in the computer. When R=0, the system goes through an instruction cycle. During execution phase of the instruction cycle IEN is checked by the control, if it is 0, it says that the programmer does not want to use the interrupt, so control goes with the next instruction cycle. If IEN = 1, control checks the flag bits, if both are 0, it means that the input and output register are not ready for transfer of information. In that case control continues with next cycle. If flag is set to 1 while IEN = 1, flip flop R is set to 1. At end of execute phase, control checks the value of R, if R=1, it goes to an interrupt cycle instead of an instruction cycle. The interrupt cycle is a H/W implementation of a branch and save return address operation. At the beginning of the next instruction cycle, the instruction that is read from memory is in address 1. At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine. The instruction that returns the control to the original program is indirect BUN 0. 9

11 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 2 R flag can be set to 1 in ay of T-states T3 or T4 or T5 or T6. But CPU will enter into the interrupt cycle after execution of present instruction and when SC is cleared to 0. The condition of setting flag R to 1 can be expressed as : T0 T1 T2 (IEN) (FGI + FGO) (T3 + T4 + T5 + T6) : R 1 Interrupt cycle will be executed as follows: RT0: AR 0, TR PC RT1: M [AR] TR, PC 0 RT2: PC PC + 1, IEN 0, R 0, SC 0 10

12 Darshan Institute of Engineering & Technology for Diploma Studies Unit Explain general register organization of CPU. When a large number of registers are included in the CPU, it is most convenient to connect them through a common bus system. The register communicates with each other for data transfer, also while performing various micro operations. So it is better to provide a common unit that can perform all the arithmetic, logic & shift micro operations in the processor. As we see below figure, ALU get two separate inputs from two buses A and B. There are eight different sources to put the data on the buses. We have general processor registers & one external input to select from for this purpose. Two 8*1 multiplexers are used to select input data to the ALU. Each multiplexer needs three select lines for selecting input. 11

13 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 3 Arithmetic & logic unit performs the operation on these two data & the result is placed on the data bus or output bus. From here result can be transferred to any of seven registers or can be outputted directly to the peripherals. To select the destination register 3*8 decoder is used which generates seven register select signals going to load input of each register (R1 TO R7). Example: To Perform Operation: R1 R2 + R3 The control must provide binary variables to the following selector inputs: 1. MUX A selector (SELA) : BUS A R2 2. MUX B selector (SELB) : BUS B R3 3. ALU operation selector (OPR) : ALU to ADD 4. Decoder destination selector (SELD) : R1 Out Bus In first clock cycle, the data from two source registers enters in the multiplexers and the ALU, to the output BUS, and into the inputs of the destination register. When next clock cycle occurs, the binary information from the output bus is transferred into R Explain stack organized CPU in detail. Stack is a type of memory implementation in which data can be retrieved which was just stored in it. It is also knows as Last In First Out (LIFO) memory. Just as there is an address register (AR) for main memory, stack memory have a stack pointer. We can read or write into stack Memory register whose address is indicated by stack pointer. Stack pointer always points to the top of stack. Two operation of a stack are the insertion and deletion of items. The operation of insertion is called PUSH, it can be thought of as the result of pushing a new item on top of stack. The operation of deletion is called POP,it can be thought of as the result of removing one item so that the stack pop up (However nothing is pushed or popped in a computer stack. These operations are carried out by incrementing or decrementing the stack pointer register. In above figure, a register stack is shown. The size of stack pointer is 5 bit so the size of stack is decided to be 32 words. There are two single bit flip-flops, namely FULL& EMPTY to keep 12

14 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 3 track of the status of stack. When no data is entered in to stack is said to be empty & at that time EMPTY flag is set to 1, also at this time stack is not full, so FULL flag is cleared to 0. If we enter just one data item in to stack, it is now no more empty. So, EMPTY flag will be cleared to 0. The FULL flag will remain 0, as long as there is at least one free memory location in the stack (where there is no free memory location available in stack then the FULL flag will be set to 1. This set/reset of FULL & EMPTY flags is carried out as per the condition of the stack, pointer as can be seen by the micro operations performed during PUSH & POP operation as shown below: Execution of PUSH instruction: Writing Into stack is known as PUSH operation. Initially SP (Stack Pointer) is cleared. EMPTY flag is set to 1 and FULL flag is cleared to 0. SP is pointing to 0 th location of the stack. This is top of stack in the beginning. At 0 th location of stack no data is stored, so no PUSH or POP operation is possible at this location. Following are the sequence of micro operation for PUSH operation: SP SP + 1 : stack pointer is incremented. If( SP = TOS ) then (FULL 1) : check if stack is full or not. M[ SP ] DR : at this new location data is written. EMPTY 0 : now, stack is not empty. Execution of POP instruction: Reading from the stack is known as POP operation. POP operation consists of following sequence of micro operation: DR M[ SP ] : Read data from the top of stack. SP SP - 1 : Stack pointer is decremented by one. If( SP = 0) then (EMPTY 1) : Check if stack is empty or not. FULL 0 : now, stack is not full. SP is pointing to top of stack; the last item which was written into stack. The data will be copied to DR. Now SP is decremented by one location. Then SP is checked & if is found 0 then stack is empty, so empty flag is set to 1. If before this POP operation stack was full (FULL 1), then after this POP operation stack do not remain FULL. SO, FULL flag is cleared to Explain different types of instruction formats. The number of address fields available in instruction defines the format of instruction. There are different format for the instructions like zero, one, two, three address fields. Let the arithmetic operation be: X = (A + B) * (C + D) 1. Zero address field instruction: The stack organized CPU uses this type of instruction. It is inherent that the operations will take place between top two data pushed into stack so in such computational instruction address information is not required. Of course for PUSH and POP instruction one address field is required. The operation will be solved as program, before that convert this infix notation into RPN: AB + CD + * PUSH A /* TOS A */ 13

15 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 3 PUSH B /* TOS B */ ADD /* TOS (A + B) */ PUSHC /* TOS C*/ PUSH D /* TOS D */ ADD /*TOS (C + D) */ MUL /* TOS (C + D) * (A+ B) */ POP X /* M[X] TOS */ 2. One address instruction: In such type of format, the CPU organization uses accumulator implied addressing mode. LOAD A /* ACM [A] */ ADD B /* AC AC+ M [B] */ STORE T /* M[T] AC */ LOAD C /* AC M[C] */ ADD D /* ACAC + M [D] */ MUL T /* ACAC*M [T] */ STORE X /* M[X] AC */ Here T is address of temporary memory location where immediate results are stored. Also note that only seven instructions are required to solve the operation, thus binary instruction becomes still smaller. 3. Two address instruction: These types of instructions are quite common in commercial computers. The operation can be solved as: MOV R1, A /* R1 M [A] */ ADD R1, B /* R1 R1 + M [B] */ MOV R2, C /* R2 M[C] */ ADD R2, D /* R2R2 + M [D] */ MUL R1, R2 /* R1R1 + R2 */ MOV X, R1 /* M[X] R1 */ Here operation specific instructions are used (like MOV, ADD, MUL) to solve the operation. Here address fields are two, CPU designs becomes simpler. More time is needed since we need six instructions to solve to come to the result. 4. Three address instruction: Results in short program but instruction becomes long (many bits). The drawback of this type of format is that the word size increase and it is more difficult to handle big word at a time. The design of CPU bus structure also becomes difficult. ADD R1, A, B /* R1M[A] + M[B] */ ADD R2, C, D /* R2M[C] + M[D] */ MUX X, R1, R2 /* M[X]R1 * R2 */ 14

16 Darshan Institute of Engineering & Technology for Diploma Studies Unit Explain different addressing modes with example. The way in which operand is selected during instruction execution is decided by addressing mode. If there are more than one address fields then different addresses may have different addressing mode. Different addressing modes are as under: 1. Implied mode: There is one command CMA, to complement the accumulator content. In this command separate address field for accumulator is not required but it is specified implicitly. All the register reference and memory reference instruction that involve accumulator are implied mode instruction. i.e. ADD B == AC AC + B Here, address information for register B is required to be supplied but address for accumulator is implied and no need to supply. This is called implied addressing mode. 2. Immediate mode: In this type of addressing mode, the data is supplied with the instruction itself. Such instruction do not have address field but have operand or data field. Such instructions are used to initialize the processor registers. 3. Register mode: If the address field specifies the CPU register for the operand, then it is called register mode addressing. If the address field is of k bit then it can specify 2k CPU register. 4. Register indirect mode: If the address field of the instruction specifies the CPU register where the true address of the data is stored than such type of addressing mode is called register indirect mode. 5. Auto increment or auto decrement mode: If the table implement in the memory is accessed by the program, then it is possible that the next access will be just one location after or before the present memory address. For such situation the memory address should be just increment or decrement by one. 6. Direct address mode: If the address information in the address field of the instruction is true or effective then it is called direct addressing mode. 7. Indirect addressing mode: If the address information in the address field of instruction is the address value of a memory location in which true or effective address is stored then it is called indirect address mode. In indirect mode two memory accesses are needed to acquire the data for the ALU. The effective address = content of the address field of instruction + content of CPU register. 8. Relative address mode: In this type of addressing mode, the content of the program counter is added to the address part of the instruction and the effective address is calculated. Relative address mode is used in branch instruction where the ranch address is not too far off the present location of instruction, but relatively near. 3 different relative addressing modes depending on R: PC relative addressing mode ( R = PC) EA = PC + IR (address) Indexed addressing mode ( R = IX, where IX : index register) 15

17 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 3 EA = IX + IR (address) Base register addressing mode ( R = BAR, where BAR : base addressing register) EA = BAR + IR (address) 9. Indexed address mode: Here the content of an index register is added with the content of address filed of present instruction, to find the effective address. In some computers a special register is dedicated for this purpose. In case CPU has many registers then one register must be explicitly set as indexed register. 10. Base register address mode: In this mode the content of address field of instruction is added with content of register. Almost same as index address mode but use is different. In base register is kept constant and the address field of instruction is updated to generate the address. 13. Explain characteristics of RISC and CISC architecture. Characteristics of RISC: Relatively few instruction mostly register to register operations. Relatively few addressing modes (because of 1). Memory access limited to load and store instruction. All operation done within the register of the CPU. Fixed length, easily decoded instruction format simplifies control logic. Single cycle instruction executions i.e. fetch, decode and execute phase. Hardwired rather than micro programmed control (faster). A large number of register useful for storing intermediate result and for optimizing operand references. Uses overlapped register windows to speed-up procedure call and return. Efficient instruction pipeline. Compiler support for efficient translation of high level language programs into machine language programs. Characteristics of CISC: A large instruction set. Instruction that perform special tasks and are used infrequently. A large variety of addressing modes (5-20 different modes). Variable length instruction formats. Instruction that manipulate operands in memory. 14. Explain different types of interrupts. There are three types of interrupts that cause a break in the normal execution of a program. 1. External interrupt: Generated from (I/O) devices like peripheral devices, timing devices, from a circuit monitoring devices or any other external source. When I/O device is ready to communicate with CPU, t generates external interrupt. On receiving this interrupt, CPU will execute corresponding service routine. Similarly when timing set for a particular event is elapsed; timing device generates external interrupt, which is executed by CPU. Similarly, when circuit monitoring device detects power failure, it generates interrupts. 16

18 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 3 Such interrupts are known as external interrupt. 2. Internal interrupt: When any erroneous or illegal use of data or instruction is done, internal interrupt is generated. It is also called TRAP. Generally these types of interrupt are generated from software due to any error in s/w instruction that is being executed. On receiving erroneous instruction, CPU generates that interrupt signal and takes necessary action to rectify the problem. E.g. Of such erroneous instruction are data overflow, divide by zero, stack overflow, protection violation etc. 3. S/W interrupt: S/W interrupt is a special call instruction that works like interrupt rather than subroutine call. It is used by programmer to initiate the interrupt procedure whenever programmer wants. These types of interrupt are used to switch between user mode and supervisor mode operation of CPU. Normally application programs are run in user mode, but whenever application requires supervisor mode, S/W interrupt is generated from programmer for switch to supervisor mode. Such interrupt are called as S/W interrupt. 15. RPN example calculation. There are three types of notation: 1. Infix notation A+B: Here mathematical operation is placed in between two operands (data A and B). If the expiration is quite big, including all types of operator and parenthesis (single or multiple) then it becomes quite difficult and involves many back and forth scanning to solve the arithmetic expression. It becomes difficult and time consuming. To avoid this we use RPN or postfix notation. 2. Postfix notation: In this notation, the operator is placed after two operand (two data) on which the operation is to be performed. 3. Prefix notation: In this notation, the operator is placed before two operand (two data) on which the operation is to be performed. Let us see to convert arithmetic expression from infix polish notation. A+B infix notation +AB prefix or polish notation AB+ postfix or reverse polish notation Consider following infix arithmetic operation. (A+B) + [C-(D/F) **2] The hierarchy of different mathematical operator is as: ** Exponentiation * Multiplication / Division 17

19 Darshan Institute of Engineering & Technology for Diploma Studies Unit Addition - Subtraction Solution to convert above operation to postfix notation. 1. AB+ + [C DF/ ** 2] 2. AB+ + [C DF/2**] 3. AB+ + CDF/2** 4. AB+CDF/2** + 18

20 Darshan Institute of Engineering & Technology for Diploma Studies Unit What is cache memory? Explain direct mapping of cache memory. The computer program consists of loop and sub-routine calls. Every time there is a need to reference memory for such loop & sub- routine calls. So when this program is executed, there is repeated memory access done for same instructions. To lesser this degree of memory references, we use a special memory called cache memory which is placed inside CPU. Cache memory is the nearest memory processor. Above figure demonstrate the CPU connection with cache memory & main memory. The CPU communicates with both memories. It first searches the cache for address. If there is a hit, the CPU gets data from cache. If there is a miss, CPU reads the word (data address) from main memory & the same word is transferred to cache. The basic characteristic of cache memory is its fast access time. Thus, very little or no time must be wasted when searching for words in cache memory. In order to achieve this, three types of mapping are used from main memory to cache memory: 1. Associative mapping 2. Direct mapping 3. Set-associative mapping Direct Mapping: 19

21 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 4 In general case, there are 2 k words in cache memory and 2 n words in main memory. The n bit memory address is divided into two fields: k bits for the index field and n-k bits for the tag field. The direct mapping cache organization uses the n-bit address to access the main memory & k-bit index to access the cache. This concept is shown in figure below: When a new word is first bought into cache, the tag bits are stored data bits. When CPU generates a memory request, the index field is used for the address to access the cache. If the tag field in cache is matched with index field with main memory, there is a hit else there is a miss. If there is a hit, the CPU gets data from cache. If there is a miss, CPU reads the word (data address) from main memory & the same word is transferred to cache. 18. Explain cache coherence, associative mapping, Write Through & Write Back in cache memory. Cache coherence: In case of shared memory multiprocessor with each processor having separate cache memory, there can be many copies of same instruction operand example one copy in main memory & one in each cache memory. When one copy of operand is changed, the other copies must also be changed in parallel. Associative mapping: The fastest and most flexible cache organization uses associative memory. Associative memory stores both the address and content (data) of memory word. Thus any location in cache can store any word from main memory. Above diagram shows the associative mapping example. As shown, there are words stored in cache. The tag in cache represented the index of data in main memory. A CPU address is first searched inside cache associative memory for matching address. If address is found, there is a hit else there is a miss. If there is a hit, the CPU gets data from cache. If there is a miss, CPU reads the word (data address) from main memory & the same word is transferred to cache. 20

22 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 4 Write through: Whenever there is an update of data done by CPU, this update has to be done in main memory and cache memory parallel. This method is called write through method. The advantage of this method is that the main memory and cache memory always have the same data. This is more helpful when using DMA transfers. Write Black: In this method, only the cache location is updated during the write (update) operation. On updating cache, it is marked as flag so when the word is removed i.e. when operation completes, the updated data is copies to main memory. 21

23 Darshan Institute of Engineering & Technology for Diploma Studies Unit What is I/O interface? Draw Block diagram of communication link between microprocessor and different peripherals. The purpose of communication link is to resolve following difference that exist between the central computer and each peripheral. 1. The conversion of signal values is required between peripherals (electromagnetic device) & CPU (electronic devices). 2. Synchronization in data transfer rate between both CPU and peripheral devices. 3. Data codes & formats in peripherals differ from the world format in the CPU and memory. 4. The operating modes of every peripheral are different, thus CPU need to control them so each peripheral do not disturb operation of other. To resolve these differences, CPU uses interface units to supervise and synchronize between CPU and peripherals. CPU uses Input-Output interface that matches the formats & timing characteristics of CPU with peripherals. A communication link between processor and several peripherals is shown in above figure. The I/O consists of data lines, address lines and control lines as shown. Each peripheral device has its own interface unit. Each interface decodes the address & control received from I/O bus. Also synchronizes the data flow & supervises the transfer between CPU and peripherals. Each peripheral has its own controller that operates particular device for example printer controller controls the paper motion, the print timing and selection of printing character. To communication with a peripheral device, the CPU places a device address on the address lines. Each interface has address decoder that monitors the address lines. When interface detects its own address, it activates the path between bus lines and device. 21. Explain modes of data transfer. There are three modes of data transfer between peripherals & CPU 1. Programmed I/O 2. Interrupt initiated I/O 3. Direct memory access (DMA) Programmed I/O: In a programmed I/O method, the I/O devices do not have direct access to memory. A transfer from an I/O device to memory requires the execution of several instructions by CPU. Other instructions may be needed to verify that the data is available from device & to 21

24 Darshan Institute of Engineering & Technology for Diploma Studies Unit - 5 count the number of words transferred. Here, a program is written for the computer to check the flag in the status register to see if the byte is placed in data register or not. This is done by reading the status register into a CPU register and checking the value of flag bit. If the flag = 1, the CPU reads the data from data register. Once data has been read, the flag bit is cleared to 0 by CPU or by interface depending on program written. Once flag bit is cleared to 0, interface disable data accepted line and device can then transfer the next data bytes. A flowchart of program written for CPU is shown above. It is supposed that device is sending a sequence of bytes that must be stored in memory of CPU. The transfer of each byte requires three instructions. 1. Read the status register 2. Check the status of the flag bit and branch to step 1 if not set or step 3 if set. 3. Read the data register Interrupt Initiated I/O: In Programmed I/O, the CPU stays in program loop until device indicates that it is ready for data transfer. This is time consuming process since the processor remains busy uselessly. This can be avoided by generating interrupt request signal by device s interface whenever it is ready. In the meantime, CPU can work with other program till interrupt signal occurs. The interface keeps monitoring the device. When interface determines that the device is ready, it generates the interrupt request to CPU. On receiving this interrupt, CPU momentarily stops its current task, and executes the Interrupt Service Routine. On completion of ISR CPU returns to the task it was originally performing. DMA: In DMA, the interface transfers data to or from the memory through the memory bus. Large blocks of data transferred at a high speed to or from high speed devices, magnetic drums, disks, tapes, etc. When transfer is completed, DMA requests memory cycles through the memory bus. When bus is granted, DMA transfer data directly to memory. DMA Controller: It is an interface that provides I/O transfer of data directly to and from the memory and the I/O device. CPU initializes the DMA controller by sending a memory address and the number of words to be transferred. The CPU merely delays its memory access operation to allow the direct memory I/O transfer. Actual transfer of data id done directly between the device and memory through DMA controller. Many computers combine the interface logic with the requirements for direct memory access into one unit & call it an I/O processor (IOP). 22

25 Darshan Institute of Engineering & Technology for Diploma Studies Unit Explain with diagram the function of Input-Output Processor (IOP). The IOP is similar to CPU except that it is designed to handle I/O processing. IOP can fetch & execute its own instructions. IOP instructions are specifically designed to performed I/O transfers. The block diagram of computer with two processors is shown above. Memory unit is at centre so it can communicate with both processors by using DMA. The IOP provides path for transfer of data various peripherals & memory unit. Once CPU starts I/O program, IOP operates independent of CPU & transfer data between peripherals & memory. IOP gathers the data from peripherals at device speed & bit rate, once data is obtained it transfers that data directly to memory by stealing (taking) one memory cycle from CPU. Similarly data is transferred from memory to peripheral. The communication between IOP and devices attached to it is similar to program control I/O. The way in which IOP & CPU communication is shown in figure below: 23