PRES: A Pseudo-Random Encoding Scheme to Increase Bit Flip Reduction in Memory

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1 PRES: A Pseudo-Random Encoding Scheme to Increase Bit Flip Reduction in Memory Seyed Mohammad Seyedzadeh, Raan Maddah, Alex Jones, Rami Melhem Computer Science Department, University of Pittsburgh {seyedzadeh,maddah,jones,melhem}@cs.pitt.edu ABSTRACT Nonvolatile memory technologies such as Spin-Transfer Torque Random Access Memory (STT-RAM) and Phase Change Memory (PCM) are emerging as promising replacements to DRAM. Before deploying STT-RAM and PCM into functional systems, a number of challenges still remain. Specifically, both require relatively high write energy, STT-RAM suffers from high bit error rates and PCM suffers from low endurance. A common solution to overcome those challenges is to minimize the number of bits changed per write. In this wor, we introduce Pseudo-Random Encoding Scheme (PRES) to minimize the number of bit changes during memory writes. PRES maps the write data vector into an intermediate highly random set of data vectors. Subsequently, the intermediate data vector that yields the least number of differences when compared to the currently stored data is selected. Our evaluation shows that PRES reduces bit flips by up to 5% over a baseline differential writing scheme. Further, PRES reduces bit flips by 15% over the leading bit-flip minimization scheme, while decreasing encoding and decoding complexities by more than 90%. Categories and Subject Descriptors B.8. [Performance and Reliability]: Performance Analysis General Terms Design, Reliability Keywords Memory, Endurance, Pseudo-Random Encoding 1. INTRODUCTION As the number of cores per chip continues to increase, the memory system is becoming more than ever a defining component for the performance of computer systems. A large memory capacity operating under stringent quality of service requirements is required to respond to memory access requests of executing cores within acceptable latencies. Unfortunately, DRAM, which currently forms the building bloc of the memory system, is becoming limited by power and scalability challenges, thus, endangering the evolution of the memory system. This has turned the attention of architects and researchers to considering alternative memory technologies [1 4]. Amongst several memory candidates, both Phase Change Memory (PCM) and Spin-Transfer Torque Random Access Memory (STT-RAM) are receiving considerable attention as potential replacements for DRAM. Assessments and evaluations of PCM [5, 6] show that it can compete with DRAM in terms of performance while providing improved scalability and power efficiency. Multi-level cell techniques for STT- RAM [7] suggest the potential for near DRAM densities while retaining a near SRAM performance (potentially faster than DRAM). Yet, both technologies suffer from a number of challenges that must be resolved to become viable for high volume manufacturing. Specifically, PCM suffers from low endurance [8] (10 6 to 10 8 writes on average) and STT-RAM suffers from high write bit error rates [9, 10]. To address the challenges faced by PCM and STT-RAM, servicing write requests while minimizing the actual number of bits written to memory is a promising approach. This achieves a reduced effective wear-out rate of PCM cells and a lower effective bit error rate for STT-RAM. In its simplest form, minimizing the actual number of bit flips can be achieved through a concept called a differential write [11]. Differential write is a bit by bit comparison between the new data to be written and the currently stored data within the memory bloc and subsequently only writing to the cells that their stored bit values differ than their new bit values. Clearly, the higher the similarity of the new data to the currently stored data the lower the number of required bit changes. In this realm, coding techniques [1 16] have been used to encode the new data into a form that exhibits high similarity of the data to be written to the currently stored data. The encoding process consists of mapping the new data vector to be written into several other vector candidates and subsequently picing the candidate that minimizes the bit flips. In this paper, we mae the following contributions to data encoding for bit flip minimization as follows: We observe that increasing the randomness of encoded vector candidates decreases the required number of bit flips required for unbiased (i.e. apparently random) data sets. We demonstrate mathematically and by simulation that random encoding outperforms the leading bit-minimization encoding approach based partially inverting bits of the current value. As truly random data vector generation is a non-reversible transformation, we propose a low overhead, reversible pseudo-random encoding scheme (PRES) for bit-flip minimization of unbiased data. We demonstrate the randomness using a battery of random code tests for both PRES and the leading encoding for bit flip minimization that uses Hamming dual codes. PRES reduces bit flips by up to 5% over a baseline differential writing scheme. Further, PRES reduces bit flips

2 by 15% over the leading bit-flip minimization scheme, Flip- Min, while decreasing encoding and decoding complexities by more than 90%. The remainder of this paper is organized as follows. Section presents fundamentals on bit flip reduction techniques. Section 3 explores the effect of randomization on bit flip reduction. Section 4 describes PRES in detail including the encoding and decoding process and overheads. Section 5 presents a experimental evaluation of PRES and conclusions are related in Section 6.. BACKGROUND: WRITE MINIMIZATION USING COSET THEORY There have been several proposals to minimize the number of bit differences between two consecutive values for a variety of purposes. For example, coset theory was proposed to reduce the number of bit transitions between two successive values [17, 18]. However, coset theory can be used to further reduce the number of bits written in emerging memory technologies. Recall, as mentioned in the previous section, differential write [11] is a technique to minimize bits written by only writing bits that change value during the write operation. Consider an n-bit data bloc B that is to be written to an n-cell memory bloc that already stores data D. A traditional differential write first reads D, compares it with B and only writes the bits of B that are different from their corresponding bits in D. Thus, for entirely random data, the distribution of zeros and ones in both B and D is random, and hence, on average, n/ bits are written to memory instead of n bits. Coset theory attempts to increase the number of bits that are identical in B and D by exploring a number K of possible encodings of B, where K =. The overall number of written bits can be reduced by selecting the encoding that has the minimum Hamming distance to D (the fewest number of different bits). To recover the original data B, it is necessary to have a unique decoding path. To accomplish this, the coset approach defines a fixed set of K, n-bit vectors, C 0,..., C K 1 and uses these vectors to generate K different encodings of B through bit-wise XOR. We denote these K different encodings of B as W 0,, W K 1 where each W i, 0 i K 1, is an (n + )-bit vector with the first n bits equal C i B and the last bits record the binary representation of the index i. Any W i among the K possible encodings can be decoded bac to B by recovering i from the last bits of W i to looup and XOR C i with the first n bits of W i, i.e., (C i B) C i = B. To minimize the number of bits written, as previously mentioned, coset writes the encoding W i that has the minimum Hamming distance from D (the data already stored in memory). However, using coset, each W i and D contains n + bits, while the data bloc, B, contains only n bits. The additional bits, which we recall stores the index i, represents the coding overhead that is needed to reduce the Hamming distance and minimize the number of bits written during a differential write. We denote these overhead bits as h 0,..., h 1. In the rest of this paper, we will refer to the set C 0,..., C K 1 as the base coset. Flip-N-Write (FNW) proposes a method to reduce bits written using differential write by selectively inverting blocs of the data to be written [15]. In general, for any number of bits, Flip-N-Write divides B into equal partitions and writes each partition directly or inverted, whichever minimizes the number of written bits. It uses overhead bits h 0,, h 1 to trac which partition is inverted to allow retrieval of the original data. FNW is a special case of the coset approach in which each n-bit vector C i in the base coset is constructed from K = sub-vectors, C i,j, j = 0,, K 1, each consisting of n/ bits. Specifically, if the overhead bits, h 0,, h 1, are used to store the binary representation of the index i, then the n/ bits of C i,j are all zeroes if h j = 0 and the n/ bits of C i,j are all ones if h j = 1. For example, if = 1 (that is K = ), then the Base Coset for Flip-N-Write contains the two vectors 0 0 and 1 1, which means that the data vector B can be either written as is B 0 0 or written inverted B 1 1, with one overhead bit, h 0, indicating which of the two option is used. For = (that is K = 4), the Base Coset for Flip-N-Write contains the 4 vectors , , and , which means that B is divided into two halves and each of the two halves can be either inverted or not inverted, with one overhead bit, h 0, to indicate if the first half is inverted and another overhead bit, h 1, to indicate if the second half is inverted. Another approach for write minimization, Flip-Min, proposes using a special instance of coset theory to encode using Hamming (7,64) s dual code [19] to obtain W 0,, W K 1 from B and to decode any W i bac to B [16]. Experimental studies showed that Flip-Min reduces the number of written bits further than FNW. Thus, we have two options from previous wor to build n-bit vectors in the base coset. The first option is based on FNW and leverages simple and non-random patterns such as 0 0 and 1 1. The second option is based on FlipMin and utilizes the generator of the linear code. Since n-bit vectors are derived from the linear combinations of the rows of the generator matrix, they are not random. In the next section, we propose a third option for the base coset. 3. WRITE MINIMIZATION USING A RANDOM BASE COSET In this section, we tae a different approach to building the base coset by randomly generating each vector C 0,, C K 1. In this section we mathematically demonstrate that a random base coset can complete write requests while inducing fewer bit flips than FNW. Given a memory bloc of size n and auxiliary bits, the number of written bits (NWB) by FNW [15] can be expressed as: NW B F NW = n 1 n 1 i i=0 ( n ) ( ) + n n i n +1 n To derive a formula for the number of written bits when the base coset consists of K randomly generated vectors, C 0,, C K 1, we compute the Hamming distance between each encoded vector C i B and the currently stored data, D. We then estimate the expected value of the minimum of this distance over i = 0,, K 1. The Hamming distance between C i B and D is equal to the Hamming weight of C i B D. Moreover, because B, D and C i are random, then C i B D is also random. This implies that NW B Random is equivalent to the expected value of the minimum Hamming weight of K random vectors. The random vector, C i can be any element of the set of n possible strings of zeroes and ones. We divide the set of n possible elements into the set of n distinct groups so that each group has elements. The number of groups can change from one group ( = n) to n groups ( = 0). We assume that the weight of a word is determined by the number of ones it contains denoted by the parameter w such that 0 w n. The total number of elements that has weight w in the (1)

3 set of n elements is ( n w). Since the number of elements in each group is, the number of elements with weight w in a group of elements ranges 1 l. In the set of n elements, there are ( n ) different combinations to form n distinct groups so that each group includes elements. To obtain the average weight of groups, we follow steps 1-3 as follows: Step 1. Find the number of combinations with the weight w so that each combination has at least one element with weight w and at most elements with weight w as follows: l=1 (( n w l )) ( n j=w+1 l ( ) n j) Step. Multiply outputs of Step 1 by the corresponding weights as follows: ( n (( n )) ( n ( )) n w w j=w+1 j) (3) l l w=0 l=1 Step 3. Calculate the average number of bits updated per write (denoted NW B Random ) as follows: ( n w=0 w ( ( n ) ( w) n l=1 l j=w+1 ( n j) ) ) l NW B Random = ( n ) (4) where 0 w n, 1 l and 0 n. Figure 1 shows the bit flip reduction over differential write (n/ bit flips) achieved by random based cosets and FNW based cosets derived through Eq. (4) and Eq. (1). The random based coset achieves considerably higher flip reduction rates than a FNW based coset for various different bloc sizes. Accordingly, we propose in the next section a new write minimization scheme that is based on the idea of random cosets. Unfortunately, it is infeasible to determine an analytical model to estimate the number of required bit flips for Flip- Min to complete a write request. Thus, we rely on Monte Carlo simulations to compare random cosets against Flip- Min. Our analysis from these simulations do indicate that random cosets can achieve significantly fewer bit flips than Flip-Min and we report these results in Section WRITE MINIMIZATION USING PSEUDO- RANDOM ENCODING In Section we introduced cosets that can encode a value B into a value W i that reduces the bit transitions when writing to a memory cell containing D using differential write. We can also refer to the encoded value W i as a codeword. In Section 3 we demonstrated that using a randomly generated coset provided higher reduction in bit flips to the leading existing flip minimization schemes. However, to decode a codeword encoded with a random coset, we need to now the random vector C i that we used to encode the data. Since an inverse generator matrix concept used in Flip-Min is not a valid option for a random coset, we are left with the option of generating the random coset elements in advance and storing them in both the encoder and the decoder. Unfortunately, this option incurs an unnecessarily large storage overhead. Another potential solution is to use a random number generator at encoding time. Such an encoder leverages the initial value B to generate the random coset. The use of traditional pseudo-random number generator has a few dif- () Bit Flip Reduc:on ( =8 auxiliary bits) 5% 0% 15% 10% 5% 0% Random Based Coset FNW Based Coset 64 (1.5%) 18 (6.5%) 56 (3.15%) 51 (1.565%) 104 (0.7815%) Bloc Size Figure 1: Weight average difference of FNW and random cosets with 8 auxiliary bits and different bloc sizes. The value in between the parenthesis represents space overhead. ficulties, the overhead of generating these random numbers has a high hardware overhead and is typically irreversible. To address these difficulties, in this section we propose PRES, a novel tree-structure pseudo-random encoding model to generate pseudo-random vectors directly from the value B. PRES does not require additional storage for coset elements. PRES codewords are quicly recoverable using an efficient decoding mechanism that is less complex than Flip- Min. Further, we define conditions for our proposed treestructure model to encode/decode to guarantee that the generation of the pseudo-random vectors is demonstrably close to true random through several standard tests. We describe the PRES scheme in detail in the following sections. 4.1 PREM: A Pseudo-Random Encoding Model We first define a pseudo-random encoding model (PREM) to decorrelate a data bloc B as: P n 1 B i i=0 P i = B i 1 B i i=1 P i 1 B i i=,...,n-1 where B i and P i represent the i-th element of the data bloc and the pseudo-random vector, respectively. The parameter n is the number of memory cells to be encoded. As illustrated in Eq. (5), P i for 1 i n 1 is first generated, followed by P 0 that is produced with P n 1 from the previous step and B 0. Eq. (5) has been designed so that all B i have the potential to be updated after each encoding process; Since, the probability of the cell having a 0 or 1 is 1, it follows that the probability of the cell being updated is also 1. Thus, the probability of cells with dif- Pn- 1 Pn- 1 B0 B1... Bn- Bn- 1 P0 P1... Pn- Pn- 1 B0 B1... Bn- Bn- 1 Figure : Overview of PREM for encoding and decoding. Encoder Decoder (5)

4 LR RL TB BT Dataword Bloc/Index (a)/ (b)/ (c)/ Figure 3: PRES 16-bit example (a) the 4 4 bloc, (b) the generation of parents, (c) the generation of children. ferent values is 1 because the corresponding combinations are 0 1 and also 1 0 out of the four possible combinations that also include 0 0 and 1 1. Therefore, there is a high probability to produce pseudo-random vectors using Eq. (5). The corresponding decoding algorithm for Eq. (5) can be expressed as: P n 1 P i i=0 B i = B i 1 P i i=1 (6) P i 1 P i i=,...,n-1 Figure shows the feedbac path from the left side to the right side that causes P i to be produced serially. As shown in Figure, there is no feedbac path between P i and B i. However, the advantage of this configuration is that all cells in the decoder can be simultaneously decoded. Thus, read accesses that are typically on the critical path for processor performance and require decoding can be streamlined. Further, several pseudo-random encodings can be obtained by applying PREM in different bit-orderings to expand the number of candidate encodings. For example, if the feedbac path in Figure is used from the right side to the left side (i.e., reversed), the pseudo-random vector P can be generated. Thus, it is possible to utilize one bit pattern in two different directions to build P and P. To produce additional pseudo-random codewords, the encoding process can be applied in different patterns such as different bloc interleaved orderings. We describe this process in the following section and use this to build an indexable set of pseudorandom vectors for write minimized encoding. 4. PRES: A Pseudo-Random Encoding Scheme We can create p different patterns by subdividing B into sub-blocs conceptually represented by the rows (or columns) of a two dimensional matrix. Thus, PRES can simultaneously and independently encode these sub-blocs using PREM in two opposite directions to generate two different pseudo-random codewords. By constructing p different matrices we can generate p codewords. For a partition based pseudo-random generator model to be functional, there are certain requirements on how each matrix be partitioned and encoded. To that end, each particular partitioning corresponds to a particular pattern and results in a unique pseudo-random encoding. However, partitions should attempt to group bits in the sub-blocs such that each partition groups unique bits together and does not repeat bits grouped together in other partitions sub-blocs. If overlapping occurs, those bits are guaranteed to have the same values in the two different codewords, which decreases the randomness of the encoding candidates. Ensuring that the patterns have minimal overlap maes it possible to build a partition based pseudo-random generator model that closely mimics an ideal random encoding generator. One way to do this is to use a single matrix and to apply PREM along different dimensions using different orderings such as along rows, then columns, diagonals, etc. In PRES we propose a two-phase tree structure to generate p codewords in the first phase and to tae these resulting codewords and from each generate p 1 codewords in the second phase, resulting in a total of p (p 1) codewords. We assume each matrix partitions the n bits of B in a square m m matrix, such that each row (or column) of the matrix can be considered a sub-bloc that contains m bits 1. The encoding process is explained as follows: Step 1. The encoder uses p given patterns in the tree structure to partition B into the equal sub-blocs and generate p new partitioned matrices. PREM is independently applied to the sub-blocs of p new partitioned matrices in two different directions to generate p pseudo-random codewords. The generated codewords are different in terms of the used encoding direction or the pattern. Then, each codeword can be re-partitioned into p new matrices to produce p 1 codewords by PREM. Note, the same direction of the original PREM used to generate the first phase codeword is not used as it will essentially reproduce several bits of the original bloc B. Step. The encoder utilizes -bit indices ( = log 4p ) to label the generated codewords (C 0,, C 1) in Step 1 and compare each codeword, concatenated with its corresponding index (i.e., W i), with D. The W i that has the minimum Hamming distance to D is selected. Step 3. Then, W i is written to memory. To retrieve B, the decoder uses the index i in memory to find the corresponding patterns (matrix partitioning) and encoding directions used for the codeword written in memory. Finally, the decoder using Eq. (6) restores the original data bloc by reversing the two phases from the encoding. To clarify the process we provide a detailed example in Figure 3 to generate 16 pseudo-random codewords from a new 16-bit data bloc storing B=0xBC07 and then minimize the number of bits flipped during the write to the memory that currently stores an existing value D=0x Recall that D is the concatenation of a previously stored codeword (16-bits) and index (4-bits) requiring 0-bits of storage to store a 16-bit value. Let us assume bits of B are arranged in a 4 4 matrix [Figure 3(a)]. In the first phase of PRES, 1 It is relatively straightforward to extend this idea to support non-square matrices through repartitioning.

5 PREM is applied to the matrix from Left-to-Right (LR), Right-to-Left (RL), Top-to-Bottom (TB), and Bottom-to- Top (BT). Note, TB is equivalent to applying LR to the transposed matrix. Each function generates one codeword we call a parent [Figure 3(b)]. In the next phase, each parent using the three other functions generates three additional codewords, or children. For instance, the parent generated by LR uses RL, BT and TB functions to create three children [Figure 3(c)]. Each parent and child is provided a 4-bit unique index. PRES then compares 16 generated codewords and index (i.e., W 0,, W 15) with D (i.e., 0x00000) and selects W i with the minimum Hamming weight. According to Figure 3, the bloc with the minimum Hamming weight is five at index i = 4. Thus W 4 is written in memory. It is important to note that PRES actually generates 17 codeword candidates, because the original data B can be a codeword. If there is a desire to use the original data as one of the codeword candidates, rather than use an additional index bit, we can systematically replace one of the generated codewords with B. Also, in this example, only p = patterns (horizontal and vertical) were used to generate 16 pseudo-random codewords. If we have additional index bits (e.g., 6-bits), PRES can utilize other patterns such as southwest-to-northeast and southeast-to-northwest diagonal patterns to increase the generated pseudo-random codewords from 16 to EXPERIMENTAL RESULTS In this section, we evaluate PRES against both Flip-min and FNW. We compare the reduction in bit flips achieved by each scheme with respect to differential write as a baseline. Moreover, we compare the encoding and decoding overhead of each scheme in terms of the number of required operations. Finally, we measure the randomness degree of the data vectors generated by the encoder of each scheme. Our experiments process random data and are applied across various bloc sizes with different space overhead. 5.1 Comparison of Bit Flip Reduction To compare the bit flips reduction over differential write, we assign each scheme 4 auxiliary bits ( = 4) i.e. the base coset of each of the three schemes encompasses 16 different elements. In addition, we experiment with different size blocs to vary the incurred space overhead. Figure 4 shows that PRES is capable of flipping fewer bits than either Flip- Min or FNW across different bloc sizes with varying space overhead. PRES requires up to 15% and 3% fewer bit flips than Flip-Min and FNW, respectively. To achieve higher flip reduction rates, the number of elements of the base coset can be increased to allow the currently stored data to be compared against more data vectors. Accordingly, we extend the number of auxiliary bits to eight (56 elements per coset) and plot our findings in Figure 5. The results show that for the same space overhead as in Figure 4, the flip reduction capabilities of PRES, as well as Flip-Min and FNW, have significantly improved. For a space overhead of 1.5%, the flip reduction capability of PRES increased from 1% to 5% which amounts to a 15% improvement. This improvement comes at a higher computational overhead as a larger base coset requires more elements to compare against. Thus, the number of elements that forms the base coset requires a trade-off between the flip reduction capability and the increase in computational complexity. We note that with a larger base cost, Flip-Min gets closer to the capability of PRES for blocs with higher space overhead. However, the performance overhead of Flip- Min is significantly larger than PRES as we show next. Bit Flip Reduc:on (=4 auxiliary Bits) 0% 15% 10% 5% 0% 3 (1.5%) 64 (6.5%) 18 (3.15%) 56 (1.565%) 51 (0.781%) Bloc Size PRES FlipMin FNW Figure 4: Bit flip reduction over Differential Write with 4 auxiliary bits and different bloc sizes. The value in between the parenthesis represents space overhead. Bit Flip Reduc:on (=8 auxiliary Bits) 5% 0% 15% 10% 5% 0% 64 (1.5%) 18 (6.5%) 56 (3.15%) 51 (1.565%) 104 (0.781%) Bloc Size PRES FlipMin FNW Figure 5: Bit flip reduction over Differential Write with 8 auxiliary bits and different bloc sizes. The value in between the parenthesis represents space overhead. 5. Comparison of Coding Complexity In Table 1, we report the number of required operations to encode n-bit datawords and decode (n + ) bit codewords. While the encoding and decoding process of PRES is merely a series of simple XOR operation, Flip-Min necessitates a series of AND operations on top of the XOR operations. Furthermore, the overall required operations by Flip-Min are significantly more than PRES. For instance, PRES requires less than 10% of the overall required number of operations by Flip-Min to encode 64-bit data words with Base coset of 56 elements. Moreover, PRES requires less than 1.5% of the overall required number of operation by Flip-Min to decode the data. Although Flip-Min can flip as few bits as PRES, it comes at an excessively higher computational overhead than PRES. In comparison to FNW, more operations are required by PRES to encode/decode data. However, PRES significantly outperforms FNW in flip reduction capability as illustrated in Figures 4 and 5. Moreover, Table 1 reveals that PRES overhead is comparable to FNW for decoding. As for the encoding, the operations required by PRES are executed off the critical path and their incurred latency can be mased though buffering techniques. 5.3 Randomness Measurement Figures 4 and 5 showed that PRES outperforms both Flip- Min and FNW in bit flip reduction capability. We attribute those results to the fact that PRES generates a base coset with elements that are more random than the elements of the base cosets of Flip-Min and FNW. NIST SP 800- [0] are well nown tests to measure the randomness of data vectors. Each of the tests reports whether an input data vector is random or not. Accordingly, we have used those

6 Table 1: The number of operations used in PRES, FlipMin and FNW. Scheme PRES FlipMin FNW Operation XOR AND XOR AND XOR AND n-bit Input, n (n + ) 0 ( + 1) (n + ) (n + ) n+ 0 (n+)-bit Output Encoder n=3, = n=64, = n-bit Input, (n + ) 0 n (n + ) n (n + ) n+ 0 (n+)-bit Output Decoder n=3, = n=64, = tests to measure the randomness of the codewords produced by the encoders of PRES, Flip-Min and FNW. Our measurements reveal that the data vectors generated by PRES, FlipMin and FNW pass 98.94%, 95.61% and 88.67% of the tests, respectively. Those findings bac our rationale that the higher the randomness of the base coset elements the higher the rate of bit flip reduction that can be achieved. 6. CONCLUSION In this paper, we have showed that the effectiveness of coset based write minimization techniques is directly correlated with the randomness of the elements that form the base coset. We have proposed PRES as a new scheme to minimize the number of flipped bits to service write requests. PRES encoding is characterized by its capability to generate highly random coset elements. Our analyses and experimental results showed that pseudo-random codewords generated by PRES can lead to fewer bit flips than non-random codewords generated based on linear generator matrices while incurring low performance overhead. Overall, PRES represents a solid foundation to help overcome the challenges of emerging non-volatile memories, paving the way for their deployment in functional systems. References [1] H.-S. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, Phase change memory, Proceedings of the IEEE, vol. 98, no. 1, pp. 01 7, 010. [] E. Chen, D. Apalov, Z. Diao, A. Drisill-Smith, D. Druist, D. Lottis, V. Niitin, X. Tang, S. Watts, S. Wang et al., Advances and future prospects of spintransfer torque random access memory, Magnetics, IEEE Transactions on, vol. 46, no. 6, pp , 010. [3] M. Rasquinha, D. Choudhary, S. Chatterjee, S. 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