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1 INTERNAL ASSESSMENT TEST III Date : 21/11/2017 Max Marks : 40 Subject & Code : Computer Organization (15CS34) Semester : III (A & B) Name of the faculty: Mrs. Sharmila Banu Time : am 1.00 pm Answer any FIVE full questions, choosing one full question from each part Q.No Questions Marks Part-1 1 a List the different systems used to represent a signed number and give one example for each. Specify which number representation system is preferred in a computer and why? 4 NUMBER REPRESENTATION Numbers can be represented in 3 formats: 1) Sign and magnitude 2) 1's complement 3) 2's complement In sign-and-magnitude system, negative value is obtained by changing the MSB from 0 to 1 of the corresponding positive value. For ex, +5 is represented by 0101 & -5 is represented by In 1's complement system, negative values are obtained by complementing each bit of the corresponding positive number. For ex, -5 is obtained by complementing each bit in 0101 to yield (In other words, the operation of forming the 1's complement of a given number is equivalent to subtracting that number from 2n-1). In 2's complement system, forming the 2's complement of a number is done by subtracting that number from 2n. For ex, -5 is obtained by complementing each bit in 0101 & then adding 1 to yield (In other words, the 2's complement of a number is obtained by adding 1 to the 1's complement of that number). Two s complement is preferred in computer systems because Only one representation for 0 Sign extension The simplicity of adding or subtracting signed numbers in 2 s complement representation. b) Perform the following operations on the 5 bit signed numbers using 2 s complement representation system. Also indicate whether overflow has occurred. (i)(-12)+ (-13) (ii) (-10) - (+4) (2 s complement of 4) Overflow No overflow

2 Or 2 a Design a logic circuit to perform addition/subtraction of two n bit numbers X and Y. 4 Analysis: If Add/Sub control =1, then X + (1's complement of Y) +1 appears as the result. If Add/Sub control =0, then X+Y appears as the result. b) Differentiate between restoring and non-restoring division. 4 Each step of your division calculation the result of the step is either 1 or 0, depending if the dividend is less than or larger than the divisor. You generally do a test subtraction for each digit step; If the result is positive or zero, you note down a 1 as next digit of your quotient. If the result is negative, you proceed with one of two strategies: restoring method: you add the divisor back, and put 0 as your next quotient digit non-restoring method: you don t do that - you keep negative remainder and a digit 1, and basically correct things by a supplementary addition afterwards. Part-2 3 a Design 4 bit adder with carry look ahead logic and explain how it is faster than 4 bit ripple adder. 8 Carry-Look ahead Addition: A fast adder circuit must speed up the generation of the carry signals, it is necessary to make the carry input to each stage readily available along with the input bits. This can be achieved either by propagating the previous carry or by generating a carry depending on the input bits & previous carry. The logic expressions for S i (sum) and C i+1 (carry-out) of stage ith are 2

3 c i +1 = G i + P i c i c i = G i 1 + P i 1 c i 1 c i+1 = G i + P i (G i 1 + P i 1 c i 1 ) continuing c i+1 = G i + P i (G i 1 + P i 1 (G i 2 + P i 2 c i 2 )) until c i+1 = G i + P i G i 1 + P i P i 1 G i P i P i 1..P 1 G 0 + P i P i 1...P 0 c 0 All carries can be obtained 3 gate delays after X, Y and c 0 are applied. -One gate delay for P i and G i -Two gate delays in the AND-OR circuit for c i+1 All sums can be obtained 1 gate delay after the carries are computed. Independent of n, n-bit addition requires only 4 gate delays. This is called Carry Lookahead adder. For 4-bit ripple-carry adder, the equations to obtain four carry signals are: C 1 = G 0 + P 0.C 0 C 2 = G 1 + P 1.G 0 +P 1 P 0 Co C 3 = G 2 + P 2.G 1 +P 2 P 1 G 0 +P 2 P 1 P 0 Co C 4 = G 3 + P 3.G 2 + P 3 P 2 G 1 +P 3 P 2 P 1 G 0 +P 3 P 2 P 1 P 0 C 0

4 The carries are implemented in the block labeled carry-lookahead logic. An adder implemented in this form is called a carry-lookahead adder. Delay is 3 gate delay for all carry bits 4 gate delay for all sum bits. 4 bit ripple carry adder requires 7 gate delay for s3 and 8 gate delay for c4. For an n-bit ripple carry adder, s n-1 is available after 2n-1 gate delays c n is available after 2n gate delays. 4 a Explain Booth s Algorithm. Perform signed multiplication of number (-12) and (-11) using Booth's algorithm. 8 The Booth algorithm generates a 2n-bit product and both positive and negative 2's-complement n-bit operands are uniformly treated. To explain this algorithm, consider a multiplication operation in which the multiplier is positive and has a single block of 1s, for example, (+30). To derive the product, as in the normal standard procedure, we could add four appropriately shifted versions of the multiplicand. However, using the Booth algorithm, we can reduce the number of required operations by regarding this multiplier as the difference between numbers 32 & 2 as shown below For convenience, we can describe the sequence of required operations by recoding the preceding multiplier as In general, in the Booth scheme, -1 times the shifted multiplicand is selected when moving from 0 to 1, and +1 times the shifted multiplicand is selected when moving from 1 to 0, as the multiplier is scanned from right to left. Multiplier Recording Table Part-3 5 a Explain IEEE standard for floating point number. 4 IEEE Floating Point notation is the standard representation in use. There are two representations: - Single precision. - Double precision. Both have an implied base of 2. 2

5 Floating point numbers have to be represented in a normalized form to maximize the use of available mantissa digits. In a base-2 representation, this implies that the MSB of the mantissa is always equal to 1. If every number is normalized, then the MSB of the mantissa is always 1. We can do away without storing the MSB. IEEE notation assumes that all numbers are normalized so that the MSB of the mantissa is a 1 and does not store this bit. So the real MSB of a number in the IEEE notation is either a 0 or a 1. The values of the numbers represented in the IEEE single precision notation are of the form: (E- 127) (+,-) 1.M x 2 b) What is the use of guard bits in floating point operations? List the methods to truncate those bits? 4 While adding two floating point numbers with 24-bit mantissas, we Shift the mantissa of the number with the smaller exponent to the right Until the two exponents are equalized. This implies that mantissa bits may be lost during the right shift (that is, bits of precision may be shifted out of the mantissa being shifted). To prevent this, floating point operations are implemented by keeping guard bits, that is, extra bits of precision at the least significant end of the mantissa. The arithmetic on the mantissas is performed with these extra bits of precision. After an arithmetic operation, the guarded mantissas are: - Normalized (if necessary) - Converted back by a process called truncation/rounding to a 24-bit mantissa. Straight chopping: The guard bits (excess bits of precision) are dropped. 0.b -1 b -2 b to 0.b -1 b -2 b are truncated to 0.b -1 b -2 b -3. Von Neumann rounding: If the guard bits are all 0, they are dropped.

6 However, if any bit of the guard bit is a 1, then the LSB of the retained bit is set to 1. If b -4 b -5 b -6 is not equal to 000 are truncated to 0.b -1 b -2 1 Rounding: If there is a 1 in the MSB of the guard bit then a 1 is added to the LSB of the retained bits. 0.b -1 b -2 b -3 1 is rounded to 0.b -1 b -2 b and 0.b -1 b -2 b Is rounded to 0.b -1 b -2 b a Explain the circuit arrangements for binary division. Given A=10101 and B=00100 perform A/B using restoring division algorithm An n-bit positive-divisor is loaded into register M. An n-bit positive-dividend is loaded into register Q at the start of the operation. Register A is set to 0 (Figure 9.21). After division operation, the n-bit quotient is in register Q, and the remainder is in register A. 8 Restoring Division Shift A and Q left one binary position Subtract M from A, and place the answer back in A If the sign of A is 1, set q 0 to 0 and add M back to A (restore A); otherwise, set q 0 to 1 Repeat these steps n times Remainder Quotient

7 Part-4 7 a List out the actions needed to execute the instruction ADD (R3), R1. Write and explain the sequence of control steps for the execution of the same. Add (R3), R1 Fetch the instruction Fetch the first operand (the contents of the memory location pointed to by R3) Perform the addition Load the result into R1 Step Action 8 1 PC out, MAR in, Read, Select4,Add, Z in 2 Z out, PC in, Y in, WMF C 3 MDR out, IR in 4 R3 out, MAR in, Read 5 R1 out, Y in, WMF C 6 MDR out, SelectY, Add, Z in 7 Z out, R1 in, End Figure 7.6. Control sequencefor execution of the instruction Add (R3),R1. Instruction execution proceeds as follows: Step1--> The instruction-fetch operation is initiated by loading contents of PC into MAR & sending a Read request to memory. The Select signal is set to Select4, which causes the Mux to select constant 4. This value is added to operand at input B (PC s content), and the result is stored in Z. Step2--> Updated value in Z is moved to PC. This completes the PC increment operation and PC will now point to next instruction. Step3--> Fetched instruction is moved into MDR and then to IR. The step 1 through 3 constitutes the Fetch Phase. At the beginning of step 4, the instruction decoder interprets the contents of the IR. This enables the control circuitry to activate the control-signals for steps 4 through 7. The step 4 through 7 constitutes the Execution Phase. Step4--> Contents of R3 are loaded into MAR & a memory read signal is issued. Step5--> Contents of R1 are transferred to Y to prepare for addition. Step6--> When Read operation is completed, memory-operand is available in MDR, and the addition is performed. Step7--> Sum is stored in Z, then transferred to R1.The End signal causes a new instruction fetch cycle to begin by returning to step1.

8 8 a With a neat block diagram, explain hardwired control unit. Show the generation of Zin and END control signals. 8 HARDWIRED CONTROL Hardwired control is a method of control unit design (Figure 7.11). The control-signals are generated by using logic circuits such as gates, flip-flops, decoders etc. Decoder/Encoder Block is a combinational-circuit that generates required control-outputs depending on state of all its inputs. Instruction Decoder It decodes the instruction loaded in the IR. If IR is an 8 bit register, then instruction decoder generates 28(256 lines); one for each instruction. It consists of a separate output-lines INS1 through INSm for each machine instruction. According to code in the IR, one of the output-lines INS1 through INSm is set to 1, and all other lines are set to 0. Step-Decoder provides a separate signal line for each step in the control sequence. Encoder It gets the input from instruction decoder, step decoder, external inputs and condition codes. It uses all these inputs to generate individual control-signals: Yin, PCout, Add, End and so on. For example (Figure 7.12), Zin=T1+T6.ADD+T4.BR This signal is asserted during time-slot T1 for all instructions. during T6 for an Add instruction. during T4 for unconditional branch instruction When RUN=1, counter is incremented by 1 at the end of every clock cycle. When RUN=0, counter stops counting. After execution of each instruction, end signal is generated. End signal resets step counter. Sequence of operations carried out by this machine is determined by wiring of logic circuits, hence the name hardwired. Advantage: Can operate at high speed. Disadvantages: 1) Since no. of instructions/control-lines is often in hundreds, the complexity of control unit is very high. 2) It is costly and difficult to design. 3) The control unit is inflexible because it is difficult to change the design. Clock CLK Control step counter Reset Step decoder T 1 T 2 T n IR Instruction decoder INS 1 INS 2 INS m Encoder External inputs Condition codes Run End Control signals Figure Separation of the decoding and encoding functions. Z in = T 1 + T 6 ADD + T 4 BR + 2

9 End = T 7 ADD + T 5 BR + (T 5 N + T 4 N) BRN + Add N Branch<0 N Branch T 7 T 5 T 4 T 5 End Figure Generation of the End control signal. Part- 5 9 a With a neat sketch, explain the organisation of a micro programmed control unit. 8 MICROPROGRAMMED CONTROL Microprogramming is a method of control unit design (Figure 7.16). Control-signals are generated by a program similar to machine language programs. Control Word(CW) is a word whose individual bits represent various control-signals (like Add, PCin). Each of the control-steps in control sequence of an instruction defines a unique combination of 1s & 0s in CW. Individual control-words in microroutine are referred to as microinstructions (Figure 7.15). A sequence of CWs corresponding to control-sequence of a machine instruction constitutes the microroutine. The microroutines for all instructions in the instruction-set of a computer are stored in a special memory called the Control Store (CS). Control-unit generates control-signals for any instruction by sequentially reading CWs of corresponding microroutine from CS. µpc is used to read CWs sequentially from CS. (µpc Microprogram Counter). Every time new instruction is loaded into IR, o/p of Starting Address Generator is loaded into µpc.

10 Then, µpc is automatically incremented by clock; causing successive microinstructions to be read from CS. Hence, control-signals are delivered to various parts of processor in correct sequence. Advantages It simplifies the design of control unit. Thus it is both, cheaper and less error prone implement. Control functions are implemented in software rather than hardware. The design process is orderly and systematic. More flexible, can be changed to accommodate new system specifications or to correct the design errors quickly and cheaply. Complex function such as floating point arithmetic can be realized efficiently. Disadvantages A microprogrammed control unit is somewhat slower than the hardwired control unit, because time is required to access the microinstructions from CM. The flexibility is achieved at some extra hardware cost due to the control memory and its access circuitry. Drawback of previous Microprogram control: It cannot handle the situation when the control unit is required to check the status of the condition codes or external inputs to choose between alternative courses of action. Solution: Use conditional branch microinstruction. In case of conditional branching, microinstructions specify which of the external inputs, conditioncodes should be checked as a condition for branching to take place. 2

11 10 a Write down the control sequence for the instruction ADD R4, R5, R6 for three bus organisation. 4 b) What is Bit-ORing? How it is used in microroutines? Give example. 4 The branch address is determined by ORing particular bit or bits with the current address of microinstruction. Eg: If the current address is 170 and branch address is 171 then the branch address can be generated by ORing 01(bit 1), with the current address. When it is necessary to choose between direct and indirect addressing modes. If indirect-mode is specified in the instruction, then the microinstruction in location 170 is performed to fetch the operand from the memory. If direct-mode is specified, this fetch must be bypassed by branching immediately to location 171. The most efficient way to bypass microinstruction 170 is to have bit-oring of current address 170 & branch address 171.

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