# COMBINATIONAL LOGIC CIRCUITS

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1 COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic gates, where outputs are at any instant and are determined only by the present combination of inputs without regard to previous inputs or previous state of outputs. A combinational circuit performs a specific information-processing operation assigned logically by a set of Boolean functions. Sequential circuits contain logic gates as well as memory cells. Their outputs depend on the present inputs and also on the states of memory elements. Since the outputs of sequential circuits depend not only on the present inputs but also on past inputs, the circuit behavior must be specified by a time sequence of inputs and memory states. A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept signals from inputs and output signals are generated according to the logic circuits employed in it. Binary information from the given data transforms to desired output data in this process. Both input and output are obviously the binary signals, i.e., both the input and output signals are of two possible states, logic 1 and logic 0. Figure 4.1 shows a block diagram of a combinational logic circuit. There are n number of input variables coming from an electric source and m number of output signals go to an external destination. The source and/or destination may consist of memory elements or sequential logic circuit or shift registers, located either in the vicinity of the combinational logic circuit or in a remote external location. But the external circuit does not interfere in the behavior of the combinational circuit. Figure (4-1) 1

3 Figure (4-2) From the truth table in Figure 4.2, it can be seen that the outputs S and C functions are similar to Exclusive-OR and AND functions respectively, as shown in Figure 4.3 in Chapter 3. The Boolean expressions are S = A B+AB and C = AB. Figure 4.3 shows the logic diagram to implement the half-adder circuit. Figure (4-3) Design of Full-adders A combinational circuit of full-adder performs the operation of addition of three bits the augend, addend, and previous carry, and produces the outputs sum and carry. Let us designate the input variables augend as A, addend as B, and previous carry as X, and outputs sum as S and carry as C. As there are three input variables, eight different input combinations are possible. The truth table is shown in Figure 4.4 according to its functions. 3

4 Figure (4-4) To derive the simplified Boolean expression from the truth table, the Karnaugh map method is adopted as in Figures 4.5(a)-(b). Figure 4.5(a) Map for function S. Figure 4.5(b) Map for function C. The simplified Boolean expressions of the outputs are S = X A B + X AB + XA B + XAB and C = AB + BX + AX. The logic diagram for the above functions is shown in Figure 4.6. It is assumed complements of X, A, and B are available at the input source. Note that one type of configuration of the combinational circuit diagram for full-adder is realized in Figure 4.6, with two-input and three-input AND gates, and three input and four-input OR gates. Other configurations can also be developed where number and type of gates are reduced. For this, the Boolean expressions of S and C are modified as follow. Figure (4-6) 4

5 S = X A B + X AB + XA B + XAB = X (A B + AB ) + X (A B + AB) = X (A B) + X (A B) = X A B C = AB + BX + AX = AB + X (A + B) = AB + X (AB + AB + AB + A B) = AB + X (AB + AB + A B) = AB + XAB + X (AB + A B) = AB + X (A B) Logic diagram according to the modified expression is shown Figure 4.7. Figure (4-7) You may notice that the full-adder developed in Figure 4.7 consists of two 2-input AND gates, two 2-input XOR (Exclusive-OR) gates and one 2-input OR gate. This contains a reduced number of gates as well as type of gates as compared to Figure 4.6. Also, if compared with a half-adder circuit, the full-adder circuit can be formed with two half-adders and one OR gate. 4.4 SUBTRACTORS Subtraction is the other basic function of arithmetic operations of informationprocessing tasks of digital computers. Similar to the addition function, subtraction of two binary digits consists of four possible elementary operations, which are 0 0 = 0, 0 1 = 1 with borrow of 1, 1 0 = 1, and 1 1 = 0. The first, third, and fourth operations produce a subtraction of one digit, but the second operation produces a difference bit as well as a borrow bit. The borrow bit is used for subtraction of the next higher significant bit. A combinational circuit that performs the subtraction of two bits as described above is called a half-subtractor. The digit from which another digit is subtracted is called the minuend and the digit which is to be subtracted is called the subtrahend. When the minuend and subtrahend numbers contain more significant 5

6 digits, the borrow obtained from the subtraction of two bits is subtracted from the next higher-order pair of significant bits. Here the subtraction operation involves three bits the minuend bit, subtrahend bit, and the borrow bit, and produces a different result as well as a borrow. The combinational circuit that performs this type of addition operation is called a full-subtractor. Similar to an adder circuit, a fullsubtractor combinational circuit can be developed by using two half-subtractors Design of Half-subtractors A half-subtractor has two inputs and two outputs. Let the input variables minuend and subtrahend be designated as X and Y respectively, and output functions be designated as D for difference and B for borrow. The truth table of the functions is as follows. Figure (4-8) By considering the minterms of the truth table in Figure 4.8, the Boolean expressions of the outputs D and B functions can be written as D = X Y + XY and B = X Y. Figure 4.9 shows the logic diagram to realize the half-subtractor circuit. Figure (4-9) 6

7 4.4.2 Design of Full-subtractors A combinational circuit of full-subtractor performs the operation of subtraction of three bits the minuend, subtrahend, and borrow generated from the subtraction operation of previous significant digits and produces the outputs difference and borrow. Let us designate the input variables minuend as X, subtrahend as Y, and previous borrow as Z, and outputs difference as D and borrow as B. Eight different input combinations are possible for three input variables. The truth table is shown in Figure 4.10(a) according to its functions. Figure 4-10 (a) Figure 4.10(b) Map for function D. Figure 4.10(b) Map for function B. Karnaugh maps are prepared to derive simplified Boolean expressions of D and B as in Figures 4.10(b) and 4.10(c), respectively. The simplified Boolean expressions of the outputs are D = X Y Z + X YZ + XY Z + XYZ and B = X Z + X Y + YZ. The logic diagram for the above functions is shown in Figure Similar to a full-adder circuit, it should be noticed that the configuration of the combinational circuit diagram for full-subtractor as shown in Figure 4.11 contains two-input and three-input AND gates, and three-input and four-input OR gates. Other 7

8 configurations can also be developed where number and type of gates are reduced. For this, the Boolean expressions of D and B are modified as follows. Figure 4-11 D = X Y Z + X YZ + XY Z + XYZ = X (Y Z + YZ ) + X (Y Z + YZ) = X (Y Z) + X (Y Z) = X Y Z B = X Z + X Y +YZ = X Y + Z (X + Y) = X Y + Z(X Y + X Y + XY + X Y) = X Y + Z(X Y + X Y + XY) = X Y + X YZ + Z(X Y + XY) = X Y + Z(X Y) Logic diagram according to the modified expression is shown in Figure Figure 4-12 Note that the full-subtractor developed in Figure 4.12 consists of two 2-input AND gates, two 2-input XOR (Exclusive-OR) gates, two INVERTER gates, and one 2- input OR gate. This contains a reduced number of gates as well as type of gates as compared to Figure Also, it may be observed, if compared with a half-subtractor circuit, the full-subtractor circuit can be developed with two half-subtractors and one OR gate. 8

9 Programmable Logic Devices 5.1 Decoders In a digital system, discrete quantities of information are represented with binary codes. A binary code of n bits can represent up to 2n distinct elements of the coded information. A decoder is a combinational circuit that converts n bits of binary information of input lines to a maximum of 2n unique output lines. Usually decoders are designated as an n to m lines decoder, where n is the number of input lines and m (=2n) is the number of output lines. Decoders have a wide variety of applications in digital systems such as data demultiplexing, digital display, digital to analog converting, memory addressing, etc. A 3-to-8 line decoder is illustrated in Figure 5.1. Figure (5.1) Figure (5.2) 1

10 The 3-to-8 line decoder consists of three input variables and eight output lines. Note that each of the output lines represents one of the minterms generated from three variables. The internal combinational circuit is realized with the help of INVERTER gates and AND gates. The operation of the decoder circuit may be further illustrated from the input output relationship as given in the table in Figure 5.2. Note that the output variables are mutually exclusive to each other, as only one output is possible to be logic 1 at any one time Some Applications of Decoders As we have seen that decoders give multiple outputs equivalent to the minterms corresponding to the input variables, it is obvious that any Boolean expression in the sum of the products form can be very easily implemented with the help of decoders. It is not necessary to obtain the minimized expression through simplifying procedures like a Karnaugh map, or tabulation method, or any other procedure. It is sufficient to inspect the minterm contents of a function from the truth table, or the canonical form of sum of the products of a Boolean expression and selected minterms obtained from the output lines of a decoder may be simply OR-gated to derive the required function. The following examples will demonstrate this. Example 5.1. Implement the function F (A,B,C) = Σ (1,3,5,6). Solution. Since the above function has three input variables, a 3-to-8 line decoder may be employed. It is in the sum of the products of the minterms m1, m3, m5, and m6, and so decoder output D1, D3, D5, and D6 may be OR-gated to achieve the desired function. The combinational circuit of the above functions is shown in Figure 5.3. Figure (5.3) 2

11 Example 5.2. Design a full adder circuit with decoder IC. Solution. We have seen earlier that full adder circuits are implemented with logic gates. This can be very easily implemented with the help of a decoder IC. If we observe the truth table of a full adder. In respect to minterms, the Boolean expression of sum output S and carry output C can be written as: S = X A B + X AB + XA B + XAB and C = X AB + XA B + XAB + XAB. The above expression can be realized in Figure 5.4. Figure (5.4) 5.2 ENCODERS An encoder is a combinational network that performs the reverse operation of the decoder. An encoder has 2 n or less numbers of inputs and n output lines. The output lines of an encoder generate the binary code for the 2 n input variables. Figure 5.5 illustrates an eight inputs/three outputs encoder. It may also be referred to as an octalto-binary encoder where binary codes are generated at outputs according to the input conditions. The truth table is given in Figure 5.6. Figure (5.5) 3

12 Figure (5.6) The encoder in Figure 5.5 assumes that only one input line is activated to logic 1 at any particular time, otherwise the other circuit has no meaning. It may be noted that for eight inputs there are a possible 2 8 = 256 combinations, but only eight input combinations are useful and the rest are don t-care conditions. It may also be noted that D 0 input is not connected to any of the gates. All the binary outputs A, B, and C must be all 0s in this case. All 0s output may also be obtained if all input variables D 0 to D 7 are logic 0. This is the main discrepancy of this circuit. This discrepancy can be eliminated by introducing another output indicating the fact that all the inputs are not logic 0. However, this type of encoder is not available in an IC package because it is not easy to implement with OR gates and not much of the gates are used. The type of encoder available in IC package is called a priority encoder. These encoders establish an input priority to ensure that only highest priority input is encoded. As an example, if both D 2 and D 4 inputs are logic 1 simultaneously, then output will be according to D 4 only i.e., output is MULTIPLEXERS OR DATA SELECTORS A multiplexer is one of the important combinational circuits and has a wide range of applications. The term multiplex means many into one. Multiplexers transmit large numbers of information channels to a smaller number of channels. A digital multiplexer is a combinational circuit that selects binary information from one of the many input channels and transmits to a single output line. That is why the multiplxers are also called data selectors. The selection of the particular input channel is controlled by a set of select inputs. 4

13 A digital multiplexer of 2n input channels can be controlled by n numbers of select lines and an input line is selected according to the bit combinations of select lines. Figure (5.7) A 4-to-1 line multiplexer is defined as the multiplexer consisting of four input channels and information of one of the channels can be selected and transmitted to an output line according to the select inputs combinations. Selection of one of the four input channels is possible by two selection inputs. Figure 5.7 illustrates the truth table. Input channels I 0, I 1, I 2, and I 3 are selected by the combinations of select inputs S 1 and S 0. The circuit diagram is shown in Figure 5.8. To demonstrate the operation, let us consider that select input combination S 1 S 0 is 01. The AND gate associated with I 1 will have two of inputs equal to logic 1 and a third input is connected to I 1. Therefore, output of this AND gate is according to the information provided by channel I 1. The other three AND gates have logic 0 to at least one of their inputs which makes their outputs to logic 0. Hence, OR output (Y) is equal to the data provided by the channel I 1. Thus, information from I 1 is available at Y. Normally a multiplexer has an ENABLE input to also control its operation. The ENABLE input (also called STROBE) is useful to expand two or more multiplexer ICs to a digital multiplexer with a larger number of inputs. A multiplexer is often abbreviated as MUX. Its block diagram is shown in Figure

14 Figure (5.8) Figure (5.9) 6

15 BCD Code or 8421 Code The full form of BCD is Binary-Coded Decimal. Since this is a coding scheme relating decimal and binary numbers, four bits are required to code each decimal number. For example, (35) 10 is represented as using BCD code, rather than (100011) 2. From the example it is clear that it requires more number of bits to code a decimal number using BCD code than using the straight binary code. However, inspite of this disadvantage it is convenient to use BCD code for input and output operations in digital systems. The code is also known as code. This is because 8, 4, 2, and 1 are the weights of the four bits of the BCD code. The weight of the LSB is 2 0 or 1, that of the next higher order bit is 2 1 or 2, that of the next higher order bit is 2 2 or 4, and that of the MSB is 2 3 or 8. Therefore, this is a weighted code and arithmetic operations can be performed using this code, which will be discussed later on. The bit assignment 0101, for example, can be interpreted by the weights to represent the decimal digit 5 because = 5. Since four binary bits are used the maximum decimal equivalent that may be coded is (i.e., ). But the maximum decimal digit available is Hence the binary codes 1010, 1011, 1100, 1101, 1110, 1111, representing 10, 11, 12, 13, 14, and 15 in decimal are never being used in BCD code. So these six codes are called forbidden codes and the group of these codes is called the forbidden group in BCD code. BCD code for decimal digits 0 to 9 is shown in the following table. 1

16 Example 1. Give the BCD equivalent for the decimal number 589. Solution. The decimal number is BCD code is Hence, (589) 10 = ( ) BCD Example 2. Give the BCD equivalent for the decimal number Solution. The decimal number BCD code is Hence, (69.27) 10 = ( ) BCD 2

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