CS 265. Computer Architecture. Wei Lu, Ph.D., P.Eng.

Transcription

1 CS 265 Computer Architecture Wei Lu, Ph.D., P.Eng.

2 Part 4: Memory Organization Our goal: understand the basic types of memory in computer understand memory hierarchy and the general process to access memory know how memory is organized to store data understand cache memory and virtual memory

3 Part 4: Memory Organization Overview: Introduction to memory Memory hierarchy and how computer access memory How memory is organized to store data and program Two memory technologies - Cache memory - Virtual memory

4 Introduction to Memory Volatile or nonvolatile Random or sequential access Read-write or read-only

5 Memory Volatility Volatile memory Contents disappear when power is removed Least expensive Nonvolatile memory Contents remain without power More expensive than volatile memory May have slower access times

6 Memory Access Random access Typical memory used by personal computer Sequential access Special purpose memory Hardware known as FIFO (First-In-First-Out)

7 Read-Only Memory ROM (Read Only Memory) Values can be read, but not changed, e.g. firmware PROM (Programmable Read Only Memory) Contents can be altered, but doing so is time-consuming EEPROM (Electrically Erasable Programmable Read Only Memory), a.k.a E2PROM Form of PROM that can be changed while installed

8 Read-write Memory: Random Access Memory Main memory (a.k.a. RAM): dynamic RAM (DRAM) and static RAM (SRAM). Dynamic RAM consists of capacitors that slowly leak their charge over time. Thus they must be refreshed every few milliseconds to prevent data loss. SRAM is very fast memory and it doesn t need to be refreshed like DRAM does. It is used to build cache memory, which we will discuss soon.

9 Random Access Memory: SRAM When enable is high, output is same as input Otherwise, output holds last value high speed; but power consumption and heat is high as well

10 Random Access Memory: DRAM Alternative to SRAM; consumes less power and acts like a capacitor Capacitor gradually loses charge (i.e. logical 1 changes to logical 0) Extra hardware known as refresh circuit needed to repeatedly read value from location in DRAM and Write value back into same location

11 Memory Hierarchy Motivation Process to access memory hierarchy Terminology on memory hierarchy

12 Motivation of Memory Hierarchy Key concept to memory designer Generally speaking, faster memory is more expensive than slower memory. To provide the best performance at the lowest cost, memory is organized in a hierarchical fashion. Small, fast storage elements are kept in the CPU, larger, slower main memory is accessed through the data bus. Larger, (almost) permanent storage in the form of disk.

13 Dozens of general-purpose registers Megabytes of main memory Gigabytes of secondary storage Memory Hierarchy

14 Access to Memory Hierarchy To access a particular piece of data, the CPU first sends a request to its nearest memory, usually cache. If the data is not in cache, then main memory is queried. If the data is not in main memory, then the request goes to disk. Once the data is located, then the data, and a number of its nearby data elements are fetched into cache memory.

15 Terminology on Memory Hierarchy A hit is when data is found at a given memory level. A miss is when it is not found. The hit rate is the percentage of time data is found at a given memory level. The miss rate is the percentage of time it is not. Miss rate = 1 - hit rate. The hit time is the time required to access data at a given memory level. The miss penalty is the time required to process a miss, including the time that it takes to replace a block of memory plus the time it takes to deliver the data to the processor.

16 Memory Organization Memory Bus Physical Memory Address and Address Space How Data and Program Stored in Memory

17 Memory Bus Parallel interface used between computer and memory, called a bus Memory Bus determines amount of memory to be transferred simultaneously Example memory bus sizes: 16 bits; 32 bits or 64 bits Important to programmers!

18 Physical Memory Address Physical memory consists of a linear array of addressable storage cells that includes N bits each Terminology Group of N bits is called a word (N>8) N is known as the width of a word or the word size and is always a power of 2 and at least 16bits Each word (or byte) of memory is assigned a unique number known as a physical memory address Physical memory address can be byte-addressable, or wordaddressable, where a word typically consists of two or more bytes.

19 Byte memory addressing: an example Physical address bit 1 2 byte1 byte2 2 N... 2 N -1 One byte 19

20 This is a problem encountered by programmers Refers to integer storage in memory Byte Alignment An integer value is aligned if the bytes of the integer corresponds to a word in the underlying physical memory. In this example : An integer composed of Bytes 12, 13, 14, 15 are aligned An integer composed of Bytes 6, 7, 8, and 9 are not aligned.

21 Byte Alignment to Programmers The organization of physical memory affects programming: even if a processor allows unaligned memory access, aligning data on boundaries that correspond to the physical word size can improve program performance.

22 Memory Size and Address Space Memory size dictates address scheme Size of address limits maximum memory Example: 32-bit address can represent unique addresses, which is known as address space

23 Memory Size and Address Space Memory is constructed of RAM chips, often referred to in terms of length width If the memory word size of the machine is 16 bits, then a 4M 16 RAM chip gives us 4 megabytes of 16-bit memory locations We observe that 4M can be expressed as = 2 22 words. The memory locations for this memory are numbered 0 through Thus, the memory bus of this system requires at least 22 address lines. The address lines count from 0 to in binary. Each line is either on or off indicating the location of the desired memory element.

24 Memory Dump Printable representation of bytes in memory and show how the program is stored in the memory Each line of output specifies memory address and bytes starting at that address Examples

25 Thank you for your attendance Any questions?