II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.

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1 Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic Design Maximum : 60 Marks (1X12 = 12 Marks) Answer ONE question from each unit. (4X12=48 Marks) 1. Answer all questions (1X12=12 Marks) a) What are the basic operations in Boolean Algebra? b) Convert the decimal number 76 into the binary number c) State Demorgan s Laws? d) Mention disadvantages of K-map e) Differentiate between a latch and a Flip Flop f) Which gate is called an all or nothing gate? Why? g) What is a literal? h) What is a code convertor? i) What are different types of RAM? j) What is race around condition? k) What is a counter? Mention different types of counters. l) What is meant by PLA? UNIT I 2. a) Convert the decimal number to base 3, base 7, base 8and base 16. b) Reduce the following expression to the simplest possible POS and SOP forms f=σm(6,9,13,18,19,25,27,29,31)+d(2,3,11,15,17,24,28) (OR) 3. a) Find the sum of the products expression using K-map for the function F = Σm(7, 9, 10, 11, 12, 13, 14, 15) 8M b) Reduce the following expressions using a Four-variable K-map ABC + A BCD + ABC D + ABC 4M UNIT II 4. a) Implement Full-Subtractor using two Half- Subtractors and OR Gate. b) Explain in detail about 4-bit magnitude comparator? (OR) 5. a) Obtain the set of prime implicants for the Boolean expression f=σm(0,1,6,7,8,9,13,14,15) using the tabular method? b) Explain and Design Half Adder and Full Adder? UNIT III 6. a) What is race around condition? How is it eliminated? Explain with neat diagram 8M b) Draw the circuit of D-Flip flop and explain its operation along with Truth Table. 4M (OR) 7. a) Draw the logical diagram (showing all gates) of a Master-Slave D Flip Flop. Use NAND gates. b) With a neat diagram explain the working of SR-flip flop with characteristic table, excitation table and characteristic equation UNIT IV 8. a) Design a 4-bit up/down ripple counter using J-K Flip- Flops. b) Explain the working of bi-directional shift register with a neat diagram (OR) 9. Write in detail about PROM, PLA and PAL 1 1

2 2 14CS IT303

3 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. Answer ONE question from each unit. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Scheme of Evaluation & Solutions 14CS IT303 Common for CSE & IT Digital Logic Design Maximum : 60 Marks (1X12 = 12 Marks) (4X12=48 Marks) Answer all questions (1X12=12 Marks) a) What are the basic operations in Boolean Algebra? The Basic operations in Boolean Algebra are Logical AND, OR and NOT operations. b) Convert the decimal number 76 into the binary number c) State Demorgan s Laws? d) Mention disadvantages of K-map The disadvantage of k map : It is not suitable for computer reduction. It is not suitable when the number of variables involved exceed four. Care must be taken to field in every cell with the relevant entry, such as a 0, 1 (or) don't care terms. e) Differentiate between a latch and a Flip Flop. Latch and Flip Flop both are capable to store one bit of binary data, but the difference is that latch doesn t accept clock pulse, but Flip Flop accept clock pulse. f) Which gate is called an all or nothing gate? Why? Ex- Nor gate is called all or nothing gate, why because if both inputs are 1 or both are 0 it out puts 1 otherwise 0. g) What is a literal? A literal is a primed or un primed form of a variable. Or True form or complement form of a variable. Ex: x, x, y, y... h) What is a code convertor? A Code convertor is a Combinational Logic Circuit, Which converts a code from one form to another form. Ex: a) BCD 8421 to Ex-3 Code convertor b) BCD 8421 to 2421 code convertor and etc. i) What are different types of RAM? SRAM: Static RAM DRAM: Dynamic RAM. j) What is race around condition? In JK flip-flop output is fed back to the input. Therefore change in the output results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called race around condition. [Any relevant answer award one mark] 3

4 k) What is a counter? Mention different types of counters. A Counter is a sequential logic circuit, which counts the number of occurrences of an event based on clock pulses. The following are different type of counters. Asynchronous (ripple) counters Synchronous counters Johnson counters Decade counters Up-Down counters Ring counters [Note: Listing any two counter types award full marks.] l) What is meant by PLA? PLA: Programmable Logic Array. Definition: PLA is programmable logic device, which is used to build reconfigurable logic circuits. And PLAs contained a two level structure of AND and OR gates with user programmable connections. UNIT I 2. a) Convert the decimal number to base 3, base 7, base 8 and base 16. [For each conversion 1.5 Marks] i) to base / 3 = 83 rem > 1 we're diving by three (our target base) and then keeping the remainder as our result and then repeat the process with the remaining number. 83 / 3 = 27 rem > 2 27 / 3 = 9 rem > 0 9 / 3 = 3 rem > 0 3 / 3 = 1 rem > 0 1 / 3 = 0 rem > 1 1.5M Now convert 0.5: 0.5 * 3 = >1 0.5 * 3 = > * 3 = > 1 this one goes on indefinitely! Both lists of digits start at the radix/decimal point and move away, the integer part to the left and the fraction part to the right. So the answer is: (250.5) 10 = ( ) 3 ii) to base / 7 = 35 rem / 7 = 5 rem / 7 = 0 rem M 0.5 * 7 = * 7 = * 7 = answer is: (250.5) 10 = ( ) 7 iii) to base / 8 = 31 rem / 8 = 3 rem / 8 = 0 rem * 8 = answer is: (250.5) 10 = ( 372.4) 8 1.5M 4

iv) 250.5 to base 16 250 / 16 = 15 rem 10...A 15 / 16 = 0 rem 15...F 14CS IT303 1.5M 0.

8)16 b) Reduce the following expression to the simplest possible POS and SOP forms

5 iv) to base / 16 = 15 rem 10...A 15 / 16 = 0 rem 15...F 14CS IT M 0.5 * 16 = answer is: (250.5)10 = (FA.8)16 b) Reduce the following expression to the simplest possible POS and SOP forms f=σm(6,9,13,18,19,25,27,29,31)+d(2,3,11,15,17,24,28) [5v K-Map Structure, SOP form, POS form ] For Simplified SOP: F = xw + v x y z For Simplified POS: F= (z + w). (x + z). (x + z + w). (v + x + w ). (v + x + y ) 5

14, 15) [4 variable k-map structure-, Filling-, Grouping-, Simplifies expression ] Given expression

. 8M 4M Simplifies SOP is: F= wx + wy + wz + xyz b) Reduce the following expressions using a

6 (OR) 3. a) Find the sum of the products expression using K-map for the function F = Σm(7, 9, 10, 11, 12, 13, 14, 15) [4 variable k-map structure-, Filling-, Grouping-, Simplifies expression ] Given expression contains 4 variables, therefore 4v k map is required for simplification. 4 Variable K map.. 8M 4M Simplifies SOP is: F= wx + wy + wz + xyz b) Reduce the following expressions using a Four-variable K-map ABC + A BCD + ABC D + ABC [expression expansion, K map-, Grouping-, Simplified expression ] 4M Given expression contains 4 variables, therefore 4v k map is required for simplification. 4 Variable K map.. 6

borrowed by a lower significant bit. The circuit has three inputs and two outputs.

7 Simplifies SOP is: F = AC + ABD + BCD UNIT II 4. a) Implement Full-Subtractor using two Half- Subtractors and OR Gate. [Behaviour & Truth table, Expressions -, Logic circuit -] A full subtractor is a combinational circuit that performs a subtraction between two bits, taking into account that a 1 may have been borrowed by a lower significant bit. The circuit has three inputs and two outputs. Input variables are minuend (X), subtrahend (Y), and previous borrow (Z); output variables are difference (D) and output borrow (B). It performs the operation X Y Z. It should be noted that the weight of the output borrow bit is -2, while the weight of the output difference bit is +1. The truth table of the full subtractor is The simplified Boolean functions for the two outputs are: The Logic diagram for Full subtractor using two half suntractors is: 7

8 b) Explain in detail about 4-bit magnitude comparator? [Definitiona-, For each Boolean expression, logic circuit- ] A magnitude comparator is a combinational circuit that compares two numbers A & B to determine whether: A > B, or A = B, or A < B. Here A and B are the two n-bit binary numbers. Input: First n-bit number A, Second n-bit number B Outputs: 3 output signals (GT, EQ, LT), where: 1. GT = 1 IFF A > B 2. EQ = 1 IFF A = B 3. LT = 1 IFF A < B => 4-bit magnitude comparator is a combinational logic circuit, which compares two 4-bit binary numbers A and B Inputs: 8-bits (A 4-bits, B 4-bits) A and B are two 4-bit numbers Let A = A 3A 2A 1A 0, and Let B = B 3B 2B 1B 0 Note: Inputs have 28 (256) possible combinations. Not easy to design using conventional techniques (OR) 8

9 5. a) Obtain the set of prime implicants for the Boolean expression f=σm(0,1,6,7,8,9,13,14,15) using the tabular method? [Iteration process-, Prime implicants-, Essential prime implecants-, Simplified expression -] 9

b) Explain and Design Half Adder and Full Adder? [Half adder -3M, Full adder 3M] Adder is a combinational circuit, which add the given bits. Adders are two types.

Half adder (HA) A half adder (HA) is an arithmetic circuit that is used to add two bits. It has two inputs and two outputs. The inputs of the HA are the 2 bits to be added; the augend, and addend.

10 b) Explain and Design Half Adder and Full Adder? [Half adder -3M, Full adder 3M] Adder is a combinational circuit, which add the given bits. Adders are two types. A half adder (HA) is an arithmetic circuit that is used to add two bits. A full adder (FA) is an arithmetic circuit that is used to add three bits. Half adder (HA) A half adder (HA) is an arithmetic circuit that is used to add two bits. It has two inputs and two outputs. The inputs of the HA are the 2 bits to be added; the augend, and addend. The output is the result of this addition, i.e. a sum bit (S) and a carry bit (C). The truth table of HA is The Boolean functions for the two outputs can be obtained from the truth table which are: The Logic diagram for half adder is Full Adder: It has three inputs and two outputs. The inputs of the FA are the 3 bits to be added; the augend, addend, and carry from previous lower significant position. The output is the result of this addition, i.e. a sum bit (S) and a carry bit (C). The simplified Boolean functions for the two outputs can be obtained from the truth table 10

11 14CS IT303 The Logic diagram for Full adder is 6. a) UNIT III What is race around condition? How is it eliminated? Explain with neat diagram 8M [Race around condition -, Elimination methods-, Explaining any one method- 5M (Explanation 2.5M, Logic circuit- 2.5M)] Race around condition In JK flip flop, the state of the flip flop is changes from 1to 0 and 0 to1 continuously, when continuous clock pulse is applied and j=1, k=1. This situation is called race around condition. Race around condition is eliminated in two ways. They are i) Master slave flip flop ii) Edge triggered flip flop. i) Master slave flip flop: 2.5M 2.5M 11

12 ii) Edge triggered flip flop. 14CS IT303 b) Draw the circuit of D-Flip flop and explain its operation along with Truth Table. [D flip flop -. Logic circuit-, truth table-, Explanation -] A Flip flop is a memory element, which is capable to store one bit of binary information. We have four type of flip flops. They are SR flip flop, D flip flop, JK flip flop and T flip flop. D Flip Flop: The RS latch seen earlier contains ambiguous state, to eliminate this condition we can ensure that S and R are never equal. This is done by connecting S and R together with an inverter. Thus we have D Latch same as the RS latch, with the only difference that there is only one input, instead of two (R and S). This input is called D 4M 12

(OR) 7. a) Draw the logical diagram (showing all gates) of a Master-Slave D Flip Flop. Use NAND gates. [Explanation -3M, logic circuit 3M] This circuit is a master-slave D flip-flop.

13 (OR) 7. a) Draw the logical diagram (showing all gates) of a Master-Slave D Flip Flop. Use NAND gates. [Explanation -3M, logic circuit 3M] This circuit is a master-slave D flip-flop. A D flip flop takes only a single input, the D (data) input. The master-slave configuration has the advantage of being edge-triggered, making it easier to use in larger circuits, since the inputs to a flip-flop often depend on the state of its output. The circuit consists of two D flip-flops connected together. When the clock is high, the D input is stored in the first latch, but the second latch cannot change state. When the clock is low, the first latch's output is stored in the second latch, but the first latch cannot change state. The result is that output can only change state when the clock makes a transition from high to low. 3M 3M b) With a neat diagram explain the working of SR-flip flop with characteristic table, excitation table and characteristic equation [SR Flip Flop-, Characteristic table, Excitation Table -] A Flip flop is a memory element, which is capable to store one bit of binary information. We have four type of flip flops. They are SR flip flop, D flip flop, JK flip flop and T flip flop. SR Flip Flop: 13

14 Excitation Table UNIT IV 8. a) Design a 4-bit up/down ripple counter using J-K Flip- Flops. [Explanation 3M, Logic diagram -3M] b) Explain the working of bi-directional shift register with a neat diagram [Explanation 3M, Logic circuit 3M] 4 bit Bidirectional Shift Register: Bidirectional shift register allows shifting of data either to left or to the right side. It can be implemented using logic gates circuitry that enables the transfer of data from one stage to the next stage to the right or to the left, depend on the level of control line. The RIGHT/LEFT is the control input signal which allows data shifting either towards right or towards left. A high on this line enables the shifting of data towards right and low enables it towards left. When RIGHT/LEFT is high, gates G1, G2, G3 and G4 are enabled. The state of Q output of each flip flop is passed through the D input of the following flip flop. When the pulse arrives, the data are shifted one place to the right. When the RIGHT/LEFT signal is low, gates G5, G6, G7 are enabled. The Q output of each flip-flop is passed through the D input of the preceding flipflop. 3M 14

15 3M (OR) 9. Write in detail about PROM, PLA and PAL [PLD- 3M, PROM 3M, PLA -3M, PAL 3M] 1 Programmable logic device (PLD s): Programmable Logic Device is an electronic component used to build reconfigurable digital circuits. PLD s contains set of inputs, AND gate array, OR gate array and set of outputs. Ex: PROM, PLA and PAL. PLDs are typically built with an array of AND gates (AND-array) and an array of OR gates (OR-array). 3M Three Fundamental Types of PLDs: The three fundamental types of PLDs differ in the placement of programmable connections in the AND-OR arrays. i) PROM (Programmable Read only memory) Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines) The fixed "AND" array is a decoder with 3 inputs and 8outputs implementing minterms. The programmable "OR array uses a single line to represent all inputs to an OR gate. An X in the array corresponds to attaching the minterm to the OR 3M ii) PLA(Programmable logic array ) Programmable Logic Array is an electronic component, has a programmable AND gate array, which links to a Programmable OR gate array, which can then be conditionally complemented to produce an output (use XOR gates at the output lines). A block diagram of the PLA is shown in the figure. It consists of n inputs, m outputs, and k product terms. 3M 15

iii) PAL (Programmable Array logic) Programmable Array Logic is an electronic component, has a programmable AND gate array, which links to a fixed OR gate array to produce output.

16 iii) PAL (Programmable Array logic) Programmable Array Logic is an electronic component, has a programmable AND gate array, which links to a fixed OR gate array to produce output. The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs. 3M HOD,IT Dept.. Scheme Prepared by. Mr. P. Srinivas Rao, Dept. of IT, BEC. Signature of Subject Teachers: S.No Name of the Faculty Name of the college Signature Signature of Paper evaluators: S.No Name of the Faculty Name of the college Signature

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don