II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.


 Lorena Parrish
 4 years ago
 Views:
Transcription
1 Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic Design Maximum : 60 Marks (1X12 = 12 Marks) Answer ONE question from each unit. (4X12=48 Marks) 1. Answer all questions (1X12=12 Marks) a) What are the basic operations in Boolean Algebra? b) Convert the decimal number 76 into the binary number c) State Demorgan s Laws? d) Mention disadvantages of Kmap e) Differentiate between a latch and a Flip Flop f) Which gate is called an all or nothing gate? Why? g) What is a literal? h) What is a code convertor? i) What are different types of RAM? j) What is race around condition? k) What is a counter? Mention different types of counters. l) What is meant by PLA? UNIT I 2. a) Convert the decimal number to base 3, base 7, base 8and base 16. b) Reduce the following expression to the simplest possible POS and SOP forms f=σm(6,9,13,18,19,25,27,29,31)+d(2,3,11,15,17,24,28) (OR) 3. a) Find the sum of the products expression using Kmap for the function F = Σm(7, 9, 10, 11, 12, 13, 14, 15) 8M b) Reduce the following expressions using a Fourvariable Kmap ABC + A BCD + ABC D + ABC 4M UNIT II 4. a) Implement FullSubtractor using two Half Subtractors and OR Gate. b) Explain in detail about 4bit magnitude comparator? (OR) 5. a) Obtain the set of prime implicants for the Boolean expression f=σm(0,1,6,7,8,9,13,14,15) using the tabular method? b) Explain and Design Half Adder and Full Adder? UNIT III 6. a) What is race around condition? How is it eliminated? Explain with neat diagram 8M b) Draw the circuit of DFlip flop and explain its operation along with Truth Table. 4M (OR) 7. a) Draw the logical diagram (showing all gates) of a MasterSlave D Flip Flop. Use NAND gates. b) With a neat diagram explain the working of SRflip flop with characteristic table, excitation table and characteristic equation UNIT IV 8. a) Design a 4bit up/down ripple counter using JK Flip Flops. b) Explain the working of bidirectional shift register with a neat diagram (OR) 9. Write in detail about PROM, PLA and PAL 1 1
2 2 14CS IT303
3 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. Answer ONE question from each unit. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Scheme of Evaluation & Solutions 14CS IT303 Common for CSE & IT Digital Logic Design Maximum : 60 Marks (1X12 = 12 Marks) (4X12=48 Marks) Answer all questions (1X12=12 Marks) a) What are the basic operations in Boolean Algebra? The Basic operations in Boolean Algebra are Logical AND, OR and NOT operations. b) Convert the decimal number 76 into the binary number c) State Demorgan s Laws? d) Mention disadvantages of Kmap The disadvantage of k map : It is not suitable for computer reduction. It is not suitable when the number of variables involved exceed four. Care must be taken to field in every cell with the relevant entry, such as a 0, 1 (or) don't care terms. e) Differentiate between a latch and a Flip Flop. Latch and Flip Flop both are capable to store one bit of binary data, but the difference is that latch doesn t accept clock pulse, but Flip Flop accept clock pulse. f) Which gate is called an all or nothing gate? Why? Ex Nor gate is called all or nothing gate, why because if both inputs are 1 or both are 0 it out puts 1 otherwise 0. g) What is a literal? A literal is a primed or un primed form of a variable. Or True form or complement form of a variable. Ex: x, x, y, y... h) What is a code convertor? A Code convertor is a Combinational Logic Circuit, Which converts a code from one form to another form. Ex: a) BCD 8421 to Ex3 Code convertor b) BCD 8421 to 2421 code convertor and etc. i) What are different types of RAM? SRAM: Static RAM DRAM: Dynamic RAM. j) What is race around condition? In JK flipflop output is fed back to the input. Therefore change in the output results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called race around condition. [Any relevant answer award one mark] 3
4 k) What is a counter? Mention different types of counters. A Counter is a sequential logic circuit, which counts the number of occurrences of an event based on clock pulses. The following are different type of counters. Asynchronous (ripple) counters Synchronous counters Johnson counters Decade counters UpDown counters Ring counters [Note: Listing any two counter types award full marks.] l) What is meant by PLA? PLA: Programmable Logic Array. Definition: PLA is programmable logic device, which is used to build reconfigurable logic circuits. And PLAs contained a two level structure of AND and OR gates with user programmable connections. UNIT I 2. a) Convert the decimal number to base 3, base 7, base 8 and base 16. [For each conversion 1.5 Marks] i) to base / 3 = 83 rem > 1 we're diving by three (our target base) and then keeping the remainder as our result and then repeat the process with the remaining number. 83 / 3 = 27 rem > 2 27 / 3 = 9 rem > 0 9 / 3 = 3 rem > 0 3 / 3 = 1 rem > 0 1 / 3 = 0 rem > 1 1.5M Now convert 0.5: 0.5 * 3 = >1 0.5 * 3 = > * 3 = > 1 this one goes on indefinitely! Both lists of digits start at the radix/decimal point and move away, the integer part to the left and the fraction part to the right. So the answer is: (250.5) 10 = ( ) 3 ii) to base / 7 = 35 rem / 7 = 5 rem / 7 = 0 rem M 0.5 * 7 = * 7 = * 7 = answer is: (250.5) 10 = ( ) 7 iii) to base / 8 = 31 rem / 8 = 3 rem / 8 = 0 rem * 8 = answer is: (250.5) 10 = ( 372.4) 8 1.5M 4
5 iv) to base / 16 = 15 rem 10...A 15 / 16 = 0 rem 15...F 14CS IT M 0.5 * 16 = answer is: (250.5)10 = (FA.8)16 b) Reduce the following expression to the simplest possible POS and SOP forms f=σm(6,9,13,18,19,25,27,29,31)+d(2,3,11,15,17,24,28) [5v KMap Structure, SOP form, POS form ] For Simplified SOP: F = xw + v x y z For Simplified POS: F= (z + w). (x + z). (x + z + w). (v + x + w ). (v + x + y ) 5
6 (OR) 3. a) Find the sum of the products expression using Kmap for the function F = Σm(7, 9, 10, 11, 12, 13, 14, 15) [4 variable kmap structure, Filling, Grouping, Simplifies expression ] Given expression contains 4 variables, therefore 4v k map is required for simplification. 4 Variable K map.. 8M 4M Simplifies SOP is: F= wx + wy + wz + xyz b) Reduce the following expressions using a Fourvariable Kmap ABC + A BCD + ABC D + ABC [expression expansion, K map, Grouping, Simplified expression ] 4M Given expression contains 4 variables, therefore 4v k map is required for simplification. 4 Variable K map.. 6
7 Simplifies SOP is: F = AC + ABD + BCD UNIT II 4. a) Implement FullSubtractor using two Half Subtractors and OR Gate. [Behaviour & Truth table, Expressions , Logic circuit ] A full subtractor is a combinational circuit that performs a subtraction between two bits, taking into account that a 1 may have been borrowed by a lower significant bit. The circuit has three inputs and two outputs. Input variables are minuend (X), subtrahend (Y), and previous borrow (Z); output variables are difference (D) and output borrow (B). It performs the operation X Y Z. It should be noted that the weight of the output borrow bit is 2, while the weight of the output difference bit is +1. The truth table of the full subtractor is The simplified Boolean functions for the two outputs are: The Logic diagram for Full subtractor using two half suntractors is: 7
8 b) Explain in detail about 4bit magnitude comparator? [Definitiona, For each Boolean expression, logic circuit ] A magnitude comparator is a combinational circuit that compares two numbers A & B to determine whether: A > B, or A = B, or A < B. Here A and B are the two nbit binary numbers. Input: First nbit number A, Second nbit number B Outputs: 3 output signals (GT, EQ, LT), where: 1. GT = 1 IFF A > B 2. EQ = 1 IFF A = B 3. LT = 1 IFF A < B => 4bit magnitude comparator is a combinational logic circuit, which compares two 4bit binary numbers A and B Inputs: 8bits (A 4bits, B 4bits) A and B are two 4bit numbers Let A = A 3A 2A 1A 0, and Let B = B 3B 2B 1B 0 Note: Inputs have 28 (256) possible combinations. Not easy to design using conventional techniques (OR) 8
9 5. a) Obtain the set of prime implicants for the Boolean expression f=σm(0,1,6,7,8,9,13,14,15) using the tabular method? [Iteration process, Prime implicants, Essential prime implecants, Simplified expression ] 9
10 b) Explain and Design Half Adder and Full Adder? [Half adder 3M, Full adder 3M] Adder is a combinational circuit, which add the given bits. Adders are two types. A half adder (HA) is an arithmetic circuit that is used to add two bits. A full adder (FA) is an arithmetic circuit that is used to add three bits. Half adder (HA) A half adder (HA) is an arithmetic circuit that is used to add two bits. It has two inputs and two outputs. The inputs of the HA are the 2 bits to be added; the augend, and addend. The output is the result of this addition, i.e. a sum bit (S) and a carry bit (C). The truth table of HA is The Boolean functions for the two outputs can be obtained from the truth table which are: The Logic diagram for half adder is Full Adder: It has three inputs and two outputs. The inputs of the FA are the 3 bits to be added; the augend, addend, and carry from previous lower significant position. The output is the result of this addition, i.e. a sum bit (S) and a carry bit (C). The simplified Boolean functions for the two outputs can be obtained from the truth table 10
11 14CS IT303 The Logic diagram for Full adder is 6. a) UNIT III What is race around condition? How is it eliminated? Explain with neat diagram 8M [Race around condition , Elimination methods, Explaining any one method 5M (Explanation 2.5M, Logic circuit 2.5M)] Race around condition In JK flip flop, the state of the flip flop is changes from 1to 0 and 0 to1 continuously, when continuous clock pulse is applied and j=1, k=1. This situation is called race around condition. Race around condition is eliminated in two ways. They are i) Master slave flip flop ii) Edge triggered flip flop. i) Master slave flip flop: 2.5M 2.5M 11
12 ii) Edge triggered flip flop. 14CS IT303 b) Draw the circuit of DFlip flop and explain its operation along with Truth Table. [D flip flop . Logic circuit, truth table, Explanation ] A Flip flop is a memory element, which is capable to store one bit of binary information. We have four type of flip flops. They are SR flip flop, D flip flop, JK flip flop and T flip flop. D Flip Flop: The RS latch seen earlier contains ambiguous state, to eliminate this condition we can ensure that S and R are never equal. This is done by connecting S and R together with an inverter. Thus we have D Latch same as the RS latch, with the only difference that there is only one input, instead of two (R and S). This input is called D 4M 12
13 (OR) 7. a) Draw the logical diagram (showing all gates) of a MasterSlave D Flip Flop. Use NAND gates. [Explanation 3M, logic circuit 3M] This circuit is a masterslave D flipflop. A D flip flop takes only a single input, the D (data) input. The masterslave configuration has the advantage of being edgetriggered, making it easier to use in larger circuits, since the inputs to a flipflop often depend on the state of its output. The circuit consists of two D flipflops connected together. When the clock is high, the D input is stored in the first latch, but the second latch cannot change state. When the clock is low, the first latch's output is stored in the second latch, but the first latch cannot change state. The result is that output can only change state when the clock makes a transition from high to low. 3M 3M b) With a neat diagram explain the working of SRflip flop with characteristic table, excitation table and characteristic equation [SR Flip Flop, Characteristic table, Excitation Table ] A Flip flop is a memory element, which is capable to store one bit of binary information. We have four type of flip flops. They are SR flip flop, D flip flop, JK flip flop and T flip flop. SR Flip Flop: 13
14 Excitation Table UNIT IV 8. a) Design a 4bit up/down ripple counter using JK Flip Flops. [Explanation 3M, Logic diagram 3M] b) Explain the working of bidirectional shift register with a neat diagram [Explanation 3M, Logic circuit 3M] 4 bit Bidirectional Shift Register: Bidirectional shift register allows shifting of data either to left or to the right side. It can be implemented using logic gates circuitry that enables the transfer of data from one stage to the next stage to the right or to the left, depend on the level of control line. The RIGHT/LEFT is the control input signal which allows data shifting either towards right or towards left. A high on this line enables the shifting of data towards right and low enables it towards left. When RIGHT/LEFT is high, gates G1, G2, G3 and G4 are enabled. The state of Q output of each flip flop is passed through the D input of the following flip flop. When the pulse arrives, the data are shifted one place to the right. When the RIGHT/LEFT signal is low, gates G5, G6, G7 are enabled. The Q output of each flipflop is passed through the D input of the preceding flipflop. 3M 14
15 3M (OR) 9. Write in detail about PROM, PLA and PAL [PLD 3M, PROM 3M, PLA 3M, PAL 3M] 1 Programmable logic device (PLD s): Programmable Logic Device is an electronic component used to build reconfigurable digital circuits. PLD s contains set of inputs, AND gate array, OR gate array and set of outputs. Ex: PROM, PLA and PAL. PLDs are typically built with an array of AND gates (ANDarray) and an array of OR gates (ORarray). 3M Three Fundamental Types of PLDs: The three fundamental types of PLDs differ in the placement of programmable connections in the ANDOR arrays. i) PROM (Programmable Read only memory) Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines) The fixed "AND" array is a decoder with 3 inputs and 8outputs implementing minterms. The programmable "OR array uses a single line to represent all inputs to an OR gate. An X in the array corresponds to attaching the minterm to the OR 3M ii) PLA(Programmable logic array ) Programmable Logic Array is an electronic component, has a programmable AND gate array, which links to a Programmable OR gate array, which can then be conditionally complemented to produce an output (use XOR gates at the output lines). A block diagram of the PLA is shown in the figure. It consists of n inputs, m outputs, and k product terms. 3M 15
16 iii) PAL (Programmable Array logic) Programmable Array Logic is an electronic component, has a programmable AND gate array, which links to a fixed OR gate array to produce output. The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs. 3M HOD,IT Dept.. Scheme Prepared by. Mr. P. Srinivas Rao, Dept. of IT, BEC. Signature of Subject Teachers: S.No Name of the Faculty Name of the college Signature Signature of Paper evaluators: S.No Name of the Faculty Name of the college Signature
B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is  Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 20152016 (ODD
More informationCOLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012DIGITAL
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN
SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.201718 INSTRUCTOR: Sri A.M.K.KANNA
More informationHANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment
Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)
More informationInjntu.com Injntu.com Injntu.com R16
1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by Kmap? Name it advantages and disadvantages. (3M) c) Distinguish between a halfadder
More informationR10. II B. Tech I Semester, Supplementary Examinations, May
SET  1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) 48 and +31
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201 DIGITAL PRINCIPLE AND SYSTEM DESIGN
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad  500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester
More informationSUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3
UNIT  I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented
More informationENDTERM EXAMINATION
(Please Write your Exam Roll No. immediately) ENDTERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA103 Subject: Digital Electronics Time: 3 Hours Maximum
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Academic Year 2018 19 III SEMESTER CS8351DIGITAL PRINCIPLES AND SYSTEM DESIGN Regulation
More informationDHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY
DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many
More informationR a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method
SET  1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove demorgan laws c) Implement two input EXOR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad  500043 Course Name : DIGITAL LOGIC DESISN Course Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : 2018 2019
More informationCS6201DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PARTB UNITI BOOLEAN ALGEBRA AND LOGIC GATES.
CS6201DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PARTB UNITI BOOLEAN ALGEBRA AND LOGIC GATES. 1) Simplify the boolean function using tabulation method. F = (0, 1, 2, 8, 10, 11, 14, 15) List all
More informationBHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS
BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS FREQUENTLY ASKED QUESTIONS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES
More informationPrinciples of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.
Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)
More informationNADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni625531 Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering
More information(ii) Simplify and implement the following SOP function using NOR gates:
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be
More informationSIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: IIB.Tech & ISem Course & Branch: B.Tech
More informationR07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April
SET  1 II B. Tech II Semester, Supplementary Examinations, April  2012 SWITCHING THEORY AND LOGIC DESIGN (Electronics and Communications Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions
More informationPART B. 3. Minimize the following function using Kmap and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).
II B. Tech II Semester Regular Examinations, May/June 2015 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, ECC, EIE.) Time: 3 hours Max. Marks: 70 Note: 1. Question Paper consists of two parts (PartA
More informationUNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PARTA (2 MARKS)
SUBJECT NAME: DIGITAL LOGIC CIRCUITS YEAR / SEM : II / III DEPARTMENT : EEE UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. What is variable mapping? 2. Name the two canonical forms for Boolean algebra.
More informationSHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI
SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL
More informationLogic design Ibn Al Haitham collage /Computer science Eng. Sameer
DEMORGAN'S THEOREMS One of DeMorgan's theorems stated as follows: The complement of a product of variables is equal to the sum of the complements of the variables. DeMorgan's second theorem is stated as
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL
More informationCOPYRIGHTED MATERIAL INDEX
INDEX Absorption law, 31, 38 Acyclic graph, 35 tree, 36 Addition operators, in VHDL (VHSIC hardware description language), 192 Algebraic division, 105 AND gate, 48 49 Antisymmetric, 34 Applicable input
More informationDigital logic fundamentals. Question Bank. Unit I
Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019
More informationMGUBCA205 Second Sem Core VI Fundamentals of Digital Systems MCQ s. 2. Why the decimal number system is also called as positional number system?
MGUBCA205 Second Sem Core VI Fundamentals of Digital Systems MCQ s Unit1 Number Systems 1. What does a decimal number represents? A. Quality B. Quantity C. Position D. None of the above 2. Why the
More informationCS/IT DIGITAL LOGIC DESIGN
CS/IT 214 (CR) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER 2016 First Semester CS/IT DIGITAL LOGIC DESIGN Time: Three Hours 1. a) FlipFlop Answer
More informationSwitching Theory & Logic Design/Digital Logic Design Question Bank
Switching Theory & Logic Design/Digital Logic Design Question Bank UNIT I NUMBER SYSTEMS AND CODES 1. A 12bit Hamming code word containing 8bits of data and 4 parity bits is read from memory. What was
More informationCONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)
CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...
More information10EC33: DIGITAL ELECTRONICS QUESTION BANK
10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function
More informationKING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:0011:50AM Class
More informationHours / 100 Marks Seat No.
17333 13141 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Illustrate your answers with neat sketches wherever necessary. (4)
More informationAPPENDIX A SHORT QUESTIONS AND ANSWERS
APPENDIX A SHORT QUESTIONS AND ANSWERS Unit I Boolean Algebra and Logic Gates Part  A 1. Define binary logic? Binary logic consists of binary variables and logical operations. The variables are designated
More informationDE Solution Set QP Code : 00904
DE Solution Set QP Code : 00904 1. Attempt any three of the following: 15 a. Define digital signal. (1M) With respect to digital signal explain the terms digits and bits.(2m) Also discuss active high and
More informationScheme G. Sample Test PaperI
Sample Test PaperI Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable
More informationR07
www..com www..com SET  1 II B. Tech I Semester Supplementary Examinations May 2013 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, EIE, BME, ECC) Time: 3 hours Max. Marks: 80 Answer any FIVE Questions
More informationUPY14602DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan
UPY14602DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I  NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal Binary Octal Hexadecimal number systemsinter conversionsbcd code Excess
More informationMULTIMEDIA COLLEGE JALAN GURNEY KIRI KUALA LUMPUR
STUDENT IDENTIFICATION NO MULTIMEDIA COLLEGE JALAN GURNEY KIRI 54100 KUALA LUMPUR SECOND SEMESTER FINAL EXAMINATION, 2013/2014 SESSION ITC2223 COMPUTER ORGANIZATION & ARCHITECTURE DSEWEF 1/13 18 FEBRUARY
More informationDIGITAL ELECTRONICS. Vayu Education of India
DIGITAL ELECTRONICS ARUN RANA Assistant Professor Department of Electronics & Communication Engineering Doon Valley Institute of Engineering & Technology Karnal, Haryana (An ISO 9001:2008 ) Vayu Education
More informationHours / 100 Marks Seat No.
17320 21718 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Figures to the right indicate full marks. (4) Assume suitable data,
More informationProgrammable Logic Devices
Programmable Logic Devices Programmable Logic Devices Fig. (1) General structure of PLDs Programmable Logic Device (PLD): is an integrated circuit with internal logic gates and/or connections that can
More informationModel EXAM Question Bank
VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI Department of Information Technology Model Exam 1 1. List the main difference between PLA and PAL. PLA: Both AND and OR arrays are programmable
More informationChapter 4 Arithmetic Functions
Logic and Computer Design Fundamentals Chapter 4 Arithmetic Functions Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Overview Iterative combinational
More informationFinal Exam Solution Sunday, December 15, 10:0512:05 PM
Last (family) name: First (given) name: Student I.D. #: Circle section: Kim Hu Department of Electrical and Computer Engineering University of Wisconsin  Madison ECE/CS 352 Digital System Fundamentals
More informationChapter 2: Combinational Systems
Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch
More informationQuestion Total Possible Test Score Total 100
Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,
More informationDigital Logic Design Exercises. Assignment 1
Assignment 1 For Exercises 15, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system
More informationCourse Batch Semester Subject Code Subject Name. B.EMarine Engineering B.E ME16 III UBEE307 Integrated Circuits
Course Batch Semester Subject Code Subject Name B.EMarine Engineering B.E ME16 III UBEE307 Integrated Circuits PartA 1 Define DeMorgan's theorem. 2 Convert the following hexadecimal number to decimal
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationSRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR
SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR 603203 DEPARTMENT OF COMPUTER SCIENCE & APPLICATIONS LESSON PLAN (207208) Course / Branch : B.Sc CS Total Hours : 50 Subject Name : Digital Electronics
More informationDIGITAL ELECTRONICS. P41l 3 HOURS
UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER
More informationCOMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic
More informationChapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More information2. (a) Compare the characteristics of a floppy disk and a hard disk. (b) Discuss in detail memory interleaving. [8+7]
Code No: A109211202 R09 Set No. 2 1. (a) Explain the purpose of the following registers: i. IR ii. PC iii. MDR iv. MAR. (b) Explain with an example the steps in subtraction of two ndigit unsigned numbers.
More informationPresentation 4: Programmable Combinational Devices
Presentation 4: Programmable Combinational Devices Asst. Prof Dr. Ahmet ÖZKURT DEUEEE Based on the Presentation by Prof. Kim, Young Ho Dept. of Information Computer Engineering Email : yhkim@hyowon.cs.pusan.ac.kr
More informationR.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai
L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT  I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean
More information3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0
1. The number of level in a digital signal is: a) one b) two c) four d) ten 2. A pure sine wave is : a) a digital signal b) analog signal c) can be digital or analog signal d) neither digital nor analog
More informationEECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15
1.) CLD2 problem 2.2 We are allowed to use AND gates, OR gates, and inverters. Note that all of the Boolean expression are already conveniently expressed in terms of AND's, OR's, and inversions. Thus,
More informationII/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Discrete Mathematical Structures. Answer ONE question from each unit.
14CS IT302 November,2016 II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Discrete Mathematical Structures (4X12=48 Marks) 1. Answer all questions (1X12=12 Marks) a (Pv~P) is
More informationD I G I T A L C I R C U I T S E E
D I G I T A L C I R C U I T S E E Digital Circuits Basic Scope and Introduction This book covers theory solved examples and previous year gate question for following topics: Number system, Boolean algebra,
More informationAssignment (36) Boolean Algebra and Logic Simplification  General Questions
Assignment (36) Boolean Algebra and Logic Simplification  General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationThis tutorial gives a complete understanding on Computer Logical Organization starting from basic computer overview till its advanced architecture.
About the Tutorial Computer Logical Organization refers to the level of abstraction above the digital logic level, but below the operating system level. At this level, the major components are functional
More informationLOGIC CIRCUITS. Kirti P_Didital Design 1
LOGIC CIRCUITS Kirti P_Didital Design 1 Introduction The digital system consists of two types of circuits, namely (i) Combinational circuits and (ii) Sequential circuit A combinational circuit consists
More information1. Prove that if you have tristate buffers and inverters, you can build any combinational logic circuit. [4]
HW 3 Answer Key 1. Prove that if you have tristate buffers and inverters, you can build any combinational logic circuit. [4] You can build a NAND gate from tristate buffers and inverters and thus you
More informationGATE CSE. GATE CSE Book. November 2016 GATE CSE
GATE CSE GATE CSE Book November 2016 GATE CSE Preface This book is made thanks to the effort of GATE CSE members and Praneeth who made most of the latex notes for GATE CSE. Remaining work of completing
More informationMLR Institute of Technology
MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad 500 043 Course Name Course Code Class Branch ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK : DIGITAL DESIGN
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationDIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER.
DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER 2015 2016 onwards DIGITAL ELECTRONICS CURRICULUM DEVELOPMENT CENTRE Curriculum Development
More informationDigital Design Using Digilent FPGA Boards  Verilog / ActiveHDL Edition
Digital Design Using Digilent FPGA Boards  Verilog / ActiveHDL Edition Table of Contents 1. Introduction to Digital Logic 1 1.1 Background 1 1.2 Digital Logic 5 1.3 Verilog 8 2. Basic Logic Gates 9
More informationINSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad ELECTRONICS AND COMMUNICATIONS ENGINEERING
INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad  00 0 ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK Course Name : DIGITAL DESIGN USING VERILOG HDL Course Code : A00 Class : II  B.
More informationCO Computer Architecture and Programming Languages CAPL. Lecture 9
CO20320241 Computer Architecture and Programming Languages CAPL Lecture 9 Dr. Kinga Lipskoch Fall 2017 A Fourbit Number Circle CAPL Fall 2017 2 / 38 Functional Parts of an ALU CAPL Fall 2017 3 / 38 Addition
More informationUnit 6 1.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2.Programmable Logic
EE 200: Digital Logic Circuit Design Dr Radwan E AbdelAal, COE Unit 6.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2. Logic Logic and Computer Design Fundamentals Part Implementation
More informationSpecifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
More informationECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks
ECE 331: N0 ECE230 Review Professor Andrew Mason Michigan State University Spring 2013 1.1 Announcements Opening Remarks HW1 due next Mon Labs begin in week 4 No class nextnext Mon MLK Day ECE230 Review
More informationComputer Architecture: Part III. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University
Computer Architecture: Part III First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Decoders Multiplexers Registers Shift Registers Binary Counters Memory
More informationReference Sheet for C112 Hardware
Reference Sheet for C112 Hardware 1 Boolean Algebra, Gates and Circuits Autumn 2016 Basic Operators Precedence : (strongest),, + (weakest). AND A B R 0 0 0 0 1 0 1 0 0 1 1 1 OR + A B R 0 0 0 0 1 1 1 0
More informationBHARATHIDASAN ENGINEERING COLLEGE
BHARATHIDASAN ENGINEERING COLLEGE CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (FOR COMMON TO 2 SEM CSE & IT) Lecturer notes Prepared by L.Gopinath M.tech Assistant professor UNIT 1 BOOLEAN ALGEBRS AND
More informationChapter 4. Combinational Logic
Chapter 4. Combinational Logic Tong In Oh 1 4.1 Introduction Combinational logic: Logic gates Output determined from only the present combination of inputs Specified by a set of Boolean functions Sequential
More informationWritten exam for IE1204/5 Digital Design Thursday 29/
Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.0013.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 087904487 Exam text does not have to be returned when
More informationChapter Three. Digital Components
Chapter Three 3.1. Combinational Circuit A combinational circuit is a connected arrangement of logic gates with a set of inputs and outputs. The binary values of the outputs are a function of the binary
More informationComputer Logical Organization Tutorial
Computer Logical Organization Tutorial COMPUTER LOGICAL ORGANIZATION TUTORIAL Simply Easy Learning by tutorialspoint.com tutorialspoint.com i ABOUT THE TUTORIAL Computer Logical Organization Tutorial Computer
More informationSWITCHING THEORY AND LOGIC CIRCUITS
SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra
More informationCHAPTER  2 : DESIGN OF ARITHMETIC CIRCUITS
Contents i SYLLABUS osmania university UNIT  I CHAPTER  1 : BASIC VERILOG HDL Introduction to HDLs, Overview of Digital Design With Verilog HDL, Basic Concepts, Data Types, System Tasks and Compiler
More informationDIGITAL ARITHMETIC: OPERATIONS AND CIRCUITS
C H A P T E R 6 DIGITAL ARITHMETIC: OPERATIONS AND CIRCUITS OUTLINE 6 Binary Addition 62 Representing Signed Numbers 63 Addition in the 2 s Complement System 64 Subtraction in the 2 s Complement
More informationSECTIONA
M.Sc(CS) ( First Semester) Examination,2013 Digital Electronics Paper: Fifth  SECTIONA I) An electronics circuit/ device
More informationii) Do the following conversions: output is. (a) (101.10) 10 = (?) 2 i) Define XNOR gate. (b) (10101) 2 = (?) Gray (2) /030832/31034
No. of Printed Pages : 4 Roll No.... rd 3 Sem. / ECE Subject : Digital Electronics  I SECTIONA Note: Very Short Answer type questions. Attempt any 15 parts. (15x2=30) Q.1 a) Define analog signal. b)
More informationBinary Addition. Add the binary numbers and and show the equivalent decimal addition.
Binary Addition The rules for binary addition are 0 + 0 = 0 Sum = 0, carry = 0 0 + 1 = 0 Sum = 1, carry = 0 1 + 0 = 0 Sum = 1, carry = 0 1 + 1 = 10 Sum = 0, carry = 1 When an input carry = 1 due to a previous
More informationSt.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad
St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad500 014 Subject: Digital Design Using Verilog Hdl Class : ECEII Group A (Short Answer Questions) UNITI 1 Define verilog HDL? 2 List levels of
More informationFinal Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)
Your Name: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS
More informationRipple Counters. Lecture 30 1
Ripple Counters A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter. The input pulses may be clock pulses, or they may originate from some
More information