Academic Course Description. VL2001 Digital System Design using Verilog First Semester, (Odd semester)

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1 Academic Course Description SRM University Faculty of Engineering and Technology Department of Electronics and Communication Engineering VL2001 Digital System Design using Verilog First Semester, (Odd semester) Course (catalog) description The course explores the design aspects involved in the realization of CMOS integrated circuits/systems from device up to the register/subsystem level. It addresses major design methodologies with emphasis placed on structured full custom design. The course includes the study of the MOS device, critical interconnect and gate characteristics that determine the performance of VLSI circuits. This course will held the students to learn basic digital VLSI design paradigms and the necessary Verilog HDL constructs that would help them to build combinational & sequential logic circuits in CMOS and run simulations using CAD tools. Compulsory/Elective course: Compulsory for 1 st semester M. Tech (VLSI Design) students. Credit hours: 4 credits Course coordinator(s): Mrs.M.valarmathi, Asst. Professor (Sr. Grade), Department of ECE Instructor(s) Name of the instructor Class handling Office location Office phone Consultation Mrs.M.valarmathi VLSI TP10S3 - valarmathi.m@ktr.srmuniv.ac.in Day pm Relationship to other courses Pre-requisites : Nil Assumed knowledge : Knowledge of digital design is useful to fully benefit from this course. However, no hardware description language experience is necessary. Following courses : VL2103 Low Power VLSI Design, VL2115 High Speed VLSI VL2118 Digital HDL Design and Verification Tools used ModelSim: Modelsim is a Simulation tool in which we write the code to check the Desired functionality and if require we debug the code. Xilinx ISE: Xilinx ISE is an Integrated Software Environment use to check HDL error and little bit simulation (Not as good as compare to Modelsim) plus it will synthesize the code and generate the required files for the Xilinx Device. Therefore, ISE does Simulation+Synthesis+FPGA File generation for Hardware configuration. Page 1 of 5

2 REFERENCES 1. Samir palnitkar, Verilog HDL, Pearson education, Second Edition,20O3. 2. J. Bhasker, A Verilog HDL Primer, Second Edition, Star Galaxy, J. Bhasker, A Verilog Synthesis: A Practical Primer, Star Galaxy, Jan.M.Rabaey., Anitha Chandrakasan Borivoje Nikolic, "Digital Integrated Circuits", Second Edition 5. Neil H.E Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design", 2nd Edition, Addition,Wesley, Sung Mu Kang, Yusuf Leblebici CMOS Digital Integrated Circuits, 3 rd edition, Tata McGraw- Hill, Class schedule: Four 50 minutes Lecture sessions and Four 50 minutes lab session per week Section VLSI Schedule Day1:8.50am- 9.40am Day2:9.45am-10.35am Day3: 1.25pm-2.15pm Day4:2.20pm-3.10pm Professional component General - 0% Basic Sciences - 0% Engineering sciences & Technical arts - 0% Professional subject - 100% Broad area: Communication Signal Processing Electronics VLSI Embedded Test Schedule - Theory This is a tentative Schedule that may change during the semester. S. No. Test Portions Duration 1 Cycle Test 2 units 2 periods 2 Model Exam 3 units 3hrs Course objectives 1. To use mathematical methods and circuit analysis models in analysis of CMOS digital electronics circuits, including logic components and their interconnects. 2. To understand of the characteristics of CMOS circuit construction. 3. To complete a significant VLSI design project having a set of objective criteria & design constraints. 4. To introduce the concepts & techniques of modern IC design and testing (CMOS VLSI). 5. To provide experience designing integrated circuits using Computer Aided Design (CAD) Tools. 6. Be able to design static CMOS combinational and sequential logic at the transistor level 7. Design for higher performance or lower area using alternative circuit families 8. Compare the tradeoffs of sequencing elements including FFs, transparent latches, and pulsed latches 9. Design functional units including adders, multipliers, ROMs, SRAMs, and PLAs Page 2 of 5

3 Course Learning Outcomes The learning outcomes for this course (i.e., what you should be able to do at the end of the course) are as follows: 1. Be able to use VLSI design methodologies to understand and design complex digital systems. 2. Be able to create circuits that realize specified digital functions. 3. Be able to identify logic and technology-specific parameters to control the functionality, timing, power, and parasitic effects.be able to complete a significant VLSI design project having a set of objective criteria & design constraints. Teaching plan(total contact hours=45 hrs) Unit -1 Basic concepts, Identifiers, System task and functions, Value set, Data types, Parameters, Operands, Operators, Modules and ports, Gate-level Modeling, Dataflow Modeling, Behavioral Modeling, Switch level modeling, Tri state gates, MOS Switches, Bidirectional switches, User defined primitives, Combinational UDP, Sequential UDP. Introduction to synthesis, Verilog HDL synthesis- Synthesis Design flow Test bench-lab exercise. Session Topics Text / Chapter 1 Basic concepts, Identifiers, Data types, Parameters, Operands, Operators, Ref [1], Chapter 3 2 Operands, Operators, Modules and ports Ref [1], Chapter 6 3 Modules and ports Ref [1], Chapter 4 4 Gate-level Modeling Ref [1], Chapter 5 5 Dataflow Modeling Ref [1], Chapter 6 6 Behavioral Modeling Ref [1], Chapter 7 7 Switch level modeling Ref [1], Chapter 11 8 User defined primitives, Combinational UDP, Sequential UDP. Ref [1], Chapter 12 9 System task and functions Ref [1], Chapter 8 10 Functions Ref [1], Chapter 8 11 Synthesis Design flow Test bench Ref [1], Chapter 8 12 lab exercises Ref[1]chapter2to12 Unit-2 MOS transistors- Threshold voltage- characteristics of MOS transistor-channel length modulation- short channel effects- Design of Logic gates using NMOS, PMOS and CMOS, Stick diagrams- Transfer characteristics of CMOS inverter- Power dissipation Delay and sizing of inverters- Lab exercise. 13 MOS transistors- Threshold voltage- characteristics of MOS transistor Ref [5], Chapter 2 14 channel length modulation Ref [5], Chapter 2 15 short channel effects- Ref [6], Chapter 3 16 Design of Logic gates using NMOS, PMOS Ref [5], Chapter 1 17 Design of Logic gates using CMOS,layout, Stick diagrams- Ref [5], Chapter 1 18 Transfer characteristics of CMOS inverter Ref [5], Chapter 1 19 Power dissipation Ref [5], Chapter 4 20 Delay Estimation Ref [5], Chapter 4 21 sizing of inverters Ref [5], Chapter 4 22 Lab exercise. Ref [5], Chapter 1 Unit3 CMOS COMBINATIONAL CIRCUITS Static CMOS design-complementary CMOS - static properties- complementary CMOS design-power consumption in CMOS logic gates-dynamic or glitching transitions - Design techniques to reduce switching activity - Radioed logic-dc VSL - pass transistor logic - Differential pass transistor logic - Sizing of level restorer-sizing in pass transistor-dynamic CMOS design-basic principles - Domino logicoptimization of Domino logic-npcmos-logic style selection -Designing logic for reduced supply voltages. Lab exercise in Switch level modeling. 23 Static CMOS and its properties Ref [5], Chapter 6 Page 3 of 5

4 24 Radioed logic circuits, Cascode Voltage Swing Ref [5], Chapter 6 25 Differential Cascode Voltage Swing logic(dcvsl). Ref [5], Chapter 6 26 Pass transistor logic - Differential pass transistor logic Ref [5], Chapter 6 27 Dynamic CMOS design-basic principles Ref [6], Chapter 9 28 Domino logic-optimization of Domino logic Ref [6], Chapter9 29 NP-CMOS-logic style selection Ref [6], Chapter9 30 Designing logic for reduced supply voltages. Ref [6], Chapter 9 31 Lab exercise in Switch level modeling. Ref [1], Chapter 11 Unit 4 CMOS SEQUENTIAL CIRCUITS Timing metrics for sequential circuit - latches Vs registers -static latches and registers - Bistability principle - multiplexer based latches-master slave edge triggered registers- non-ideal clock signals-low voltage static latches-static SR flip flop - Dynamic latches and registers-c 2 MOS register - Dual edge registers-true single phase clocked registers-pipelining to optimize sequential circuit latch Vs register based pipelines-non-bistable sequential circuit-schmitt trigger-mono stable -Astable -sequential circuit - choosing a clocking strategy.. Lab exercise in Switch level modeling 32 latches Vs registers -static latches and registers - Bistability principle - Ref [5], Chapter7 33 multiplexer based latches Ref [5], Chapter7 34 master slave edge triggered registers- non-ideal clock signalslow voltage static latches-static SR flip flop Ref [6], Chapter8 35 Dynamic latches and registers Ref [5], Chapter7 36 C 2 MOS register Ref [5], Chapter7 37 Dual edge registerstrue single Phase clockedregister Ref [5], Chapter7 38 pipelining to optimize sequential circuit latch Vs register based pipelines- Ref [5], Chapter7 39 Non-Bistable sequential circuit- Ref [5], Chapter7 40 Schmitt trigger-mono stable -Astable -sequential circuit Ref [6], Chapter8 Unit5 SUB-SYSTEM DESIGN Addition/Subtraction - Comparators- Zero/One Detectors- Binary Counters- ALUs Multiplication- Shifters- Memory elements- control: Finite-State Machines. Lab exercise. 41 Addition Ref [5], Chapter8 42 Subtraction Ref [5], Chapter8 43 Comparators- Zero/One Detectors-Binary Counters Ref [5], Chapter8 44 ALUs Shifters- Memory elements- control: Finite-State Machines. Lab exercise. Ref [5], Chapter8 45 Multiplication Ref [5], Chapter8 Grading Cycle Test - 10% Model Test - 10% Surprise Test - 5% Term Paper - 5% Lab Performance - 15% Final exam for Theory - 40% Final exam for Practical - 15% Revised by: Mrs.M.Valarmathi, Assistant Professor (Sr.Grade), Department of ECE Dated: 24 th July 2015 Revision No.: 00 Date of revision: NA Course Incharge M.VALARMATHI Page 4 of 5 HOD Dr.S.Malarvizhi

5 L T P C DIGITAL SYSTEMS DESIGN USING VERILOG VL2001 Total Contact Hours - 75 Prerequisites : Nil PURPOSE HDL programming being fundamental for VLSI design this course concentrates on delivering the necessary concepts and features. INSTRUCTIONAL OBJECTIVES The student will learn the different abstract levels in Verilog for modeling digital circuits. The student will learn the basic CMOS circuit, characteristics and performance. The student will learn the designing of combinational and sequential circuits in CMOS UNIT I - BASIC CONCEPTS - VERILOG Basic concepts, Identifiers, System task and functions, Value set, Data types, Parameters, Operands, Operators, Modules and ports, Gate-level Modeling, Dataflow Modeling, Behavioral Modeling, Switch level modeling, Tri state gates, MOS Switches, Bidirectional switches, User defined primitives, Combinational UDP, Sequential UDP. Introduction to synthesis, Verilog HDL synthesis-synthesis Design flow Test bench-lab exercise. UNIT II BASICS OF MOS TRANISTORS MOS transistors- Threshold voltage- characteristics of MOS transistor-channel length modulation- short channel effects- Design of Logic gates using NMOS, PMOS and CMOS, Stick diagrams- Transfer characteristics of CMOS inverter- Power dissipation Delay and sizing of inverters- Lab exercise. UNIT III - CMOS COMBINATIONAL CIRCUITS Static CMOS design-complementary CMOS - static properties- complementary CMOS design-power consumption in CMOS logic gates-dynamic or glitching transitions - Design techniques to reduce switching activity - Radioed logic-dc VSL - pass transistor logic - Differential pass transistor logic - Sizing of level restorer-sizing in pass transistor-dynamic CMOS design-basic principles - Domino logicoptimization of Domino logic-npcmos-logic style selection -Designing logic for reduced supply voltages. Lab exercise in Switch level modeling. UNIT IV - CMOS SEQUENTIAL CIRCUITS Timing metrics for sequential circuit - latches Vs registers -static latches and registers - Bistability principle - multiplexer based latches-master slave edge triggered registers- non-ideal clock signals-low voltage static latches-static SR flip flop - Dynamic latches and registers-c 2 MOS register - Dual edge registers-true single phase clocked registers-pipelining to optimize sequential circuit latch Vs register based pipelines-non-bistable sequential circuit-schmitt trigger-mono stable -Astable -sequential circuit - choosing a clocking strategy.. Lab exercise in Switch level modeling UNIT V SUB-SYSTEM DESIGN/ SYSTEM VERILOG Addition/Subtraction - Comparators- Zero/One Detectors- Binary Counters- ALUs Multiplication- Shifters- Memory elements- control: Finite-State Machines. Lab exercise. REFERENCES 1. Samir palnitkar, Verilog HDL, Pearson education, Second Edition,20O3. 2. J. Bhasker, A Verilog HDL Primer, Second Edition, Star Galaxy, J. Bhasker, A Verilog Synthesis: A Practical Primer, Star Galaxy, Jan.M.Rabaey., Anitha Chandrakasan Borivoje Nikolic, "Digital Integrated Circuits", Second Edition 5. Neil H.E Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design", 2nd Edition, Addition Wesley, Sung Mu Kang, Yusuf Leblebici CMOS Digital Integrated Circuits, 3 rd edition, Tata McGraw-Hill, Page 5 of 5

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