MAX6618 PECI-to-I2C Translator

Transcription

1 General Description The MAX668 PECI(.0)-to-I 2 C translator provides an efficient, low-cost solution for PECI(.0)-to-SMBus/I 2 C protocol conversion. The PECI(.0)-compliant host reads temperature data directly from up to four PECI(.0)-enabled CPUs. This translator will only communicate with CPUs that support PECI.0. The I 2 C interface provides an independent serial communication channel to communicate synchronously with peripheral devices in a multiple master or multiple slave system. This interface allows a maximum serial-data rate of 400kbps. The MAX668 is designed to operate from a +3.0V to +3.6V supply voltage and ambient temperature range of -20 C to +20 C. Servers Workstations Desktop Computers Pin Configuration appears at end of data sheet. Applications Features 400kbps I 2 C-Compatible, 2-Wire Serial Interface +3V to +3.6V Supply Voltage PECI(.0)-Compliant Port PECI(.0)-to-I 2 C Translation Programmable Temperature Offsets -20 C to +20 C Operating Temperature Range V REF Input Refers Logic Levels to the PECI Supply Voltage Automatic I 2 C Bus Lockup Timeout Reset Lead-Free, 0-Pin µmax Package Ordering Information PART TEMP RANGE PIN-PACKAGE MAX668AUB+ -20 C to +20 C 0 µmax MAX668AUB+T -20 C to +20 C 0 µmax +Denotes a lead(pb)-free/rohs-compliant package. T = Tape and reel. Typical Application Circuit +3.3V V CPU V TT V CC I 2 C MASTER SDA SDA AD2 MAX668 V REF PECI CPU INTERNAL TEMP SENSOR AD AD0 GND µmax is a registered trademark of Maxim Integrated Products. For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim Integrated s website at ; Rev 4; 5/3

2 ABSOLUTE MAXIMUM RATINGS (All voltages with respect to GND.) V CC V to +4V AD0, AD, AD2, V to (V CC + 0.3V), SDA V to +6V V REF V to +4V PECI V to (V REF + 0.3V) DC Current through SDA...0mA Continuous Power Dissipation (T A = +70 C) µmax (derate 5.6mW/ C over T A = +70 C)...444mW Operating Temperature Range C to +20 C Junction Temperature C Storage Temperature Range C to +50 C Lead Temperature (soldering, 0s) C Soldering Temperature (reflow) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Typical Application Circuit, V CC = +3V to +3.6V, V REF = +0.95V to +.26V, T A = -20 C to +20 C, unless otherwise noted. Typical values are at V CC = +3.3V, V REF = +.0V, T A = +25 C.) (Note ) SUPPLY PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage V CC V Operating Supply Current I CC = 400kHz 4 7 ma Power-On-Reset Voltage V POR V INPUT, INPUT/OUTPUT SDA Low-Level Input Voltage V IL 0.3 x V CC High-Level Input Voltage V IH 0.7 x V CC 5.5 V Low-Level Output Voltage V OL I OL = 6mA 0.4 V Leakage Current I L - + µa Input Capacitance C I 0 pf ADDRESS INPUT AD0 Low-Level Input Voltage V IL 0.3 x V CC High-Level Input Voltage V IH 0.7 x V CC Leakage Current I L µa Input Capacitance C I 0 pf PECI Supply Voltage to PECI Cell V REF V V CC V V V Input Voltage Range V IN -0.3 Low-Level Input Voltage Threshold High-Level Input Voltage Threshold V REF V IL x V REF x V REF V IH x V REF x V REF V V V 2 Maxim Integrated

3 ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, V CC = +3V to +3.6V, V REF = +0.95V to +.26V, T A = -20 C to +20 C, unless otherwise noted. Typical values are at V CC = +3.3V, V REF = +.0V, T A = +25 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Hysteresis V H 0. x V REF V Low-Level Sinking Current I IL ma High-Level Sourcing Current I IH -6 ma Input Capacitance C I (Note 2) 0 pf Signal-Noise Immunity Above 300MHz V N (Note 2) 0. x V REF V P-P TIMING CHARACTERISTICS (Typical Application Circuit, V CC = +3V to +3.6V, V REF = +0.95V to +.26V, T A = -20 C to +20 C, unless otherwise noted. Typical values are at V CC = +3.3V, V REF = +.0V, T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I 2 C INTERFACE Serial-Clock Frequency f 400 khz Bus Free Time Between a STOP and a START Condition t BUF.3 µs Hold Time, (Repeated) START Condition Repeated START Condition Setup Time t HD, STA 0.6 µs t SU, STA 0.6 µs STOP Condition Setup Time t SU, STO 0.6 µs Data Hold Time t HD, DAT (Note 3) 0.9 µs Data Setup Time t SU, DAT 20 ns Clock-Low Period t LOW.3 µs Clock-High Period t HIGH 0.6 µs Rise Time of Both SDA and Signals, Receiving t R (Notes 4, 5) C b 300 ns Fall Time of Both SDA and Signals, Receiving t F (Notes 4, 5) C b 300 ns Fall Time of SDA Transmitting t F.TX (Notes 4, 5) C b 250 ns Pulse Width of Spike Suppressed Capacitive Load for Each Bus Line t SP (Notes 2, 6) ns C b (Notes 2, 4) 400 pf PECI INTERFACE Bit Time (Note 7) t BIT Overall time evident on PECI Driven by MAX µs Maxim Integrated 3

4 TIMING CHARACTERISTICS (continued) (Typical Application Circuit, V CC = +3V to +3.6V, V REF = +0.95V to +.26V, T A = -20 C to +20 C, unless otherwise noted. Typical values are at V CC = +3.3V, V REF = +.0V, T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Bit Time Jitter t BIT, jitter header or data bytes after timing has been Between adjacent bits in an PECI message negotiated Change in Bit Time t BIT, drift Across a PECI address or PECI message bits as driven by MAX668 % 2 % High-Level Time for Logic-High t H (Note 8) x t BIT High-Level Time for Logic-Low t H x t BIT Client Asserts PECI High During Logic-High t SU x t BIT-M Rise Time t R Measured from V OL to V P MAX, V REF(nom) -5% (Note 9) Fall Time t F Measured from V OH to V N MAX, V REF(nom) +5% (Note 9) Hold Time t HOLD Time for client to maintain a low idle drive after MAX668 begins a message (Note 0) Stop Time t STOP A constant low level driven by MAX668 (Notes 8, ) /Node 30/Node ns ns 0.5 x t BIT- 2 x t BIT-M Maximum Dwell Time of the PECI Client t RESET From the end of a ResetDevice command to the next message to which the reset client must be able to respond 0.4 ms Minimum PECI Low Time Preceding a Message t SETUP If the prior t BIT is not known by MAX668, the maximum t BIT must be assumed and t SETUP = ms in this case (Note 2) 2 x t BIT-X Note : All parameters are tested at T A = +25 C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design; not production tested. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V IL of the signal) to bridge the undefined region of s falling edge. Note 4: C b = total capacitance of one bus line in pf. t R and t F measured between 0.3 x V CC and 0.7 x V CC. Note 5: I SINK 6mA. C b = total capacitance of one bus line in pf. t R and t F measured between 0.3 x V CC and 0.7 x V CC. Note 6: Input filters on the SDA and inputs suppress noise spikes less than 50ns. Note 7: The MAX668 must drive a more restrictive time to allow for quantized sampling errors by a client yet still attain the minimum time less than 500µs. t BIT limits apply equally to t BIT-A and t BIT-M. Note 8: The minimum and maximum bit times are relative to t BIT defined in the timing negotiation pulse. Note 9: Extended trace lengths can appear as additional nodes. Note 0: The client may deassert its low idle drive prior to the falling edge of the first bit of the message by using the rising edge to detect a message start. However, the time delay must be sufficient to qualify the rising edge as a true message rather than a noise spike. Note : The message stop is defined by two consecutive periods when the bus has no rising edge. Tolerance around this time is based on the t BIT-M error budget. Note 2: t SETUP is not additive with t STOP. Rather, these times may overlap. 4 Maxim Integrated

5 Pin Description PIN NAME FUNCTION PECI Platform Environment Control Interface (PECI) Serial-Bus Input/Output 2 AGND Analog Ground 3 AD0 I 2 C Bus Device Address Selection Input A0 4 SDA I 2 C Bus Data Input/Output 5 I 2 C Bus Clock Input 6 V CC Power Supply. Bypass to GND with a 0.µF capacitor. 7 GND Power-Supply Ground 8 AD2 Internally Connected. Not used for I 2 C slave address selection. Must be connected to GND or V CC. 9 AD Internally Connected. Not used for I 2 C slave address selection. Must be connected to GND or V CC. 0 V REF PECI Input Supply Voltage. Bypass V REF to AGND with a 0.µF capacitor. Block Diagram MAX668 SDA I 2 C PORT AD2 AD PECI TRANSLATION ENGINE AD0 PECI PECI PORT V REF Maxim Integrated 5

6 Detailed Description The MAX668 obtains temperature data from an internal temperature sensor in PECI-compliant hosts. Up to four PECI hosts can be connected to the PECI I/O interface. The MAX668 handles all the PECI transmissions and uses a 2-wire, I 2 C-compatible serial interface to communicate with the PECI host. Registers and Commands The following is an overview of the I 2 C/SMBus registers/commands supported by the MAX668. ADDRESS DESCRIPTION TRANSACTION TYPE 00h Read socket 0, domain 0 temperature register ReadWord 0h Read socket 0, domain temperature register ReadWord 02h Read socket, domain 0 temperature register ReadWord 03h Read socket, domain temperature register ReadWord 04h Read socket 2, domain 0 temperature register ReadWord 05h Read socket 2, domain temperature register ReadWord 06h Read socket 3, domain 0 temperature register ReadWord 07h Read socket 3, domain temperature register ReadWord 08h Read maximum temperature for all enabled sockets/domains register ReadWord 09h Read firmware version register ReadWord 0Ah Read maximum temperature address ReadWord 0Bh Read socket and domain that caused alert ReadWord 0Ch Read/write CONFIG0 register ReadWord/WriteWord 0Dh Read/write CONFIG register ReadWord/WriteWord 0Eh Read/write CONFIG2 register ReadWord/WriteWord 0Fh Read/write CONFIG3 register ReadWord/WriteWord 0h Read/write alert temperature for socket 0 ReadWord/WriteWord h Read/write alert temperature for socket ReadWord/WriteWord 2h Read/write alert temperature for socket 2 ReadWord/WriteWord 3h Read/write alert temperature for socket 3 ReadWord/WriteWord 4h Request polling SendByte 5h Clear alert SendByte Configuration The MAX668 has four configuration registers (Table ). CONFIG0 is the main configuration register that enables the PECI sockets, I 2 C bus timeout, PEC, alert activation, and polling delay. CONFIG sets the number of retries, CONFIG2 sets the temperature offset, and CONFIG3 controls the temperature averaging. You can write to the configuration registers to set the configuration or read from the configuration registers to get the current settings. Table. Configuration Registers COMMAND BYTE REGISTER DESCRIPTION TYPE RESULT 0Ch CONFIG0 register ReadWord/WriteWord See the CONFIG0 section. 0Dh CONFIG register ReadWord/WriteWord See the CONFIG section. 0Eh CONFIG2 register ReadWord/WriteWord See the CONFIG2 section. 0Fh CONFIG3 register ReadWord/WriteWord See the CONFIG3 section. 6 Maxim Integrated

7 CONFIG0 The CONFIG0 register holds a bit mask for PECI sockets and domains that are enabled for polling as well as a polling delay (minimum delay between sets of polls) and features enable/disable bits. Table 2 shows the various options for CONFIG0. Table 2. CONFIG0 Register BIT(S) DESCRIPTION DEFAULT 5:8 Polling enable for sockets and domains 00h 5 = enable socket 3, domain 0 4 = enable socket 3, domain = enable socket 2, domain 0 2 = enable socket 2, domain 0 0 = enable socket, domain 0 0 = enable socket, domain = enable socket 0, domain 0 8 = enable socket 0, domain = enable I 2 C bus lockup timeout 0 = Disable timeout = alternate data representation 0 = 6-bit data representation = enable I 2 C packet error checksum (PEC) on device return data 0 = Disable PEC 4 = mask temperature alerts 0 = Activate alerts 0 3 Reserved, set to 0 0 2:0 Poll delay, see Table The optional polling delay (bits 2:0) inserts after polling the set of all sockets and domains that are enabled in bits 5:8 with a minimal pause of 2.5ms between PECI reads. After polling all enabled sockets and domains, the device pauses PECI communications for the configured time before starting to poll the set of enabled sockets and domains again. Table 3 shows the various polling delay options. Table 3. Polling Delay POLL DELAY VALUE DELAY BETWEEN POLLS (ms) 0 Polling on request only (default) Reserved CONFIG The CONFIG register configures the maximum number of retries before aborting a PECI temperature read as well as the originated (suggested) PECI bit time. Table 4 shows the various options for CONFIG. Software must configure this value as the register default may cause improper operation. Table 4. CONFIG Register BIT(S) DESCRIPTION DEFAULT 5:8 Originated PECI bit time (before negotiation) 0h: RESERVED 4h 0FFh: CONFIG[5:8] + µs Minimum: 4h (= 2µs / 47.62kHz) Maximum: 0FFh (= 256µs / 3.906kHz) 02h 7:0 Maximum number of retries for PECI transactions 03h Maxim Integrated 7

8 CONFIG2 The CONFIG2 register holds the offset that is added to all temperature return values that are not error codes. The offset is enabled in CONFIG0, bit 6; +95 C is set as 7C0h or 005Fh, depending on the data format. To represent +95 C in 6-bit representation, convert +95 C to binary using two s complement and left-shift six times. The MAX668 automatically converts the offset value to the equivalent value when the data format is changed. See Table 5 for the default offset and Table 6 for some example values. Table 5. CONFIG2 Register BIT(S) DESCRIPTION DEFAULT 5:0 Temperature offset 0000h Table 6. Example Offset Values in 6-Bit Temperature Representation TEMP ( C) HEX RESHI BINARY RESLO h h C80h C0h C0h When configured in CONFIG2 and the return code is not an error code (see the Error Codes section), the device adds the offset value stored in CONFIG2 to the return value. For example, if the CPU s thermal control circuit activation point is at +95 C, CONFIG2 can be set to +95 C (005Fh or 7C0h) and all return values are converted to absolute temperatures. Note that the thermal control circuit activation point is CPU specific. The offset value is represented in the current data format. CONFIG3 CONFIG3 register configures the temperature averaging function. See the Temperature Averaging section for more information. Table 7 shows the default settings. Table 7. CONFIG3 Register BIT(S) DESCRIPTION DEFAULT 5:8 Reserved, set to 0 00h 7:0 Averaging shift count, see formula 00h Temperature Representation Temperature data is formatted in 6-bit two s complement representing a range from -52 C to +52 C in steps of /64 C (Figure ). Internally, the device always uses the 6-bit data format. The temperature is given in two s complement and left-shifted so that the + C bit is bit 6 (Figure 2). Temperatures can be represented externally in alternate data format if fractional readings are not needed. Table 8 shows some examples. RESLO C 4 C C C C C C 6 64 Figure. Temperature Measured in /64 C Steps TWO'S -50 C COMPLEMENT RESHI RESLO Figure 2. Conversion of Temperature Done in Two s Complement Table 8. Example of 6-Bit Representation with No Offset (Activation Point = +95 C) TEMP RELATIVE BINARY HEX ( C) TEMP ( C) RESHI RESLO FFC0h FD80h FDC0h F380h ED30h Maxim Integrated

9 Alternate Temperature Value Representation This optional feature can be enabled using bit 6 of CONFIG0. When the alternate data format is enabled, the temperature value is shifted right as shown in Table 9. The most significant bits are set to all 0s or all s depending on the sign bit 5, also shown as S in Figure 3. Table 0 shows some example values. This translation is not performed for error codes (6-bit values from 8000h through 8FFh). Excluding error codes, the software only has to examine the RESLO data byte, as it represents an integer value in the range from -28 C to +27 C in C steps. The RESHI byte is all 0s or all s for valid return codes, and either 80h or 8h for all error codes. Temperature Averaging The MAX668 can average several temperature readings and return a value as calculated by: TNEW = xt CONFIG PECI CONFIG3 xt OLD where T OLD is the previously stored temperature, T PECI is the new value read from PECI, and T NEW is the newly stored temperature ready to be returned through I 2 C. This calculation can cause significant bits to be lost. Enable temperature averaging by writing the desired averaging amount to the CONFIG3 register. Writing 00h to the CONFIG3 register disables temperature averaging. Table 9. Alternate Temperature Representation DESCRIPTION RESHI RESLO 6-bit value 5:4:3:2::0:9:8 7:6:5:4:3:2::0 Alternate representation 5:5:5:5:5:5:5:5 5:2::0:9:8:7:6 FRACTIONAL VALUE RESHI RESLO S X X X X X X X X S S S S S S S S S (SIGN BITS) INTEGER VALUE (~ C) Figure 3. Alternate Temperature Representation Table 0. Example of Alternate Representation with No Offset (Activation Point = +95 C) TEMP ( C) RELATIVE TEMP ( C) HEX BINARY RESHI RESLO FFFFh FFF6h FFE7h FFCEh FFB5h 0 00 Maxim Integrated 9

10 Temperature Commands Table shows the different commands for selecting one of the PECI hosts or getting the maximum temperature. Read commands are initiated by the MAX668, and the result returned is a 6-bit word with the least significant bit (LSB) clocked in first for the selected PECI host. The result consists of RESLO for the 8 LSBs and RESHI for the 8 MSBs, resulting in a 6-bit word. The 6-bit words are temperature values read from the PECI interface. PECI-enabled Intel microprocessors return temperature data in fractions of C below the thermalcontrol-circuit activation point, resulting in negative return values that do not represent absolute temperatures. Absolute temperatures can be achieved by setting the temperature offset in CONFIG2. Table 2 shows example return values for an Intel CPU. Note that the MAX668 does not interpret the return Table. Read Temperature ADDRESS REGISTER TYPE RESULT 00h Socket 0, domain 0 0h Socket 0, domain 02h Socket, domain 0 03h Socket, domain 04h Socket 2, domain 0 05h Socket 2, domain 06h Socket 3, domain 0 07h Socket 3, domain 08h Read maximum temperature for all enabled sockets/domains ReadWord 6-bit words Table 2. Return Temperature Values RELATIVE CONFIG2 OFFSET RESHI:RESLO RESULT TEMPERATURE ( C) 6 BITS ALTERNATE 6 BITS ALTERNATE FFC0 FFFF 7C0 005F E F700 FFDC 7C0 005F 0ec0 003B F6C0 FFDB 7C0 005F 0E80 003A F680 FFDA 7C0 005F 0E F640 FFD9 7C0 005F 0E F600 FFD8 7C0 005F 0DC F5C0 FFD7 7C0 005F 0D F580 FFD6 7C0 005F 0D F540 FFD5 7C0 005F 0D Maxim Integrated

11 data (with the exception of error codes) and the relative temperatures are listed for reference only. Table 2 shows the values with 6-bit and alternate word format. The read maximum temperature command from Table returns the highest temperature that is not an error code from the enabled PECI sockets and domains. This operation works on signed numbers only and does not give information as to what socket the temperature result comes from. To find the socket and domain, use the read maximum temperature address command as shown in Table 3. Y DATA FROM PECI ERROR? N AVERAGING Table 3. Read Maximum Temperature Address N ALT. FORMAT? COMMAND DESCRIPTION TYPE RESULT 0Ah Read address of socket/domain with the maximum temperature ReadWord 6-bit Y CONVERT DATA FORMAT The read maximum temperature address command returns the register that had the highest temperature when read maximum temperature was last called. An error is returned if the read maximum temperature has not been called or when the read maximum temperature itself returns an error. Return Value Flow Chart Figure 4 shows the operations performed on temperature data read through PECI. ADD OFFSET RETURN DATA ON I 2 C Figure 4. Operational Flowchart Maxim Integrated

12 Error Codes Error codes are represented as 6-bit words in the range 8000h 8FFh as shown in Table 4. Version Information Command Table 5 shows the command to read the firmware version. Table 5. Firmware Command Table 4. Error Codes COMMAND DESCRIPTION TYPE RESULT ERROR CODES DESCRIPTION 09h Get firmware version ReadWord 6-bit word 8000h 80FFh 800h 80h 802h 803h 804h Refer to Intel PECI specification. PECI transaction failed for more than the configured number of consecutive retries. Polling disabled for requested socket/domain. First poll not yet completed for requested socket/domain (on startup). Read maximum temperature requested, but no sockets/domains enabled or all enabled sockets/domains have errors; or read maximum temperature address requested, but read maximum temperature was not called. Get alert socket/domain requested, but no alert active. The result is a 6-bit word (low byte transmitted first, high byte second), e.g., 000h for the MAX668 firmware version.0. Bus Lockout Timeout Reset If an I 2 C transaction starts and gets locked up for greater than 20ms, the MAX668 asserts the internal bus lockup reset that restarts itself in the default startup condition. Serial Interface The MAX668 operates as a slave that sends and receives data through an I 2 C-compatible, 2-wire interface. The interface uses a serial-data line (SDA) and a serial-clock line () to achieve bidirectional communication between master and slave. A master (typically a microcontroller) initiates all data transfers to and from the MAX668 and generates the clock that synchronizes the data transfer (Figure 5). SDA t SU, DAT t SU, STA t HD, STA t BUF t LOW t HD, DAT t SU, STO t HIGH t HD, STA t R t F START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 5. 2-Wire Serial-Interface Timing Details 2 Maxim Integrated

13 The MAX668 and SDA lines operate as both inputs and open-drain outputs. A pullup resistor is required on and SDA. Each transmission consists of a START condition sent by a master, followed by the MAX668 7-bit slave address, plus an R/W bit, one or more data bytes, and finally a STOP condition (Figure 6). To write to a MAX668 register, a write transmission consists of a START condition, followed by the MAX668 7-bit slave address plus R/W = 0, a register address byte, one data byte, and finally a STOP condition. To read from a MAX668 register, a combined write and read transmissions are required. The first write transmission consists of a START condition, followed by the MAX668 7-bit slave address plus R/W = 0, a register address byte, and finally a STOP condition that sets the register to be read. The second read transmission consists of a START condition, followed by the MAX668 7-bit slave address plus R/W =, one or more data bytes, and finally a STOP condition that reads the data from the specified register. These write and read transmissions must be joined using a repeated START without a STOP after the write transaction, even though the MAX668 7-bit slave address needs to be present preceding the R/W bits. Start and Stop Conditions Both and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while is high. The bus is then free for another transmission (Figure 6). SDA SDA S START CONDITION P STOP CONDITION DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED Figure 6. Start and Stop Conditions Figure 7. Bit Transfer Maxim Integrated 3

14 Data Transfer and Acknowledge One data bit is transferred during each clock pulse. The data on SDA must remain stable while is high (Figure 7). The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data (Figure 8). Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse so that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX668, the MAX668 generates the acknowledge bit because the MAX668 is the recipient. When the MAX668 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. Slave Address The MAX668 has a 7-bit long slave address (Figure 9). The 8th bit following the 7-bit slave address is the R/W bit. The R/W bit is low for a write command and high for a read command. The first four bits of the MAX668 slave address (A6:A3) are always 00. Bits A2:A are set during the manufacturing process to 0:. A0 is selected by the address input AD0. AD0 can be connected to GND or V CC. The MAX668 has two possible slave addresses selectable by AD0. Therefore, a maximum of two MAX668 devices can be controlled independently from the same interface (see the I 2 C Address Range section). Message Format for Writing to the MAX668 A write to the MAX668 consists of the transmission of the MAX668 s slave address with the R/W bit set to zero, followed by at least byte of information. The first byte of information is the command byte. The command byte determines which register of the MAX668 is to be written to by the next byte or read from during the next read transmission. If a STOP condition is detected after the command byte is received, then the MAX668 takes no further action beyond setting the register address. The bytes received after the command byte are data bytes. The data bytes go into the register of the START CONDITION CLOCK PULSE FOR ACKNOWLEDGEMENT SDA A0 ACK SDA BY TRANSMITTER SDA BY RECEIVER S Figure 8. Acknowledge Figure 9. Slave Address 4 Maxim Integrated

15 MAX668 specified by the command byte. Only the last data byte or word transmitted before a STOP condition is stored by the device (Figure 0). Message Format for Reading the MAX668 The MAX668 is read using the MAX668 s internally stored command byte as an address pointer the same way the stored command byte is used as an address pointer for a write. The pointer autoincrements after each data byte is read. Thus, a read is initiated by first TYPICAL READ WORD COMMAND PEC (PACKET ERROR CHECKSUM) ENABLED MASTER ADDR:7 W A CMD:8 A MAX668 ADDR:7 R A RESLO:8 A RESHI:8 A PEC:8 NA P PEC (PACKET ERROR CHECKSUM) DISABLED MASTER ADDR:7 W A CMD:8 A MAX668 ADDR:7 R A RESLO:8 A RESHI:8 NA P TYPICAL WRITE WORD COMMAND COMMAND WITH PEC (PACKET ERROR CHECKSUM) MASTER S ADDR:7 W A CMD:8 A INLO:8 A INHI:8 A PEC:8 A P COMMAND WITHOUT PEC (PACKET ERROR CHECKSUM) MASTER S ADDR:7 W A CMD:8 A INLO:8 A INHI:8 A P THE RESULT CONSISTS OF RESLO FOR THE 8 LEAST SIGNIFICANT BITS (LSBS) AND RESHI FOR THE 8 MOST SIGNIFICANT BITS (MSBS), RESULTING IN A 6-BIT WORD. TEMPERATURE DATA AND ERROR CODES ARE GIVEN AS 6-BIT WORDS. ADDR:7: 7-BIT ADDRESS FOLLOWED BY A READ (R = ) OR WRITE (W = 0) BIT TO FORM THE 8-BIT ADDRESS USED IN THE I 2 C/SMBUS PROTOCOL. P: I 2 C STOP CONDITION. SEE FIGURE 6. S: I 2 C START CONDITION. SEE FIGURE 6. A: ACK. THE PULSE ON THE 9th CLOCK CYCLE TO INDICATE ACKNOWLEDGE TRANSFER. SLAVE PULLS LOW TO GND AND MASTER PULLS TO SLAVE'S V OL. NA: NOT ACKNOWLEDGE CMD: COMMAND BYTE RESLO: LEAST SIGNIFICANT 8-BIT RESULT RESHI: MOST SIGNIFICANT 8-BIT RESULT Figure 0. Typical Read/Write Word Command Maxim Integrated 5

16 configuring the MAX668 s command byte by performing a write. The master can now read N consecutive bytes from the MAX668 with the first data byte being read from the register addressed by the initialized command byte (Figure 0). Packet Error Checksum (PEC) All MAX668 I 2 C packets have an optional packet error checksum (PEC). The PEC is implemented in accordance with the SMBus specification, versions. and 2. The MAX668 accepts commands with or without PEC. The PEC for device responses is optional and can be disabled in the CONFIG0 register. Applications Information Operation with Multiple Masters If the MAX668 is operated on a 2-wire interface with multiple masters, a master reading the MAX668 should use a repeated START between the write that sets the MAX668 s address pointer, and the read(s) that takes the data from the location(s) (Table 6). This is because it is possible for master 2 to take over the bus after master has set up the MAX668 s address pointer, but before master has read the data. If master 2 subsequently changes the MAX668 s address pointer, master s delayed read can be from an unexpected location. The use of multiple masters is not recommended. I2C Address Range In addition to the four MSBs (00), the I 2 C slave address includes bit A0 (set by the address input AD0) and bits A2:A (set to 0). See Table 6. Choosing Pullup Resistors I 2 C requires pullup resistors to provide a logic-high level to data and clock lines. There are tradeoffs between power dissipation and speed, and a compromise must be made in choosing pullup resistor values. Every device connected to the bus introduces some capacitance even when the device is not in operation. I 2 C specifies a minimum 300ns rise time to go from low to high (30% to 70%) for fast mode, which is defined for a date rate of 400kbps (refer to the I 2 C specifications for details). To meet the rise time requirement, choose pullup resistors so that the rise time t R = 0.85R PULLUP x C BUS < 300ns. For typical TOP VIEW PECI AGND AD0 SDA PROCESS: CMOS Package Information For the latest package outline information and land patterns (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE + PACKAGE CODE MAX668 Pin Configuration µmax V REF AD AD2 GND V CC Chip Information OUTLINE NO. LAND PATTERN NO. 0 μmax U Table 6. MAX668 Slave Addresses A6:A (FIXED) A0 (SET BY AD0 PIN) I2C ADDRESS BYTE INCLUDING R/W BIT h, 55h h, 57h 6 Maxim Integrated

17 REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 0 /07 Initial release 8/07 Updated the Slave Address section and Figure 9; replaced Table 6; updated the I 2 C Address Range section 2 2/ Removed arrowhead in the line of the Typical Application Circuit; added the soldering temperature to the Absolute Maximum Ratings section; updated the Slave Address section and Figure 9; updated Table 6; updated the I 2 C Address Range, 2, 4, 6 section; added the Package Information table 3 2/ Clarified CONFIG information in Table 4 and repeated START condition 7, 3 4 5/3 Clarified that the device only supports PECI.0 (General Description, Features, and CONFIG sections), 7 4, 6 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 60 Rio Robles, San Jose, CA 9534 USA Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.