Advanced Digital Design Using FPGA. Dr. Shahrokh Abadi

Transcription

1 Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 1

2 Venue Computer Lab: Tuesdays am (Fixed) Computer Lab: Wednesday am (Every other odd weeks) Note: Due to some unpredicted problems with the lab systems, you d better to have your own Laptop with already installed Qii 14.1 web edition (get it from Altera website) with you. 2

3 References Advanced Digital Design with the Verilog HDL, Michael D. Ciletti, Pearson publisher, Some other extra notes that will be given during the term 3

4 Midterm Exam(s)**: Evaluation 1st ME: 5th Week 10 Marks 2nd ME: 10th Week 10 Marks Or only one ME: 8th Week 20 Marks Final Exam: Homework/Labwork: Mini Project based-on Verilog: Total: 20 Marks 45 Marks 20 Marks 20 Marks 105 Marks Projects are teamwork based, will be given at 10 th week and should be submitted one week before the final exam. ** The mark of ME can goes to the HW/LW+Project 4

5 Project Submission Deadline Your project must be submitted up to one week after the final exam. 1 min. to 24 hours after deadline: 50% > 24 hours after deadline: 0% No copy, No cheat, Collaboration s OK You need to submit your project including: Your name and a brief description on the procedure (MS Word) Your results; codes, diagrams, calculations, figures, altogether into a zipped file under your name must be sent to mhshahrokh@ieee.org Type FPGA-Project in the subject line Make sure you ve received a confirmation upon your submission 5

6 Chapter 02 Design using Verilog HDL Part 1 6

7 1. Introduction to HDL Hardware Description Language or HDL is any language from a class of computer languages for formal description and design of electronic circuits and digital logic HDL can describe the circuit's operation (behavior), its design and organization (structure), and tests to verify its operation by means of simulation Schematics describe only circuit structure C Language describes only behaviors Provide high level abstraction to speed up design HDL can be automatically transformed to circuits by EAD tools synthesis and optimization Can t verify the operation Enable rapid prototyping Independent of technology: support different hardware styles 7

8 1. Introduction to HDL Two most popular HDLs: Verilog and VHDL Recently, Cadence has come up with a HDL using mixed analog and digital design, called Verilog AMS. Can implement ADC, DAC, PLLs and the rest of analog circuits, and mix them with digital circuits. Verilog and VHDL can be used in circuit design ranging from SSI to VLSI: 50 transistors or less as SSI below 500 as MSIs below 5000 as LSIs beyond that as VLSIs/ULSIs Roughly, 4 or 5 transistors are considered as a 2-input NAND gate. We will be using Verilog in this course 8

9 1. Introduction to Verilog-HDL AHPL (A Hardware Programming Language) was developed to model data paths in the 70s at U. of Arizona. During the 80s, VHSIC HDL (VHDL) was jointly developed by IBM and TI under the sponsorship of DOD. IEEE standard was published for VHDL. In 2000 and 2002, the standard was revised to enhance VHDL. Original version of Verilog developed by Gateway Design Automation in Cadence popularized it later on. In 1990, Verilog was put into public domain. In 1995, IEEE standard for Verilog. In 2001, IEEE standard for an enhanced version of Verilog. 9

10 1. Introduction to Verilog-HDL Verilog has become an industry standard because of its simplicity: Quick to learn Verilog (easier than learning VHDL) It has C like structure and very fast design cycle times; i.e. you can use if, else statements, case statements, etc., and of course, there are small differences Verilog Slightly better at gate/transistor level Language style close to C/C++ Pre-defined data type, easy to use Commonly used in industry VHDL Slightly better at system level Language style close to Pascal User-defined data type, more flexible Commonly used in academic and military institutions 10

11 1. Introduction to Verilog-HDL Overall design SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE n+ D 11

12 1. Introduction to Verilog-HDL Different levels of abstraction in Verilog: System level RTL level Gate level Transistor level Physical level 12

13 1.1 Describing Logic Systems in Verilog Data-Flow Style Behavioral Style Assignments Style 13

14 2. Hardware Molding in Verilog In Verilog HDL, the basic unit of hardware is known as a module. Cannot contain definitions of other modules A module can be instantiated within another module, i.e. can be called to provide the basic mechanism for the creation of design hierarchy in a Verilog description. The hardware description is enclosed by the keywords module and endmodule All other parallel statements are fallen between these two keywords Any module has to have a name based-on some criteria List shows the basic layout of a module: 14

15 2. Hardware Molding in Verilog The BNF syntax in the Verilog is normative, which means that the syntax is part of the definition of the language. Along with this lecturer you are given an Alphabetical Reference Section of Verilog Keywords entitled a document called: Verilog Reference Guide. Please check all the keywords including: Syntax Rules Synthesis and the related Example During the course we use some of the keywords occasionally 15

16 3. Keywords in Verilog Comments (green color) // to the end of the line. /* to */ across several lines Keywords are lower case letter Verilog language is case sensitive Identifiers (names) Must begin with alphabetic or underscore characters a-z A-Z _ May contain the characters a-z A-Z 0-9 _ and $ Should not be a Verilog Keyword Identifier Notes adder legal identifier name XOR uppercase identifier, differes from xor keyword 1adder illegal identifier!!! _adder legal identifier name wire illegal identifier; preserved Verilog keyword!!! 16

17 Logic Values 3. Keywords in Verilog The Verilog HDL does have 4 logic values: Logic Value Description 0 zero, low, or false 1 one, high, or true Z or z high impedance (tri-stated or floating) X or x unknown or uninitialized 17

18 3. Keywords in Verilog Numbers in Verilog are specified as below: <size><base format><number> Size: contains decimal digitals that specify the size of the constant in the number of bits Base format: is the single character followed by one of the following characters b or B (binary),d or D (decimal),o or O (octal),h or H (hex) Number: legal digital Example : 347 // decimal number 4 b101 // 4- bit binary number o12 // 2-bit octal number 5 h87f7 // 5-bit hex number h87f7 2 d83 // 2-bit decimal number 18

19 3. Keywords in Verilog Numbers in Verilog (Classwork: 30 sec): Determine the Size, the Base, and the Binary Equivalent of the following numbers: Number Size (bits) Base Binary Equivalent 10 unsized decimal (32-bits) 'o7 unsized octal (32-bits) 1'b1 1 binary 1 8'Hc5 8 hex hF0 6 hex (truncated) 7'hF 7 hex (zero filled) 5'hZ 5 hex ZZZZZ (Z filled) Note: There are Literal Real Numbers but beyond the scope of this course. 19

20 3. Keywords in Verilog Numbers in Verilog (Classwork: 30 sec): Determine the Binary Equivalent of the following numbers: Number 8 b1x0 8 h0z 8 hzx 8 bx0 Binary Equivalent x0 0000zzzz zzzzxxxx x0 Note: There are Literal Real Numbers but beyond the scope of this course. 20

21 3. Keywords in Verilog Arithmetic Operators +, -, *, /, % (the modulus operator) Relational Operators: Operator a < b a > b a <= b a >= b Description a less than b a greater than b a less than or equal to b a greater than or equal to b The result is a scalar value (example a < b) 0 if the relation is false (a is bigger then b) 1 if the relation is true ( a is smaller then b) x if any of the operands has unknown x bits (if a or b contains x) 21

22 Equality Operators: Case Equality Logical Equality 3. Keywords in Verilog Operator a===b a!==b a==b a!=b Description a equal to b, including x and z (Case equality) a not equal to b, including x and z (Case inequality) a equal to b, result may be unknown (logical equality) a not equal to b, result may be unknown (logical equality) 22

23 4. Structural Modeling in Verilog Logical Operators: Operator Description! logic negation && logical and logical or Expressions connected by && and are evaluated from left to right Evaluation stops as soon as the result is known The result is a scalar value: 0 if the relation is false 1 if the relation is true x if any of the operands has x (unknown) bits 23

24 4. Structural Modeling in Verilog Bit-wise Operators: Operator Description ~ negation & and inclusive or ^ exclusive or ^~ or ~^ exclusive nor (equivalence) 24

25 3. Keywords in Verilog Module Port Declarations: <port direction> [port size] <port name>, <port name>,... ; port direction: input for scalar or vector input ports. output for scalar or vector output ports. inout for scalar or vector bi-directional ports. Examples input a,b,sel; output [7:0] result; inout [0:15] data_bus; input [15:12] addr; parameter word = 32; input [word-1:0] addr; Notes 3 scalar ports little endian convention big endian convention msb:lsb may be any integer constant expressions may be used 25

26 4. Structural Modeling in Verilog Primitives: Due to technology dependence and synthesis limitation, Transistor Level is not cover in this course Logic Gates and or xor nand nor xnor Buffers buf bufif0 bufif1 not notif0 notif1 pulldown pullup Transistors nmos pmos cmos rnmos rpmos rcmos tran tranif0 tranif1 rtran rtranif0 rtranif1 26

27 4. Structural Modeling in Verilog wire vs reg wire is used to two points it s used for designing combinational logic therefore cannot store a value. reg can store values If a value is assigned to reg type of signal, value will retain until a new value is assigned. it can be used for modeling both combinational and sequential logic reg data type can be driven from initial and always block (we will be covered later) 27

28 4. Structural Modeling in Verilog A half adder Module name Module ports module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; wire c_out_bar; xor Gate1 (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule Instance name Declaration of port modes Declaration of internal signal Instantiation of primitive gates a b sum c_out_bar Verilog keywords c_out 28

29 5. Continuous Assignment in Verilog Half Adder: module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; assign { c_out, sum } = a + b; // Continuous assignment endmodule a b Add_half sum c_out 29

30 6. Data Flow Behavioral Description Half Adder: module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; reg sum, c_out; ( a or b ) begin sum = a ^ b; // Exclusive or c_out = a & b; // And end endmodule 30

31 7. Hierarchical Design Start from building primitives pmos, nmos, NOT, DFF, AND, OR, etc. Then building small blocks 4-1 MUX, 3-8 Decode, Half Add, etc. Then building small modules 8-bit adders, register file, multiplier, etc. Then building units fixed-point unit, router, etc. Finally put units into a chip 31

32 8. Examples D Type Flip Flop module Flip_flop ( q, data_in, clk, rst ); input data_in, clk, rst; output q; reg q; data_in clk rst q ( posedge clk ) begin if ( rst == 1) q = 0; else q = data_in; end endmodule Declaration of synchronous behavior Procedural statement 32

33 9. Homeworks Can you realize Schmitt trigger and open collector buffers/inverters using Verilog? If so, explain how. If not, what do you suggest for their implementation? What are the possible applications for them? 33

34 9. Homeworks Tristate buffers can be implemented in Verilog using primitive gates. Write Verilog codes for circuits given below: (i) Octal tristate buffers (ii) Octal tristate inverters (iii) Octal tristate bi-directional buffers 34

35 9. Homeworks Parity generator/checker is commonly used to detect errors in high-speed serial data communication. Even parity output, OP, goes high when an even number of data inputs among I0 through I7 are high. Write a Verilog code to implement such an even parity generator using primitive gates. 35

36 Next Session How Does Quartus II work?!! Design Flow of Behavioral Model Continue Design and Simulation with Combinational and Sequential using ALTERA, Quartus II First Development on the Developer Board 36