18~ lls RI. 2ft R. \ '2.0. <013 L-r (.,3!<-I. III DO. 0 I :") C)06Ii.I(J-t I ='> :2- J 10 Rfo /.1 S I \ \. 1 J. 4'2.. '2.) '34 P-o '2..

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1 ECE2020 Test 2 Summer 2012 GTL Name: k.ey June 27, 2013 Calculators not allowed. Show your work for any possible partial credit or in some cases for any credit at all. Note the last page shows you some blank K maps just jn case you need them on this exam. 8 pages, possible 100 points. Problem 1 Part A (l0 points) Convert the following notations: Binary representation Hexidecimal representation QO LOl l om J c..95 Signed Binary two's complement represented Decimal '3.rS Decimal Octal 673 1'2..4-\ Decimal Notation Binary notation \ \. \ \ DO. 0 :") C)06i.(J-t ='> G 00. -:=>.') '3 + + V. '. 2 -= -, S -; 1. '" <013 L-r (.,3!<- f. 8 2, P-o 2- r l faa () 4'2.. '2.) '34 P-o 1..1, " o D '2..) \ R \ S :2- J 10 Rfo "2.. lls R '2.0 o 0 2ft R. \ 18 /.1 S \ \. 1 J 'f.. 2 _ 1

2 Problem 1 Part B (15 points) For the 24 (and 20) bit representations below, determine the most negative value, most positive value, and step size (difference between sequential values). All answers must be expressed in decimal notation. Fractions (for example 31l6ths) may be used. All signed representations are two's complement signed numbers. represen tati on most negative value most positive value step size unsigned integer (24 bits). (0 bits) 0 bm \ \ Signed integer -8M BM - \, (24 bits). (0 bits) unsigned fixed-point (17 bits). (7 bits) 0 \ '181< - '{'2 '!''l 9 signed fixed-point (15 bits). (5 bits) _1" k 110 l< - Y2.. 1/32 VN 'S' (,NSO '2." 10 1(P r\ = 2. - \ 2.. 2? -\ S \ Cr-. N '=\.) 1'1- \ N- \,$ ' '2. 2 -' :) +0 -:!. ") - '2.. 2 '2 -h. 1.22_1 2..."'- 2c) '2..r- 2./J _ /' "t-.> 9J11\-1, 17 ) 1 t '2 2 '2. - ', '2..'5 \- \.., \ '">- S - &- "To '- '2.. ::::) 2

3 Problem 2 Part A Arithmetic (5 points) For each problem below, compute the operations using the rules ofarithmetic, and indicate whether an overflow occurs assuming all numbers are expressed using a six bit unsigned representation ')'" \ 0 0 0, \ result o\\\q() C\ unsigned error? Y N Problem 2 Part B Arithmetic (10 points) For each problem below, compute the operations using the rules of arithmetic, and indicate whether an overflow occurs assuming all numbers are expressed using a six bit signed two's complement representations. \ \ \ D 0 0 \ \) 00 () Dol result \.) \) ()' \ D()()Uol 0\\\0\ 1,\ ll signed error? \ \ \ (J \ \ o 0 10 Ql> ()i 06, t. 6 )..., +- \ ouu\o\ \ a () \, i, \ 0\\ \ \ () c>o o \ \ o \, 0 \, 0 \ () 3

4 3) Given the circuit below: a) (5 points) The designer wants to implement an exclusive-or function where out = Y exclusive-or X. Fill in the values for F3 F2 F Fo to implement the desired exclusive-or function. b) (5 points) The designer wants to implement the NAND function where out = Y NAND X. Fill in the values for F3 F2 FFo to implement the desired NAND function. C) (5 points) The designer wants to implement the NOR function where out = Y NOR X. Fill in the values for F3 F2 FFo to implement the desired N OR function. function desired: a) exclusive-or b) NAND c) NOR Fl F2 F C \ () 0 Fo y f.. () C c 0 D F3 (:) CJ (;) \ F\ F"L po t:1- -Oil l'p rjo{ Q OUT Fa y x 4

5 C.OV tv", "5E'<ft JENe..E 4) Counters (15 points) Connect the needed toggle cells below to build a multiple digit counter (like in an alarm clock type application) that counts in the following strange 2 digit sequence nclude any circuitry needed to allow this to work. The toggle cells in the right column are for (le the least significant digit (right value), the toggle cells in the left column are for the most D \ significant digit (left value). nclude an active high count enable (CE) and an active high reset f 00 (RESET) inputs. desired count sequence: 00, 01, 02, 03, 04, 10, 11, 12, 13, 14, 20, 21, 22, 23, 24, 30, 31, 32, 33, 34, 40,41,42, 43, 44,00,01, 02, 03, 04, 10, j\+is S A Vlul S S E,TO< ANo OUT :J mp9< TE (:.ou,...,- r;-pum r L.\ 9 1&1 /CLR J ON.' C!(> foj'r F -lau '#- oj "'4- c... F Oil e.o rl+ D 6- T 5 <,;" o(y\,o C.Uu... '\ Po""t vat.. ucr Or=- 4- TE /5 r-- /CLR OUT l1d - l!d E,x.,.- c <ov",-r (>rot,.,l(" <:lu...,lt is '> il>,.,.. TE - /CLR OUT ----r----' TE OUT r- /CLR \ tyll"")< )<'\::'i!",\'-- C 1"1", LfT' slfr al l t'nf) "'A)C TE OUT... /CLR :S -F))... L TE OUT E-)CT C. =- (..0"',..,.,... '''i (>.6., /CLR N\A-)(... V fll tr"" <:: <Jo.JNT" ( N Uf"-) 00,.... N ote ' 5

6 5) Pliority Encoders (15 points) Given the truth table for the following plioity encoder: TN3 TN2 N TNO X 1 0 X X X 1 X X 0 0 OUT OUTO VALD X X a) List the priority order ofthe inputs N3, N2, TNl, NO: ::J:f' \ > ::fn1..- > :+rj () >.:f1\l highest lowest b) Using basic gates (AND, OR, NAND, NOR, NOT) show the gate level implementation for this priority encoder. DoT \ :: :rt'll NO -\--.:r"., A...'1.-- /""" \ \ t \ t \ \ \ 1 _\./'-..J --- ::TN l::j -;f N L> ;;:;.. ;tn\ v p...,p :::.::.t.j3 +- TN'l- -+ -:rt-j ) :icn 6 s",...e- f\s :. fi\ :rnch-":f"t ) fll... \ '0 -::. ;;:;'3, L., Tv 0 --D0P- vs i N (,. N"N :r"' 3 ;r,..? :.-.." -l>b 7NO - 1)o -- 0 VAL,'" 1)!1 N3,,,,.1.. ) \.-\ )J tr[) ' '" 0 6

7 6) Registers (15 points) Consider the register implementation below. A OUT N n Out n Our L.:tlh L ad } E1 Ell W E e1kl clk2 Assume the following signals are applied to your register. Draw the signal at point A (output of the first latch), the signal at point OUT (output of second latch). Assume A and OUT start at unknown values. Clkl Clk2 WE N A k 1 V. t f erl..lz1i---,".m---","--,,-.lt OUT 2 : Z Z / 27 Z7 j 7

8 KMAPS: /B B /A } /e e A /e /D D /D /B B /A { A { t--r--i L----L_-'-----:''-----:-' /e e /e /B B /A A { {r------r-----, 8