FSM-based Digital Design using Veriiog HDL
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1 FSM-based Digital Design using Veriiog HDL Peter Minns lan Elliott Northumbria University, UK John Wiley & Sons, Ltd
2 Contents Preface Acknowledgements xi xv 1 Introduction to Finite-State Machines and State Diagrams for the Design of Electronic Circuits and Systems Introduction Learning Material Summary 21 2 Using State Diagrams to Control External Hardware Subsystems Introduction Learning Material Summary 38 3 Synthesizing Hardware from a State Diagram Introduction to Finite-State Machine Synthesis Learning Material Summary 66 4 Synchronous Finite-State Machine Designs Traditional State Diagram Synthesis Method Dealing with Unused States Development of a High/Low Alarm Indicator System Testing the Finite-State Machine using a Test-Bench Module Simple Waveform Generator Sampling Frequency and Samples per Waveform The Dice Game Development of the Equations for the Dice Game 81
3 ii Contents 4.6 Binary Data Serial Transmitter The RECounter Block in the Shift Register offigure Development of a Serial Asynchronous Receiver Finite-State Machine Equations Adding Parity Detection to the Serial Receiver System To Incorporate the Parity Ö-Type Equations for Figure An Asynchronous Serial Transmitter System Equations for the Asynchronous Serial Transmitter ClockedWatchdog Timer D Flip-Flop Equations Output Equation Summary The One Hot Technique in Finite-State Machine Design The One Hot Technique A Data Acquisition System A Shared Memory System Fast Waveform Synthesizer Specification A Possible Solution Equations for the d Inputs to D Flip-Flops Output Equations Controlling the Finite-State Machine from a Microprocessor/Microcontroller A Memory-Chip Tester Comparing One Hot with the more Conventional Design MethodofChapter A Dynamic Memory Access Controller Flip-Flop Equations Output Equations How to Control the Dynamic Memory Access from a Microprocessor Detecting Sequential Binary Sequences using a Finite-State Machine Summary Introduction to Verflog HDL A Brief Background to Hardware Description Languages Hardware Modelling with Verflog HDL: the Module Modules within Modules: Creating Hierarchy Verflog HDL Simulation: a Complete Example 155 References Elements of Verflog HDL Built-In Primitives and Types 163
4 Contents iii Verflog Types Verflog Logic and Numeric Values Specifying Values Verflog HDL Primitive Gates Operators and Expressions Example Illustrating the Use of Verflog HDL Operators: Hamming Code Encoder Simulating the Hamming Encoder 188 References Describing Combinational and Sequential Logic using Verilog HDL The Data-Flow Style of Description: Review of the Continuous Assignment The Behavioural Style of Description: the Sequential Block Assignments within Sequential Blocks: Blocking and Nonblocking Sequential Statements Describing Combinational Logic using a Sequential Block Describing Sequential Logic using a Sequential Block Describing Memories Describing Finite-State Machines Example 1: Chess Clock Controller Finite-State Machine Example 2: Combination Lock Finite-State Machine with Automatic Lock Feature 252 References Asynchronous Finite-State Machines Introduction Development of Event-Driven Logic Using the Sequential Equation to Synthesize an Event Finite-State Machine Short-cut Rule Implementing the Design using Sum of Product as used in a Programmable Logic Device Dropping the Present State n and Next State n + 1 Notation Development of an Event Version of the Single-Pulse Generator with Memory Finite-State Machine Another Event Finite-State Machine Design from Specification through to Simulation ImportantNote! A Motor Controller with Fault Current Monitoring The Hover Mower Finite-State Machine The Specification and a Possible Solution An Example with a Transition without any Input Unusual Example: Responding to a Microprocessor-Addressed Location An Example that uses a Mealy Output Tank Water Level Control System with Solutions An Example using a Relay Circuit 296
5 iv Contents 9.12 Race Conditions in an Event Finite-State Machine Race between Primary Inputs Race between Secondary State Variables Race between Primary and Secondary Variables Wait-State Generator for a Microprocessor System Development of an Asynchronous Finite-State Machine for a Clothes Spinner System Caution when using Two-Way Branches Summary 312 References Introduction to Petri Nets Introduction to Simple Petri Nets Simple Sequential Example using a Petri Net Parallel Petri Nets Another Example ofa Parallel Petri Net Synchronizing Flow in a Parallel Petri Net Enabling and Disabling Ares Synchronization of Two Petri Nets using Enabling and Disabling Ares Control of a Shared Resource A Serial Receiver of Binary Data Equations for the First Petri Net Output Equations for the Main Petri Net Outputs The Shift Register Equations for the Shift Register The Divide-by-11 Counter The Data Latch Summary 336 References 336 Appendix A: Logic Gates and Boolean Algebra Used in the Book 337 A. 1 Basic Gate Symbols Used in the Book with Boolean Equations 337 A.2 The Exclusive OR and Exclusive NOR 338 A.3 Laws of Boolean Algebra 338 A.3.1 Basic ORRules 339 A.3.2 Basic AND Rules 339 A.3.3 Associative and Commutative Laws 340 A.3.4 Distributive Laws 340 A.3.5 Auxiliary Law for Static 1 Hazard Removal 341 A Proofof Auxiliary Rule 341 A.3.6 Consensus Theorem 342 A.3.7 The Effect of Signal Delay in Logic Gates 343 A.3.8 De Morgan's Theorem 343
6 Contents v A.4 Examples of Applying the Laws of Boolean Algebra 345 A.4.1 Example: Converting AND-OR to NAND 345 A.4.2 Example: Converting AND-OR to NOR 345 A.4.3 Logical Adjacency Rule 345 A.5 Summary 346 Appendix B: Counting and Shifting Circuit Techniques 347 B. 1 Basic Up and Down Synchronous Binary Counter Development 347 B.2 Example for a 4-Bit Synchronous Up-Counter Using T-Type Flip-Flops 349 B.3 Parallel-Loading Counters: Using TFlip-Flops 352 B.4 Using D Flip-Flops to Build Parallel-Loading Counters with Cheap Programmable Logic Devices 353 B.5 Simple Binary Up-Counter: with Parallel Inputs 354 B.6 Clock Circuit to Drive the Counter (And Finite-State Machines) 355 B.7 Counter Design using Don't Care States 355 B.8 Shift Registers 357 B.9 Asynchronous Receiver Details of Chapter B.9.1 The 11-Bit Shift Registers for the Asynchronous Receiver Module 360 B.9.2 Divide-by-11 Counter 362 B.9.3 Complete Simulation of the Asynchronous Receiver Module of Chapter B.10 Summary 365 Appendix C: Tutorial on the Use of Verilog HDL to Simulate a Finite-State Machine Design 367 C. 1 Introduction 367 C.2 The Single Pulse with Memory Synchronous Finite-State Machine Design: Using Verilog HDL to Simulate 367 C.2.1 Specification 367 C.2.2 Block Diagram 367 C.2.3 State Diagram 368 C.2.4 Equations from the State Diagram 368 C.2.5 Translation into a Verilog Description 369 C.3 Test-Bench Module and its Purpose 372 C.4 Using SynaptiCAD's VeriLogger Extreme Simulator 376 C.5 Summary 378 Appendix D: Implementing State Machines using Verilog Behavioural Mode 379 D.l Introduction 379 D.2 The Single-Pulse/Multiple-Pulse Generator with Memory Finite-State Machine Revisited 379 D.3 The Memory Tester Finite-State Machine in Section D.4 Summary 386 Index 387
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