Review: Chip Design Styles

Transcription

1 MPT-50 Introduction to omputer Design SFU, Harbour entre, Spring 007 Lecture 9: Feb. 6, 007 Programmable Logic Devices (PLDs) - Read Only Memory (ROM) - Programmable Array Logic (PAL) - Programmable Logic Array (PLA) Implementing Boolean unction using PLDs Wired-AND and Wired-OR buses What does Programmable Logic Mean? Programming = speciying the interconnections between gates, usually within arrays o OR and AND gates. Programming Technologies: Fuse Every input is connected through a use to the gate By blowing the uses connecting a and d we implement bc.* Notation: a b c d x x * We assume a disconnected input signal carries: or an AND gate 0 or an OR gate Review: hip Design Styles Full custom - the entire design o the chip down to the smallest detail o the layout is perormed Expensive Justiiable only or dense, ast chips with high sales volume Standard cell - blocks have been design ahead o time or as part o previous designs Intermediate cost Less density and speed compared to ull custom Gate array - regular patterns o gate transistors that can be used in many designs built into chip - only the interconnections between gates are speciic to a design Lowest cost Less density compared to ull custom and standard cell What does Programmable Logic Mean? (cont ) Other programming technologies: Antiuse Mask programming Single bit storage element haracterization o programming technologies: Permanent once set cannot be changed Reprogrammable Volatile programming lost once electric power is o Non-volatile Erasable Electrically erasable Flash (as in Flash Memory)

2 Why Programmable Logic? Facts: It is most economical to produce an I in large volumes Many designs required only small volumes o Is Need an I that can be: Produced in large volumes Handle many designs required in small volumes A programmable logic part can be: made in large volumes programmed to implement large numbers o dierent low-volume designs Types o PLDs General structure o a PLD: x x x Types o PLDs: Device And-array Or-array ROM Fixed Programmable PAL Programmable Fixed PLA Programmable Programmable Programmable Logic - Additional Advantages Many programmable logic devices are ieldprogrammable, i. e., can be programmed outside o the manuacturing environment Most programmable logic devices are erasable and reprogrammable. Allows updating a device or correction o errors Allows reuse the device or a dierent design - the ultimate in reusability! Ideal or course laboratories Programmable logic devices can be used to prototype design that will be implemented or sale in regular Is. omplete Intel Pentium designs were actually prototype with specialized systems based on large numbers o VLSI programmable devices! Read Only Memory Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have: N input lines, M output lines, and N decoded minterms. Fixed AND array with N outputs implementing all N-literal minterms. Programmable OR Array with M outputs lines to orm up to M sum o minterm expressions. A program or a ROM or PROM is simply a multiple-output truth table I a entry, a connection is made to the corresponding minterm or the corresponding output I a 0, no connection is made an be viewed as a memory with the inputs as addresses o data (output values), hence ROM or PROM names!

3 Read Only Memory (cont ) ROM components can be urther classiied: ROM: programmed during manuacture and cannot be changed. Programmable ROM (PROM): can be programmed once by the user and cannot reprogrammed aterwards. Erasable PROM (EPROM): reprogrammable. Its initial condition can be restored by exposure to ultraviolet light, or by connecting it to high voltage (Electrically Erasable PROM, EEPROM or E PROM). Writing and erasing EPROMs is much slower than reading. Programmable Logic Array (PAL) PAL has a programmable AND-array and ixed OR-array Example: 4 inputs outputs 8 product terms o at most 4 literals sums: o product terms o product terms Use this PAL to implement (x,y,z)= m (,,4,5,7) (x,y,z)= m (0,,,5,7) A ixed connection determined by the manuacturer o the PAL Read Only Memory Example Example: A 8 4 ROM (N = input lines, M= 4 output lines) The ixed "AND" array is a decoder with inputs and 8 outputs implementing minterms. The programmable "OR array uses a single line to represent all inputs to an OR gate. An in the array corresponds to attaching the minterm to the OR Read Example: For input (A,A,A 0 ) = 0, output is (F,F,F,F 0 ) = 00. What are unctions F, F, F and F 0 in terms o (A, A, A 0 )? A B A A A0 D7 D6 D5 D4 D D D D0 F F F F0 Example: Programmable Array Logic (x,y,z)= m (,,4,5,7) (x,y,z)= m (0,,,5,7) ( x, y, z ) = xy + xz + yz + xyz ( x, y, z ) = z + xz Since in a straight-orward way the PAL can implement sums o at most three product terms, we write: = + yz + xyz = z + = xy xz + xz

4 Example: Programmable Array Logic (cont ) = = = xy z + yz + xyz + xz + xz all inputs are connected Using a ROM would require implementing all the minterms PAL does not guarantee all possible Boolean unctions can be implemented. Programmable Logic Array Example A B What are the equations or F and F? ould the PLA implement the unctions without the OR gates? A B B A Fuse intact Fuse blown 4 A B -input, -output PLA with 4 product terms B B A A 0 F F Programmable Logic Array (PLA) In PLA both the AND-array and OR-array are programmable n x p x m PLA: For greater lexibility every output is available in its complemented orm as well. Programmable Logic Array The set o unctions to be implemented must it the available number o product terms The number o literals per term is less important in itting Since output inversion is available, terms can implement either a unction or its complement For small circuits, K-maps can be used to visualize product term sharing and use o complements For larger circuits, sotware is used to do the optimization including use o complemented unctions

5 Example Implement the ollowing unctions using a x 4 x PLA: F (A,B,)= m (0,,,4) F (A,B,)= m (0,5,6,7) Speciy the PLA connections by a PLA table: = connection with variable 0 = connection with complement - = no connection T/ = which orm o output Wired-AND and Wired-OR Buses Implementing the medium-scale integrated (MSI) circuits we mentioned (decoders, encoders, multiplexers, LPDs) require ANDing and ORing o many signals. AND/OR gates with large an-in consume more power, are more expensive, and might not be available. Solutions: Tree o gates. Wired-AND and Wired-OR buses. Programmable Logic Array Example A B AB A B Fuse intact + Fuse blown A B 4 B B A A 0 AB + A + B F AB + A + A B F Implementing Logic Gates using Switches The technological implementation o logic gates is done using transistors that implement switches. A switch is connected to wires: A control signal () wire endpoints that can be connected by the switch (A,B) We deine two types o switches: P switch Switch status N switch Switch status 0 connected 0 disconnected disconnected connected

6 Implementing Logic Gates using Switches (cont ) Examples. Building an inverter B=Ā. Building a NAND gate Z=NAND(A,B) -State Bus It is possible to connected several outputs o -state gates, as long as only one o them writes to the common output (=BUS). To guarantee this we can use a decoder. This component (BUS+decoder) is actually a 4-to- multiplexer 4-to- multiplexer -State Inverter We deine a new gate using switches: Enable=: Inverter Enable=0: No logic value assigned to B! In this case we say the value o B is Hi-Z. The gate is called -state inverter Pull-Down and Pull-Up Gates To remove the need or a decoder we deine new gates based on the NOT gate: IN= OUT=0 IN=0 OUT=Hi-Z IN=0 OUT= IN= OUT=Hi-Z

7 Wired-AND BUS onnecting several pull-down gates to a common output results in a Wired-AND Bus ( i at least one output is then the value on the bus is 0, otherwise ). This device guarantees in case every IN i =0 IN= OUT=0 IN=0 OUT=Hi-Z The implemented unction is NOR (or AND o the complements) Wired-OR BUS onnecting several pull-up gates to a common output results in a Wired-OR Bus ( i at least one output is 0 then the value on the bus is, otherwise 0 ). This device guarantees 0 in case every IN i = IN=0 OUT= IN= OUT=Hi-Z The implemented unction is NAND (or OR o the complements)