GRE Architecture Session
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1 GRE Architecture Session Session 2: Saturday 23, 1995 Young H. Cho www: Y. H. Cho Page 1 Review n Homework n Basic Gate Arithmetics n Bubble Pushing n Logic Design n Complex Digital Circuits Y. H. Cho Page 2
2 Logic Design & Complex Circuits n Karnaugh-Map K-MAP n Design with 4+ Variables n Debounced Flip-Flop (D-FF) n Culmination of small design concept Y. H. Cho Page 3 Computer n What is your idea? n RISC (Reduced Instruction Set Computer) n CISC (Complex Instruction Set Computer) n RISC versus CISC - Robot arm Analogy Y. H. Cho Page 4
3 Computer - Parts n Control n Datapath n Memory n Input n Output Y. H. Cho Page 5 Interconnections n BUS MBus Mem Bus SCSI External Bus n Network LAN (Local Area Network) WAN (Wide Area Network) Y. H. Cho Page 6
4 Memory Hierarchy n Registers n Cache n Main Memory n Disk n Tape Y. H. Cho Page 7 Performance n 1 / Execution Time n CPI = Cycles per program/instruction Count per Program n MIPS = Instruction Count / (Time X 10^6) = Clock rate / (CPI X 10^6) n MFLOPS = Floating point operation / (Time X 10^6) n Benchmarks Y. H. Cho Page 8
5 Benchmarks n SPEC - System Performance Evaluation Cooperative n CPU time = (Instr / Prog) X (Cycles / Instruction) X (Sec / Cycle) n Amdahl s Law Speedup(w/Enhancement) = (Exec Time without Enh) / (Exec Time with Enh) Y. H. Cho Page 9 Instruction Set Architecture (ISA) n Stack operands on top of stack n Accumulator one operand is implicitly the accumulator n General Purpose Register n Register/Memory only explicit operands - either memory or registers acess memory as part of any instruction n Load/Store Y. H. Cho Page 10
6 ISA History n Single Accumulator EDSAC: 1950 n Accumulator + Index Registers Manchester Mark I, IBM 700 series 1953 n Separation of Programming Model from Implementation High-level Language Based (B5000: 1963) Concept of a Family (IBM 360: 1964) n General Purpose Register Machines Y. H. Cho Page 11 Complex Instruction Sets (VAX Intel 432: Pipeline n Laundry Example n Evident Speedup n Patch things up - compiler tricks and hardware tricks Y. H. Cho Page 12
7 Basic Technology n Complementary Metal Oxide Silicon (CMOS) transistors NMOS Turns on when High (Vdd, 5V) is applied Turns off when Low (Gnd, 0V) is applied (Analogy: Opens the gate at the hill to let the water flow. Gate controlled by stream of water - Water applied to gate controls the gate.) PMOS Turns off when High (Vdd, 5V) is applied Turns on when Low (Gnd, 0V) is applied Y. H. Cho Page 13 Gate Comparison n If PMOS transistor is faster: NOR gate is preferred NMOS in Series PMOS in Parallel H to L is more critical than L to H n If NMOS transistor is faster: NAND gate is preferred NMOS in Parallel PMOS in Series Y. H. Cho Page 14 L to H is more critical than H to L
8 Summary n Performance Measurements n Instruction Set Architecture: Stack Accumulator General Purpose Register: Register/Memory Load/Store Y. H. Cho Page 15 Outline n Performance n ISA n Technology n ALU n Computer Arithmetics Binary Arithmetics Floating point Arithmetics n Single cycle and pipelines Y. H. Cho Page 16
9 Common Sense: 5 Basic Components n Datapath n Control n Memory n Input n Output Y. H. Cho Page 17 I. Performance n Comments: Important to Keep this mind when evaluating benchmarks n Speedup - Amdahl's Law n Compiler Problem - MIPS and CPI n Equations Y. H. Cho Page 18
10 II. ISA n Comments: Many different Architecture n Stack n Accumulator n General Purpose Register: n Register/Memory n Load/Store Y. H. Cho Page 19 III. Technology n Comments: Real issue in hardware implementations n CMOS technology n Internal Delay n Cycle time Y. H. Cho Page 20
11 IV. Arithmetic Logic Unit (ALU) n Comments: Basic intelligent unit implementations n Carry-Look-Ahead n Carry Select Y. H. Cho Page 21 V. Computer Arithmetics n Binary Standard n Multiplication Booths n Floating point (IEEE Standard) n Multiply, Shift, and FP Number n Comments: Important to know the concept IEEE 31 / / 22-0 Y. H. Cho Page 22 (-1)^s * (1+significand) x 2^(exponent-bias)
12 VI. Single Cycle and Pipeline Datapath n Datapath n Draw your idea of what Computer is n Block diagram Y. H. Cho Page 23
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