Embarquez votre Intelligence Artificielle (IA) sur CPU, GPU et FPGA
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1 Embarquez votre Intelligence Artificielle (IA) sur CPU, GPU et FPGA Pierre Nowodzienski Engineer 2018 The MathWorks, Inc. 1
2 From Data to Business value Make decisions Get valuable knowledge Artificial Intelligence Extract information Data analysis Generate raw data End devices 2
3 Artificial Intelligence opportunities in «Internet of Everything» world Amount of data Transport cost High latency Availability CLOUD Energy cost 3
4 Artificial Intelligence opportunities in «Internet of Everything» world CLOUD Mission Real-time analytics Local control center Operational Intelligence Do the right thing at the right place Today webinar focus: How can we design and deploy Neural Networks on embedded targets? Global control center Business intelligence SWaP-C High Medium Low Latency Very Low Low - Medium High 4
5 Embedded targets & mitigations Efficiency (performance/watt) C/C++ programing language Sequential processing High Code generation CUDA/ OpenCL programing language Partly parallel processing Code generation VHDL/Verilog programing language Partly parallel processing Low Low Development productivity Code generation High 5
6 MathWorks workflows: Neural Network to embedded targets Artificial Neural Network Design & Training Trained Convolutional or DAG Network design logic First part: Deploying Deep Neural Network GPU Coder Dataset Train the Network Trained Shallow Neural Network logic Embedded Coder HDL Coder Second part: Deploying Shallow Neural Network ANSI/ISO compliant ASIC 6
7 Deep Learning is a Subset of Machine Learning Machine Learning Deep Learning 7
8 Algorithm Design to Embedded Deployment Workflow logic Build type MATLAB algorithm (functional reference) Call CUDA from MATLAB directly Desktop GPU Call CUDA from (C++) handcoded main() Desktop GPU Embedded GPU Call CUDA from (C++) hand-coded main()..mex.lib Cross-compiled.lib C++ C++ 1 Functional test 2 Deployment unit-test 3 Deployment integration-test 4 Real-time test 8
9 Demo: Alexnet Deployment with mex Code Generation 9
10 Algorithm Design to Embedded Deployment on Tegra GPU logic Build type MATLAB algorithm (functional reference) Call CUDA from MATLAB directly Tesla GPU Call CUDA from (C++) handcoded main() Tesla GPU Tegra GPU Call CUDA from (C++) hand-coded main(). Cross-compiled on host with Linaro toolchain.mex.lib Cross-compiled.lib C++ C++ 1 Functional test 2 Deployment unit-test 3 Deployment integration-test 4 Real-time test (Test in MATLAB on host) (Test generated code in MATLAB on host + GPU) (Test generated code within C/C++ app on host + GPU) (Test generated code within C/C++ app on Tegra target) 10
11 Alexnet Deployment to Tegra: Cross-Compiled with lib Two small changes 1. Change build-type to lib 2. Select cross-compile toolchain 11
12 Deploying to CPUs logic GPU Coder Desktop CPU NVIDIA TensorRT & cudnn Libraries Raspberry Pi board 12
13 GPU Coder for Deployment GPU Coder Intel MKL-DNN Library ARM Compute Library Deep Neural Networks Deep Learning, machine learning Image Processing and Computer Vision Image filtering, feature detection/extraction Signal Processing and Communications FFT, filtering, cross correlation, 5x faster than TensorFlow 2x faster than MXNet 60x faster than CPUs for stereo disparity 20x faster than CPUs for FFTs 13
14 MathWorks workflows: Neural Network to embedded targets Artificial Neural Network Design & Training Trained Convolutional or DAG Network design logic GPU Coder Dataset Train the Network Trained Shallow Neural Network logic Embedded Coder HDL Coder Second part: Deploying Shallow Neural Network ANSI/ISO compliant ASIC 14
15 Demo: Shallow network deployment on Zynq platform Neural network as gas emission estimator (sensorless) Speed command Fuel Rate Engine Engine torque Gas emission Shallow Neural Network Estimated torque Estimated gas emission 15
16 Demo workflow Iterate Create the Network structure Train the Network Test the Network Export to Simulink Fine-tune & optimize for the target Generate code 16
17 Demo summary Iterate Create the Network structure Train the Network Test the Network Export to Simulink Fine-tune & optimize for the target Generate code Neural Network Toolbox Parallel Computing Toolbox Fixed Point Designer HDL Coder Embedded Coder 17
18 HDL Optimization options Area Optimizations HDL Coder with Simulink Streaming Sharing Line buffers as RAMs RAM Fusion Architecture Flattening Efficient resource mapping HDL Coder with MATLAB RAM Mapping Loop Streaming Resource Sharing CSD/FCSD Speed Optimizations HDL Coder with Simulink Input/Output pipelining Distributed Pipelining Hierarchical Dist. Pipelining Constrained Pipelining Clock-Rate Pipelining Back-Annotation Adaptive Pipelining HDL Coder with MATLAB Input/Output pipelining Distributed pipelining Loop Unrolling Workflow and Verification HDL Workflow Advisor Automatic Delay Balancing Validation model generation 18
19 Key takeaways Comprehensive & integrated development environment from dataset to target Fast design space exploration and trade-off Target-independant functional reference for target-optimized implementation model Deploy «Smart application», not Neural network only 19
20 MathWorks workflows: Neural Network to embedded targets Artificial Neural Network Design & Training Trained Convolutional or DAG Network design logic GPU Coder Dataset Train the Network logic Embedded Coder HDL Coder ANSI/ISO compliant ASIC Trained Shallow Neural Network 20
21 Next steps Web site technical resources Lookup Table Optimization Data Type Optimization (documentation) Efficient Implementation on FPGAs (documentation) Deep Learning Inference for Object Detection on Raspberry Pi Pedestrian Detection on a NVIDIA GPU with TensorRT Contact us pierre.nowodzienski@mathworks.fr Special thanks to Vaidehi Venkatesan (Fixed-Point Designer development team) for her great job to create this demo material! 21
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