LY62L K X 16 BIT LOW POWER CMOS SRAM
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1 REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul Rev. 1.1 Revised Package Outline Dimension(TSOP-II) Apr Rev. 1.2 Added ISB1/IDR values when TA = 25 and TA = 40 Added S grade Deleted grade Revised FEATURES & ORDERING INFORMATION ead free and green package available to Green package available Added packing type in ORDERING INFORMATION Revised VTERM to VT1 and VT2 Deleted TSODER in ABSOUTE MAXIMUN RATINGS Mar Rev. 1.3 Revised PACKAGE OUTINE DIMENSION in page 10 May Rev. 1.4 Revised ORDERING INFORMATION in page 11 Aug Rev. 1.5 Rephrased WRITE CYCE Notes 1,2 of TIMING WAVEFORMS in page 8 May Rev. 1.6 Correct ORDERING INFORMATION Typo. May Rev. 1.7 Revised PIN DESCRIPTION in page 1 Mar Revised TEST CONDITION /TYP. /MAX. of ICC Revised toe in AC EECTRICA CARACTERISTICS May
2 FEATURES Fast access time : 45/55/70ns ow power consumption: Operating current : 17/14/11mA (TYP.) Standby current : 1µA (TYP.) /S -version Single 2.7V ~ 3.6V power supply All inputs and outputs TT compatible Fully static operation Tri-state output Data byte control : B# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.5V (MIN.) Green package available Package : 44-pin 400mil TSOP II 48-ball 6mm x 8mm TFBGA GENERA DESCRIPTION The is a 2,097,152-bit low power CMOS static random access memory organized as 131,072 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TT compatible. PRODUCT FAMIY Product Operating Power Dissipation VCC Range Speed Family Temperature Standby(ISB1,TYP.) Operating(ICC,TYP.) 0 ~ ~ 3.6V 45/55/70ns 1µA 17/14/11mA (E) -20 ~ ~ 3.6V 45/55/70ns 1µA 17/14/11mA (I) -40 ~ ~ 3.6V 45/55/70ns 1µA 17/14/11mA FUNCTIONA BOCK DIAGRAM PIN DESCRIPTION Vcc Vss SYMBO A0 - A16 DESCRIPTION Address Inputs A0-A16 DECODER 128Kx16 MEMORY ARRAY DQ0 - DQ15 WE# Data Inputs/Outputs Chip Enable Input Write Enable Input OE# Output Enable Input B# ower Byte Control UB# Upper Byte Control DQ0-DQ7 ower Byte DQ8-DQ15 Upper Byte I/O DATA CIRCUIT COUMN I/O VCC VSS NC Power Supply Ground No Connection WE# OE# B# UB# CONTRO CIRCUIT 1
3 PIN CONFIGURATION A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 Vcc Vss DQ4 DQ5 DQ6 DQ7 WE# A16 A15 A14 A13 A XXXXXXXX XXXXXXXX A5 A6 A7 OE# UB# B# DQ15 DQ14 DQ13 DQ12 Vss Vcc DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC TSOP II A B# OE# A0 A1 A2 NC B DQ8 UB# A3 A4 DQ0 C D E F DQ9 DQ10 A5 Vss DQ11 NC Vcc DQ12 NC DQ14 DQ13 A14 A6 A7 A16 A15 DQ1 DQ3 DQ4 DQ5 DQ2 Vcc Vss DQ6 XXXXXXXX XXXXXXXX G DQ15 NC A12 A13 WE# DQ7 NC A8 A9 A10 A11 NC TFBGA (See through with Top View) TFBGA (Top View) 2
4 ABSOUTE MAXIMUN RATINGS* PARAMETER SYMBO RATING UNIT Voltage on VCC relative to VSS VT1-0.5 to 4.6 V Voltage on any other pin relative to VSS VT2-0.5 to VCC+0.5 V 0 to 70(C grade) Operating Temperature TA -20 to 80(E grade) -40 to 85(I grade) Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W DC Output Current IOUT 50 ma *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUT TABE MODE OE# WE# B# UB# X Standby X X Output Disable Read X Write X X Note: = VI, = VI, X = Don't care. X X X X X X I/O OPERATION DQ0 - DQ7 DOUT DOUT DIN DIN DQ8 - DQ15 DOUT DOUT DIN DIN SUPPY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 3
5 DC EECTRICA CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. *4 MAX. UNIT Supply Voltage VCC V Input igh Voltage VI * VCC+0.3 V Input ow Voltage VI * V Input eakage Current II VCC VIN VSS µa Output eakage VCC VOUT VSS, IO Current Output Disabled µa Output igh Voltage VO IO = -1mA V Output ow Voltage VO IO = 2mA V Average Operating Power supply Current Standby Power Supply Current ICC ICC1 Cycle time = MIN. = 0.2V and CE2 VCC-0.2V, II/O = 0mA Other pins at 0.2V or VCC - 0.2V Cycle time = 1µs = 0.2V, II/O = 0mA Other pins at 0.2V or VCC - 0.2V ma ma ma ma ISB = VI, other pins at VI or VI ma µa E/I µa ISB1 VCC - 0.2V Others at 0.2V or VCC - 0.2V S *5 SE *5 SI * µa µa S µa SE/SI µa Notes: 1. VI(max) = VCC + 3.0V for pulse width less than 10ns. 2. VI(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = This parameter is measured at V CC = 3.0V CAPACITANCE (T A = 25, f = 1.0Mz) PARAMETER SYMBO MIN. MAX. UNIT Input Capacitance CIN - 6 pf Input/Output Capacitance CI/O - 8 pf Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse evels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference evels 1.5V Output oad C = 30pF + 1TT, IO/IO = -1mA/2mA 4
6 AC EECTRICA CARACTERISTICS (1) READ CYCE PARAMETER SYM MIN. MAX. MIN. MAX. MIN. MAX. UNIT Read Cycle Time trc ns Address Access Time taa ns Chip Enable Access Time tace ns Output Enable Access Time toe ns Chip Enable to Output in ow-z tcz* ns Output Enable to Output in ow-z toz* ns Chip Disable to Output in tcz* ns Output Disable to Output in toz* ns Output old from Address Change to ns B#, UB# Access Time tba ns B#, UB# to Output tbz* ns B#, UB# to ow-z Output tbz* ns (2) WRITE CYCE PARAMETER SYM MIN. MAX. MIN. MAX. MIN. MAX. UNIT Write Cycle Time twc ns Address Valid to End of Write taw ns Chip Enable to End of Write tcw ns Address Set-up Time tas ns Write Pulse Width twp ns Write Recovery Time twr ns Data to Write Time Overlap tdw ns Data old from End of Write Time td ns Output Active from End of Write tow* ns Write to Output in twz* ns B#, UB# Valid to End of Write tbw ns *These parameters are guaranteed by device characterization, but not production tested. 5
7 TIMING WAVEFORMS READ CYCE 1 (Address Controlled) (1,2) Address trc taa to Dout Previous Data Valid Data Valid READ CYCE 2 ( and OE# Controlled) (1,3,4,5) Address trc taa B#,UB# tace OE# tba tbz tcz toz toe to toz tbz tcz Dout Data Valid Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, = low, B# or UB# = low. 3.Address must be valid prior to or coincident with = low, B# or UB# = low transition; otherwise taa is the limiting parameter. 4.tCZ, tbz, toz, tcz, tbz and toz are specified with C = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tcz is less than tcz, tbz is less than tbz, toz is less than toz. 6
8 WRITE CYCE 1 (WE# Controlled) (1,2,3,5,6) twc Address taw tcw tbw B#,UB# tas twp twr WE# twz tow Dout (4) (4) tdw td Din Data Valid WRITE CYCE 2 ( Controlled) (1,2,5,6) twc Address taw tas twr B#,UB# tbw tcw twp WE# Dout twz (4) tdw td Din Data Valid 7
9 WRITE CYCE 3 (B#,UB# Controlled) (1,2,5,6) twc Address taw twr B#,UB# tas tcw tbw twp WE# Dout (4) twz tdw td Din Data Valid Notes : 1.A write occurs during the overlap of a low, low WE#, B# or UB# = low. 2.All address transitions should not occur during the write period. 3.During a WE# controlled write cycle with OE# low, twp must be greater than twz + tdw to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the, B#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and twz are specified with C = 5pF. Transition is measured ±500mV from steady state. 8
10 DATA RETENTION CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. MAX. UNIT VCC for Data Retention VDR VCC - 0.2V V µa E/I µa Data Retention Current IDR S VCC = 1.5V, VCC - 0.2V µa SE Others at 0.2V or VCC-0.2V SI µa S µa SE/SI µa Chip Disable to Data Retention Time tcdr See Data Retention Waveforms (below) ns Recovery Time tr trc* - - ns trc* = Read Cycle Time DATA RETENTION WAVEFORM ow VCC Data Retention Waveform (1) ( controlled) VDR 1.5V Vcc Vcc(min.) Vcc(min.) tcdr tr VI Vcc-0.2V VI ow VCC Data Retention Waveform (2) (B#, UB# controlled) VDR 1.5V Vcc Vcc(min.) Vcc(min.) tcdr tr B#,UB# VI B#,UB# Vcc-0.2V VI 9
11 PACKAGE OUTINE DIMENSION 44-pin 400 mil TSOP Ⅱ Package Outline Dimension SYMBOS DIMENSIONS IN MIMETERS DIMENSIONS IN MIS MIN. NOM. MAX. MIN. NOM. MAX. A A A b c D E E e ZD y Θ 0 o 3 o 6 o 0 o 3 o 6 o 10
12 48-ball 6mm 8mm TFBGA Package Outline Dimension 11
13 ORDERING INFORMATION Package Type 44-pin (400mil) TSOP II Access Time (Speed)(ns) 45 Special 55 Special 70 Special Power Type Ultra ow Power Temperature Range( ) Packing Type yontek Item No. 0 ~70 Tray M-45S M-45ST -20 ~80 Tray M-45SE M-45SET -40 ~85 Tray M-45SI M-45SIT Ultra ow Power 0 ~70 Tray M-45 Ultra ow Power M-45T -20 ~80 Tray M-45E M-45ET -40 ~85 Tray M-45I M-45IT 0 ~70 Tray M-55S M-55ST -20 ~80 Tray M-55SE M-55SET -40 ~85 Tray M-55SI M-55SIT Ultra ow Power 0 ~70 Tray M-55 Ultra ow Power M-55T -20 ~80 Tray M-55E M-55ET -40 ~85 Tray M-55I M-55IT 0 ~70 Tray M-70S M-70ST -20 ~80 Tray M-70SE M-70SET -40 ~85 Tray M-70SI M-70SIT Ultra ow Power 0 ~70 Tray M-70 M-70T -20 ~80 Tray M-70E M-70ET -40 ~85 Tray M-70I M-70IT 12
14 ORDERING INFORMATION Package Type 48-ball (6mm x 8mm) TFBGA Access Time (Speed)(ns) 45 Special 55 Special 70 Special Power Type Ultra ow Power Temperature Range( ) Packing Type yontek Item No. 0 ~70 Tray G-45S G-45ST -20 ~80 Tray G-45SE G-45SET -40 ~85 Tray G-45SI G-45SIT Ultra ow Power 0 ~70 Tray G-45 Ultra ow Power G-45T -20 ~80 Tray G-45E G-45ET -40 ~85 Tray G-45I G-45IT 0 ~70 Tray G-55S G-55ST -20 ~80 Tray G-55SE G-55SET -40 ~85 Tray G-55SI G-55SIT Ultra ow Power 0 ~70 Tray G-55 Ultra ow Power G-55T -20 ~80 Tray G-55E G-55ET -40 ~85 Tray G-55I G-55IT 0 ~70 Tray G-70S G-70ST -20 ~80 Tray G-70SE G-70SET -40 ~85 Tray G-70SI G-70SIT Ultra ow Power 0 ~70 Tray G-70 G-70T -20 ~80 Tray G-70E G-70ET -40 ~85 Tray G-70I G-70IT 13
15 TIS PAGE IS EFT BANK INTENTIONAY. 14
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