Gate level or structural modeling
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1 Gate level or structural modeling Prerequisites Functioning of basic logic gates and basic understanding of Verilog coding is required. You are suggested to complete the previous unit before starting this unit. Suggested Time Gate Level Modeling requires around 4-5 hours. Motivation Gate-level modeling is virtually the lowest-level of abstraction. Although there is a lower level of abstraction known as switch-level abstraction, this is impractical to use for most systems and is rarely used. In general, gate-level modeling is used for implementing the lowest level modules in a design like, full-adder, multiplexers, etc. Verilog has gate primitives for all basic gates. Learning Objectives After finishing this module, you will be able to 1. Interpret the meaning of Gate-level modeling/structural modeling and its importance 2. Design circuits in Verilog using basic gates like AND, OR, Buffer, NOT type gates. 3. Analyze delay modeling of the circuit and analyze gate level behavior. Introduction In this module, we will discuss a design at a low level of abstraction, i.e., Gate Level. At gate level, the circuit is described in terms of gates (e.g., AND gate, NAND gate). Elementary gates are the building blocks of all
2 digital circuits - whether combinational, sequential, or involved version combining both. Conversely, any digital circuit can be split up into constituent elementary gates. Hardware design at this level is intuitive for a user with a basic knowledge of digital logic design because it is possible to see a one-to-one correspondence between the logic circuit diagram and the Verilog description. Therefore we start with gate-level modeling and move to higher levels of abstraction in the succeeding modules. Gate Primitives Gate primitives are predefined in Verilog, which are ready to use. They are instantiated like modules. There are two classes of gate primitives: Multiple input gate primitives and Single input gate primitives. Multiple input gate primitives include and, nand, or, nor, xor, and xnor. These can have multiple inputs and a single output. Single input gate primitives include not, buf, notif1, bufif1, notif0, and bufif0. These have a single input and one or more outputs. Some gate primitives like: notif1, bufif1, notif0, and bufif0 also have a control signal. Examples on gate primitives use are given below // Two input AND gate. and and_1 (out, in0, in1); // Three input NAND gate. nand nand_1 (out, in0, in1, in2);
3 // Three input NOR gate. nor nor_1 (out, in0, in1,in2); // Four input NOR gate. nor nor_1 (out, in0, in1, in2, in3); // Five input XOR gate. xor xor_1 (out, in0, in1, in2, in3, in4); In the first example and is the name of gate primitive and and_1 is the name given for reference. This name is optional and it is only for reference purposes. in0and in1 are 2 inputs and out is the output of the and module. The complete list of gate primitives is given below.
4 Gate level modeling refers to the ability to describe the circuit as a net list of primitive logic gates and functions. The gates have one scalar output and multiple scalar inputs. Gate Delays In Verilog, a designer can specify the gate delays in a gate primitive instance. This helps the designer to get a real time behavior of the logic circuit. Rise delay: It is equal to the time taken by a gate output transition to 1, from another value 0, x, or z. Fall delay: It is equal to the time taken by a gate output transition to 0, from another value 1, x, or z. Turn-off delay: It is equal to the time taken by a gate output transition to high impedance state, from another value 1, x, or z. If the gate output changes to x, the minimum of the three delays is considered. If only one delay is specified, it is used for all delays. If two values are specified, they are considered as rise, and fall delays. If three values are specified, they are considered as rise, fall, and turn-off delays. The default value of all delays is zero. Examples:
5 1. and #(2) and_1 (out, in0, in1); // All delay values are 2 time units. 2. nand #(1,2,3) nand_1 (out, in0, in1); // rise delay = 1, fall delay = 2, and turn-off delay = or #(3,4) or_1 (out, in0, in1); // rise delay = 3, fall delay = 4, and turn-off delay = min(3,4) = 3. There is another way of specifying delay times in Verilog, Min: Typ: Max values for each delay. This helps the designer to have a much better real time experience of design simulation, as in real time logic circuits the delays are not constant. The user can choose one of the delay values using +maxdelays, +typdelays, and +mindelays at run time. The typical value is the default value. Examples 1. and #(4:5:6) and_1 (out, in0, in1); // For all delay values: Min=4, Typ=5, Max=6. 2. nand #(3:4:5,4:5:6,5:6:7) nand_1 (out, in0, in1); // rise delay: Min=3, Typ=4, Max=5, fall delay: Min=4, Typ=5, Max=6, turn-off delay: Min=5, Typ=6, Max=7. In the above example, if the designer chooses typical values, then rise delay = 4, fall delay = 5, turn-off delay = 6.
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