Topics. FPGA Design EECE 277. Interconnect and Logic Elements Part 2. Laboratory Assignment #1 Save Everything!!! Guest Lecture

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1 FPGA Design EECE 277 Interconnect and Logic Elements Part 2 Dr. William H. Robinson February 4, Topics The sky is falling. I must go and tell the King. Chicken Little Guest lecture Philippe Adell Administrative stuff Laboratory Assignment #1 (due Monday, February 7) Issues with Laboratory Assignment #1 Homework Assignment #3 (due Monday, February 14) PLEASE do the tutorials in Appendix B, C, and D of the textbook Using LUTs Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (HDL) 1 2 Guest Lecture Presentations on current FPGA research Philippe Adell Implementing a Rad-Hard digital power controller with an FPGA philippe.c.adell@vanderbilt.edu Potential Final Project Ideas!!! Laboratory Assignment #1 Save Everything!!! Your data is in the reports Consider separate folders for each problem Moving the LE cell (Prob. 11) The fitter sometimes gives strange results Retargeting to the MAX chip (Prob. 13) Just use the S/W; do not worry about jumper wires Macrocell for Adder (Prob. 15) Follow the spirit of the problem Set up I/O ports with bus signals 3 4

2 FPGA Fabric (Architecture) Logic Interconnect I/O pins Evaluation of SRAM-based LUT N-input LUT can handle function of 2 n input combinations All logic functions take the same amount of space All functions have the same delay SRAM is larger than static gate equivalent of function Burns power at idle Fundamentals of Digital Logic: Chapter 3 Copyright 2005 McGraw-Hill 5 FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR 6 Example: Using LUTs Brown/Vranesic 3.45 Consider the function: f (x 1, x 2, x 3 ) = Σ m(2, 3, 4, 6, 7) Show how it can be realized using two 2-input LUTs Example: Using LUTs x 1 x 1 f f x 2 x 2 Fundamentals of Digital Logic: Chapter 3 Copyright 2005 McGraw-Hill 7 Fundamentals of Digital Logic: Chapter 3 Copyright 2005 McGraw-Hill 8

3 Technology Mapping Cover the function Each additional gate used costs area FPGA Technology Mapping Cost (number of inputs) Doesn t always increase with added functions INV AOI21 INV FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR 9 FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR 10 Custom Logic vs. FPGAs Mapping into an FPGA Cost metric for static gates is literal ax + bx has four literals, requires 8 transistors Cost metric for FPGAs is logic element All functions that fit in an LE have the same cost Must choose the FPGA Capacity Pinout/package type Maximum speed FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR 11 FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR 12

4 LUT-Based Logic Synthesis Find the largest logic cone that will fit into the LUT r r = q + s q = g + h s = d Terminology Support: set of variables used by a function Transitive fan-out: all the primary outputs and intermediate variables of a function Transitive fan-in: all the primary inputs and intermediate variables used by a function Transitive fan-in determines a cone of logic. d = a + b primary inputs cone output g h a b FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR 13 FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR 14 Combinational Logic Networks Non-Functional Requirements Functionality Size Determines manufacturing cost Other requirements Size Power/energy Performance Primary inputs Combinational logic Primary outputs Power/energy Energy related to battery life, power related to heat Many digital systems are power-limited or energy-limited Performance Clock speed is generally a primary requirement FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR 15 FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR 16

5 Hardware Description Languages Hardware Description Languages Structural description A connection of components Functional description A set of Boolean formulas, state transitions, etc. A Textual languages for describing hardware Structure Function Simulation description A program designed for simulation Major languages Verilog VHDL x NAND Most people today use textual languages rather than schematics for most digital design Schematics (transistor or gate-level) make poor use of screen space Still may use block diagrams for higher levels FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR 17 FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR 18 Summary All functions that fit in an LE have the same cost Functions are first minimized then mapped into corresponding LEs VHDL uses either a structural or behavioral description of the function 19