NAND Flash Module DESCRIPTION: FEATURES: 69F12G24, 69F24G24

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1 Module FEATURES: High density 12 Gb or 24 Gb Based on 4 Gb x8 NAND flash die Supports higher speed designs with less capacitance/fewer I/O's to drive NAND Flash Interface Single Level Cell (SLC) Technology ONFI 1.0 Compliant Operating Voltage VCC V Page Size 2112 bytes ( spare bytes). Includes internal BCH correction algorithms (4 bit correction per 528 bytes) Features High reliability data storage for demanding space applications Ceramic hermetic package with built-in TID shielding Three separate flash memory banks, supports TMR error correction Class E, I, H or K Speed Asynch: Up to asynch timing mode 5 (50MT/sec) Temperature Range -55 ⁰C to 125⁰C Endurance 100,000 cycles DESCRIPTION: DDC s 12 Gb and 24 Gb high density NAND flash features a x24 wide bus, which can also be used to TMR three banks of 4 Gb x8 NAND flash die. This NAND flash uses Single-Level Cell (SLC) NAND technology. Storing 1 bit of data per memory cell, SLC NAND offers fast read and write capabilities and boot times, excellent endurance and reliability, and has on-die ECC algorithms enabling advanced security features and data corruption protection. DDC s patented RAD-PAK packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding, while providing the required radiation shielding for a lifetime in orbit or space mission. RAD-PAK provides a greater than 100 krads(si) total dose tolerance, depending on space mission. This product is available with screening up to DDC Microelectronics self-defined Class K.

2 Supported Commands: Reset FFh - Get Features EEh - Set Features EFh - Read Status 70h - Read Status Enchanced (Multi-LUN) 78h - Random Read Data 05h E0h Change Read Column Enhanced 06h E0h Random Data Input 85h - Read Mode 00h - Read Page 00h 30h Read Page Interleaved 00h 00h, 30h Read Page Cache Sequential * 31h - Read Page Cache Random * 00h 31h Read Page Cache Last * 3Fh - Program Page 80h 10h Program Page Interleaved 80h 11h-85h,10h Program Page Cache * 80h 15h Erase Block 60h D0h Erase Block Interleaved 60h D1h Copyback Read 00h 35h Copyback Program 85h 10h Copyback Program Interleaved 85h 11h Read Unique ID EDh - Read Parameter Page ECh - Read ID 90h - * These commands supported with internal ECC disabled Not Supported Non-sequential page programming 16 bit data bus width per Target/LUN Extended ECC Synchronous Mode: clock stopped for data input Rev 1 All data sheets are subject to change without notice 2

3 Array Organization Cycle DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Second L L L L CA11 CA10 CA9 CA8 Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0 Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 Fifth L L L L L LUN/BA18 BA17 BA16 CA[n] = Column Address PA[n] = Page Address BA[n] = Bank Address LUN = Logical Unit Address Row Address = LUN, Bank, Page Address BA[6] = Plane Select Column Addresses above 2111 are invalid (page size = ) Memory Organization Bytes per page: 2048 Spare ECC bytes per page: 64 Pages per block: 64 Blocks per LUN: 4096 LUNs per chip enable: 2 Column address cycles: 2 Row address cycles: 3 Bits per cell: 1 Programs per page: 4 Number of bits ECC required: 1 (for 512 Bytes) Number of interleave address bits: Rev 1 All data sheets are subject to change without notice 3

4 Package Organization 12Gb x 24 Architecture Independent 8 bit buses per package: 3 DQ[7-0]-1 CE#-1 Targets per 8 bit bus: 1 WE-1#/CLK-1 LUNS per Target: DQS-1 (1 die per 8 bit bus) (3 die per package) DQ[7-0]-2 CE#-2 WE#-2/CLK-2 DQS-2 DQ[7-0]-3 Shared CE#-3 WE#-3/CLK-3 DQS-3 ALE RE#, W/R# CLE WP# RB# Rev 1 All data sheets are subject to change without notice 4

5 Package Organization 24Gb x 24 Architecture Independent 8 bit buses per package: 3 DQ[7-0]-1 CE#-1 Targets per 8 bit bus: 1 WE-1#/CLK-1 LUNS per Target: 2 DQS-1 (2 die per 8 bit bus) (6 die per package) DQ[7-0]-2 CE#-2 WE#-2/CLK-2 DQS-2 DQ[7-0]-3 CE#-3 WE#-3/CLK-3 DQS-3 Shared ALE RE#, W/R# CLE WP# RB# Rev 1 All data sheets are subject to change without notice 5

6 DC Characteristics (VCC = 3.0 to 3.6V, TC = -55 to +125 ⁰C) Subgroup ( 1,2,3) Description Symbol Condition Min Max Units VCC Active Read array current (per die) ICC1_A trc = trc min; CE#=VIL; Iout = 0mA - 35 ma VCC Program array Current (per die) ICC2_A - 35 ma VCC Active Erase Current (per die) ICC3_A - 35 ma Icc Standby ( TTL) (per die) ISB1H CE# = VIH ua Icc Standby (CMOS) (per die) ISB2 CE# = VCC-0.2V ua Individual Input leakage current, (per die), Note 2 ILL VIN = 0V to V CC na Individual Output leakage current, (per die) OLL VIN = 0V to V CC na Input high voltage VIH 0.8 x V CC V CC +.3V V Input low voltage, all inputs VIL -.3V 0.2 x V CC V Output Voltage, min limit is for VCC= 3V(note 1) VOH IOH = -400uA 0.67 x V CC - V Output Voltage, max limit is for VCC= 3V (note 1) VOL IOH = 2.1mA mv Output low current, (note 2) IOL_RB0 VOL = 0.4V 8 - ma Note 1: Limits valid for full drive strength Note 2: RE,CLE,ALE,WE0,WE1,WE2,CE0,CE1,CE2,WP AC Characteristics Command (VCC = 3.0 to 3.6V, TC = -55 to +125 ⁰C) Subgroup ( 9, 10, 11) Description Symbol Min Max Units ALE to data start tadl 70 - ns ALE hold time talh 5 - ns ALE setup time tals 10 - ns CE# hold time tch 5 - ns CLE hold time tclh 5 - ns CLE setup time tcls 10 - ns CE# setup time tcs 15 - ns Data hold time tdh 5 - ns Data setup time tds 7 - ns WRITE cycle time twc 20 - ns WE# pulse width HIGH twh 7 - ns WE# pulse width twp 10 - ns WP# transition to WE# LOW (note 2) tww ns Note 1: Test Condition, not measured. Note 2: Not Tested Rev 1 All data sheets are subject to change without notice 6

7 AC Characteristics Data (VCC = 3.0 to 3.6V, TC = -55 to +125 ⁰C) Subgroup ( 9, 10, 11) Description Symbol Min Max Units ALE to RE# delay tar 10 - ns CE# access time tcea - 25 ns CE# HIGH to output High -Z tchz - 50 ns CLE to RE# delay tclr 10 - ns CE# HIGH to output hold tcoh 15 - ns Output High-Z to RE# LOW (note 2) tir 0 - ns READ cycle time (note 1) trc 20 - ns RE# access time trea - 16 ns RE# HIGH hold time treh 7 - ns RE# HIGH to output hold trhoh 15 - ns RE# HIGH to WE# LOW trhw ns RE# HIGH to output High-Z trhz ns RE# LOW to output hold trloh 5 - ns RE# pulse width trp 10 - ns Ready to RE# LOW trr 20 - ns Reset time (READ) measured, (PROGRAM/ERASE) note 1 trst - 5/10/100 us WE# HIGH to busy twb ns WE# HIGH to RE# LOW twhr 60 - ns Note 1: Test Condition, not measured. Note 2: Not Tested Note 3: All timing parameters may need to be relaxed if I/O strength is not set to full Program Erase Characteristics (VCC = 3.0 to 3.6V, TC = -55 to +125 ⁰C) Subgroup ( 9, 10, 11) Description Symbol Min Max Units Number of partial-page programs (note 2) NOP - 4 cycles Erase block operation time tbers us Busy time for program cache operation tcbsy us Cache read busy time (note 1) trcbsy - 25 us Busy time for SET/GET FEATURES operations tfeat - 1 us Program page operation time no ECC tprog us Program page operation time with ECC enabled tprog_ecc us Data transfer from Flash array to data register, ECC disabled tr - 25 us Data transfer from Flash array to data register, ECC enabled tr_ecc - 70 us Busy time for TWO-PLANE PROGRAM PAGE or TWO-PLANE BLOCK ERASE (note 1) tdbsy - 1 us Note 1: Test Condition, not measured. Note 2: Not Tested Rev 1 All data sheets are subject to change without notice 7

8 Absolute Maximum Ratings Description Symbol Min Typical Max Units Voltage Input VIN V VCC Supply voltage VCC V Storage temperature TSTG C Weight RP LID W grams Weight RT LID W grams Tjc Tjc C/W Operating Conditions Description Symbol Min Max Units Temperature Trng C VCC VCC V Valid Blocks Description Symbol Min Max Units Valid Blocks -Beginning of Life NVB Blocks ECC for Block 0; bit errors per 528 bytes - 1 bit errors per 528 B ECC for Blocks >0; bit errors per 528 bytes - 2 bit errors per 528 B Delta Parameters Description Symbol Delta Change VCC Active Read array current (per die) ICC1_A 10% of DS limit VCC Program array Current (per die) ICC2_A 10% of DS limit VCC Active Erase Current (per die) ICC3_A 10% of DS limit Icc Standby (TTL) (Six Die) ISB1H 10% of DS limit Icc Standby (CMOS) (six die) ISB2 10% of DS limit Rev 1 All data sheets are subject to change without notice 8

9 Rev 1 All data sheets are subject to change without notice 9

10 Pinout Description Pin # Pin # Description VCC 1 70 VCC VSS 2 69 VSS CLE 3 68 DQ16 CE# DQ17 CE# DQ18 CE# DQ19 VCC 7 64 VCC VSS 8 63 VSS WE# DQ20 RB# DQ21 WE# DQ22 VCC DQ23 VSS VCC WE# VSS RE# NC ALE VCC VCC VSS VSS WP# DNC NC VCC VCC VSS VSS DQ DQ15 DQ DQ14 DQ DQ13 DQ DQ12 VCC VCC VSS VSS DQ DQ11 DQ DQ10 DQ DQ9 DQ DQ8 VCC VCC VSS VSS VCC VCC VSS VSS Three 8 bit buses; Each with its own CS[0-2], DQS[0-2] & WE#CLK[0-2] Three chip selects for 6 die using Multi-LUN operation. All other control signals are shared; CLE, RB#, RE#-W/R#,ALE & WP# VCCQ and VSSQ are not separated from VCC and VSS Rev 1 All data sheets are subject to change without notice 10

11 Feature Summary Description 4Gb die ONFI 1.0, 2.0, 2.1, Interleaved read operations Odd to even page copyback No Interleaved Program and erase operations Non-sequential page programming No Multiple LUN operations 16 bit data bus width per LUN No READ UNIQE ID COPYBACK READ STATUS ENHANCED GET FEATURES & SET FEATURES Read cache commands PROGRAM PAGE CACHE Number of data bytes per page 2048 Number of spare bytes per page 64 Number of bytes per partial page 512 Number of spare bytes per partial page 16 Number of pages per block 64 Number of blocks per LUN 4096 Number of LUNs per chip enable 2 Number of address cycles Column address cycles 2 Row address cycles 3 Number of bits per cell 1 Bad blocks maximum per LUN 80 Block endurance Guaranteed valid blocks at beginning 1 Block endurance for guaranteed valid blocks 0 Number of programs per page 4 Number of bits ECC correctability 4 Number of interleaved address bits 1 Interleaved address restrictions for cache operations Interleaved program cache support Interleaved block address restrictions No Overlapped/concurrent interleaving No I/O pin typical capacitance per target 20 pf/ 10pf tprog Typical (Page Program) 600 us tbers Typical (Block Erase) 3 ms tr max (Page Read) 25 us Input pin capacitance, typical 10 pf Rev 1 All data sheets are subject to change without notice 11

12 Product Ordering Options 69F XXG 24 XX F X Screening Flow: K = DDC Microelectronics Class K H = DDC Microelectronics Class H I = Industrial (testing at -55 C, +25 C, +125 C) E = Engineering (testing at +25 C) Package: F = Flat Pack Radiation Feature: RP = RAD-PAK Package Shielding RT = Kovar Lid Data Width: 24 = 24 bits wide Total Gbits: 12 = 12 Gb 24 = 24 Gb Base Product Nomenclature: 3.3V by 24 NAND FLASH SLC Rev 1 All data sheets are subject to change without notice 12