Rev. No. History Issue Date Remark

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1 128K X 8 BIT LOW VOLTAGE CMOS SRAM ocument Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue ate Remark 0.0 Initial issue February 19, 2002 Preliminary 0.1 Add 32L Pb-Free TSSOP package type October 2, Final version release July 16, 2003 Final 1.1 Change ICCR1, ICCR2 (max.) from 3μA to 1μA June 29, Add Pb-Free package type for all parts August 9, 2004 (August, 2004, Version 1.2) AMIC Technology, Corp.

2 128K X 8 BIT LOW VOLTAGE CMOS SRAM Features Power supply range: 2.7V to 3.6V Access times: 55/70 ns (max.) Current: Very low power version: Operating: 30mA(max.) Standby: 5uA (max.) Full static operation, no clock or refreshing required All inputs and outputs are directly TTL-compatible Common I/O using three-state output Output enable and two chip enable inputs for easy application ata retention voltage: 2V (min.) Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm) forward type and 36-pin CSP packages General escription The LP62S1024B-T is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a low power voltage: 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-OWN and device enable and an output enable input is included for easy interfacing. ata retention is guaranteed at a power supply voltage as low as 2V. Product Family Product Family Operating Temperature VCC Range Speed ata Retention (ICCR, Typ.) Power issipation Standby (ISB1, Typ.) Operating (ICC2, Typ.) LP62S1024B -25 C ~ +85 C 2.7V~3.6V 55ns / 70ns 0.05µA 0.08µA 1.5mA 1. Typical values are measured at VCC = 3.0V, TA = 25 C and not 100% tested. 2. ata retention current VCC = 2.0V. Package Type 32L SOP 32L TSOP 32L TSSOP 36B µbga (August, 2004, Version 1.2) 1 AMIC Technology, Corp.

3 Pin Configurations SOP TSOP/TSSOP CSP (Chip Size Package) 36-pin Top View NC 1 32 VCC A A A CE2 A WE A7 A6 A5 A4 A3 A2 A1 A0 I/O LP62S1024BM-T A13 A8 A9 A11 OE A10 I/O8 I/O7 LP62S1024BV-T (LP62S1024BX-T) A B C E F G A0 I/O5 I/O6 GN VCC I/O7 I/O8 A1 A2 OE CE2 WE NC NC A3 A4 A5 NC A16 A6 A7 A15 A8 I/O1 I/O2 VCC GN I/O3 I/O4 I/O2 I/O I/O6 I/O H A9 A10 A11 A12 A13 A14 GN I/O4 Pin No Pin Name A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 Pin No Pin Name A3 A2 A1 A0 I/O1 I/O2 I/O3 GN I/O4 I/O5 I/O6 I/O7 I/O8 A10 OE Block iagram A0 VCC GN A14 A15 ROW ECOER 512 X 2048 MEMORY ARRAY A16 I/O1 INPUT ATA CIRCUIT COLUMN I/O I/O8 CE2 OE WE CONTROL CIRCUIT (August, 2004, Version 1.2) 2 AMIC Technology, Corp.

4 Pin escriptions - SOP Pin No. Symbol escription 1 NC No Connection 2-12, 23, 25-28, , A0 - A16 I/O1 - I/O8 16 GN Ground Address Inputs ata Input/Outputs 22 Chip Enable 24 OE Output Enable 29 WE Write Enable 30 CE2 Chip Enable 32 VCC Power Supply Pin escription TSOP/TSSOP Pin No. Symbol escription 1-4, 7, 10-20, 31 A0 - A16 Address Inputs 5 WE Write Enable 6 CE2 Chip Enable 8 VCC Power Supply 9 NC No Connection 21-23, I/O1 - I/O8 24 GN Ground ata Input/Outputs 30 Chip Enable 32 OE Output Enable Pin escription - CSP Symbol escription Symbol escription A0 - A16 Address Inputs NC No Connection WE Write Enable I/O1 - I/O8 ata Input/Output OE Output Enable VCC Power Supply Chip Enable GN Ground CE2 Chip Enable (August, 2004, Version 1.2) 3 AMIC Technology, Corp.

5 Recommended C Operating Conditions (TA = -25 C to +85 C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V GN Ground V VIH Input High Voltage VCC V VIL Input Low Voltage V CL Output Load pf TTL Output Load Absolute Maximum Ratings* VCC to GN V to +4.6V IN, IN/OUT Volt to GN V to VCC +0.5V Operating Temperature, Topr C to +85 C Storage Temperature, Tstg C to +125 C Temperature Under Bias, Tbias C to +85 C Power issipation, PT W *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. C Electrical Characteristics (TA = -25 C to +85 C, VCC = 2.7V to 3.6V, GN = 0V) Symbol Parameter LP62S1024B-55LLT/70LLT Unit Conditions Min. Max. ILI Input Leakage Current - 1 µa VIN = GN to VCC ILO Output Leakage Current - 1 µa = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GN to VCC ICC Active Power Supply Current - 3 ma = VIL, CE2 = VIH, II/O = 0mA ICC1 ynamic Operating - 30 ma Min. Cycle, uty = 100% = VIL, CE2 = VIH II/O = 0mA ICC2 Current - 3 ma = VIL, CE2 = VIH VIH = VCC, VIL = 0V f = 1 MHZ, II/O = 0mA ISB ma VCC 3.3V, = VIH or CE2 =VIL ISB1 Standby Power Supply Current - 5 µa VOL Output Low Voltage V IOL = 2.1mA VOH Output High Voltage V IOH = -1.0mA VCC 3.3V, VCC - 0.2V or CE2 0.2V, VIN 0V (August, 2004, Version 1.2) 4 AMIC Technology, Corp.

6 Truth Table Mode CE2 OE WE I/O Operation Supply Current Standby H X X X High Z ISB, ISB1 X L X X High Z ISB, ISB1 Output isable L H H H High Z ICC, ICC1, ICC2 Read L H L H OUT ICC, ICC1, ICC2 Write L H X L IN ICC, ICC1, ICC2 Note: X = H or L Capacitance (TA = 25 C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pf VIN = 0V CI/O* Input/Output Capacitance 8 pf VI/O = 0V * These parameters are sampled and not 100% tested. (August, 2004, Version 1.2) 5 AMIC Technology, Corp.

7 AC Characteristics (TA = -25 C to +85 C, VCC = 2.7V to 3.6V) Symbol Parameter LP62S1024B-55LLT LP62S1024B-70LLT Unit Min. Max. Min. Max. Read Cycle trc Read Cycle Time ns taa Address Access Time ns ta Chip Enable Access Time ns tace2 CE ns toe Output Enable to Output Valid ns tclz1 Chip Enable to Output in Low Z ns tclz2 CE ns tolz Output Enable to Output in Low Z ns tchz1 Chip isable to Output in High Z ns tchz2 CE ns tohz Output isable to Output in High Z ns toh Output Hold from Address Change ns Write Cycle twc Write Cycle Time ns tcw Chip Enable to End of Write ns tas Address Setup Time ns taw Address Valid to End of Write ns twp Write Pulse Width ns twr Write Recovery Time ns twhz Write to Output in High Z ns tw ata to Write Time Overlap ns th ata Hold from Write Time ns tow Output Active from End of Write ns Notes: tchz1, tchz2, tohz, and twhz are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. (August, 2004, Version 1.2) 6 AMIC Technology, Corp.

8 Timing Waveforms (1, 2, 4) Read Cycle 1 trc Address taa toh toh OUT (1, 3, 4, 6) Read Cycle 2 ta tclz1 5 tchz1 5 OUT (1, 4, 7, 8) Read Cycle 3 CE2 tace2 tclz2 5 tchz2 5 OUT (August, 2004, Version 1.2) 7 AMIC Technology, Corp.

9 Timing Waveforms (continued) Read Cycle 4 (1) trc Address taa OE toe toh tolz 5 ta tclz1 5 tchz1 5 CE2 tace2 tohz 5 tclz2 5 tchz25 OUT Notes: 1. WE is high for Read Cycle. 2. evice is continuously enabled = VIL and CE2 = VIH. 3. Address valid prior to or coincident with transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high. 7. is low. 8. Address valid prior to or coincident with CE2 transition high. Write Cycle 1 (6) (Write Enable Controlled) twc Address taw twr 3 (4) tcw 5 CE2 (4) tas 1 twp 2 WE tw th IN twhz tow OUT (August, 2004, Version 1.2) 8 AMIC Technology, Corp.

10 Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) twc Address taw twr 3 tcw 5 tas 1 (4) CE2 (4) tcw 5 twp 2 WE tw th IN twhz 7 OUT Notes: 1. tas is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (twp) of a low, a high CE2 and a low WE. 3. twr is measured from the earliest of or WE going high or CE2 going low to the end of the Write cycle. 4. If the low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tcw is measured from the later of going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. (August, 2004, Version 1.2) 9 AMIC Technology, Corp.

11 AC Test Conditions Input Pulse Levels 0.4V to 2.4V Input Rise and Fall Time 5 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 TTL TTL CL 30pF CL 5pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tclz1, tclz2, tohz, tolz, tchz1, tchz2, twhz, and tow ata Retention Characteristics (TA = -25 C to 85 C) Symbol Parameter Min. Max. Unit Conditions VR V VCC - 0.2V VCC for ata Retention VR V CE2 0.2V, ICCR1 ata Retention Current - 1* µa VCC = 2V, VCC - 0.2V, VIN 0V ICCR2-1* µa tcr Chip isable to ata Retention Time 0 - ns tr Operation Recovery Time 5 - ms VCC = 2V, CE2 0.2V, VIN 0V See Retention Waveform * LP62S1024B-55LLT/70LLT ICCR: max. 1µA at TA = 0 C to + 40 C (August, 2004, Version 1.2) 10 AMIC Technology, Corp.

12 Low VCC ata Retention Waveform (1) ( Controlled) ATA RETENTION MOE VCC 3.0V 3.0V tcr VR 2V tr VIH VIH VR - 0.2V Low VCC ata Retention Waveform (2) (CE2 Controlled) ATA RETENTION MOE VCC 3.0V 3.0V tcr VR 2V tr CE2 VIL VIL CE2 0.2V (August, 2004, Version 1.2) 11 AMIC Technology, Corp.

13 Ordering Information Part No. Access Time (ns) Operating Current Max. (ma) Standby Current Max. (µa) Package LP62S1024BM-55LLT 32L SOP LP62S1024BM-55LLTF 32L Pb-Free SOP LP62S1024BV-55LLT 32L TSOP LP62S1024BV-55LLTF LP62S1024BX-55LLT LP62S1024BX-55LLTF LP62S1024BU-55LLT LP62S1024BU-55LLTF LP62S1024BM-70LLT LP62S1024BM-70LLTF LP62S1024BV-70LLT LP62S1024BV-70LLTF LP62S1024BX-70LLT LP62S1024BX-70LLTF LP62S1024BU-70LLT LP62S1024BU-70LLTF L Pb-Free TSOP 32L TSSOP 32L Pb-Free TSSOP 36L CSP 36L Pb-Free CSP 32L SOP 32L Pb-Free SOP 32L TSOP 32L Pb-Free TSOP 32L TSSOP 32L Pb-Free TSSOP 36L CSP 36L Pb-Free CSP (August, 2004, Version 1.2) 12 AMIC Technology, Corp.

14 Package Information SOP (W.B.) 32L Outline imensions unit: inches/mm e1 ~ E HE L 1 b 16 etail F e1 c s Seating Plane y e A1 A2 A See etail F LE Symbol imensions in inches imensions in mm A Max Max. A Min Min. A ± ±0.13 b c Typ. (0.820 Max.) Typ. (20.83 Max.) E 0.445± ±0.25 e ± ±0.15 e NOM NOM. HE 0.556± ±0.25 L 0.031± ±0.20 LE 0.055± ±0.20 S Max Max. y Max Max. θ 0 ~ 10 0 ~ 10 Notes: 1. The maximum value of dimension includes end flash. 2. imension E does not include resin fins. 3. imension e1 is for PC Board surface mount pad pitch design reference only. 4. imension S includes end flash. (August, 2004, Version 1.2) 13 AMIC Technology, Corp.

15 Package Information TSOP 32L TYPE I (8 X 20mm) Outline imensions unit: inches/mm e A A E c GAUGE PLANE A1 θ 0.25 BSC L LE H etail "A" etail "A" y S b 0.10(0.004) M Symbol imensions in inches imensions in mm A Max Max. A ± ±0.05 A ± ±0.05 b 0.008± ±0.03 c 0.006± ± ± ±0.10 E 0.315± ±0.10 e TYP TYP. H 0.787± ±0.20 L 0.020± ±0.10 LE TYP TYP. S TYP TYP. Y Max Max. θ 0 ~ 6 0 ~ 6 Notes: 1. The maximum value of dimension includes end flash. 2. imension E does not include resin fins. 3. imension e1 is for PC Board surface mount pad pitch design reference only. 4. imension S includes end flash. (August, 2004, Version 1.2) 14 AMIC Technology, Corp.

16 Package Information TSSOP 32L TYPE I (8 X 13.4mm) Outline imensions unit: inches/mm e 12.0 A2 A E c GAUGE PLANE A BSC L θ 1 LE etail "A" etail "A" 0.10MM SEATING PLANE S b Symbol imensions in inches imensions in mm A Max Max. A Min Min. A ± ±0.05 b 0.008± ±0.03 c 0.006± ±0.008 E 0.315± ±0.10 e TYP TYP ± ± ± ±0.10 L 0.02± ±0.20 LE Min Min. S TYP TYP. y Max Max. θ 0 ~ 6 0 ~ 6 Notes: 1. The maximum value of dimension includes end flash. 2. imension E does not include resin fins. 3. imension e1 is for PC Board surface mount pad pitch design reference only. 4. imension S includes end flash. (August, 2004, Version 1.2) 15 AMIC Technology, Corp.

17 Package Information 36L CSP (6 x 8 mm) Outline imensions unit: mm TOP VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER b (36X) A B C E F G H E E1 e A B C E F G H B e 1 SIE VIEW A // 0.25 C A C 0.20(4X) (0.36) C SEATING PLANE A1 A Symbol imensions in mm MIN. NOM. MAX. A A A E E e b Note: 1. THE BALL IAMETER, BALL PITCH, STAN-OFF & PACKAGE THICKNESS ARE IFFERENT FROM JEEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY ATUM C AN SEATING PLANE ARE EFINE BY THE SPHERICAL CROWNS OF THE SOLER BALLS. 3. IMENSION b IS MEASURE AT THE MAXIMUM. 4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EGE OF THE SOLER BALL AN THE BOY EGE. (August, 2004, Version 1.2) 16 AMIC Technology, Corp.

LP62S16256G-I Series. Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM. Revision History. Rev. No. History Issue Date Remark

LP62S16256G-I Series. Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM. Revision History. Rev. No. History Issue Date Remark Preliminary 256K X 16 BIT LOW VOLTAGE CMOS SRAM ocument Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue ate Remark 0.0 Initial issue June 2, 2006 Preliminary PRELIMINARY