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1 Implementation of EDDR Architecture for High Speed Motion Estimation Testing Applications A.MADHAV KUMAR #1, S.RAGAHAVA RAO #2,B.V.RAMANA #3, V.RAMOJI #4 ECE Department, Bonam Venkata Chalamayya Institute of Engineering and Technology, Amalapuram 1 madhavamk07@gmail.com 2 raghu7327@gmail.com 3 bvramana.bvcits@gmail.com 4 ramoji.btech@gmail.com ABSTRACT _Motion Estimation (ME) plays a critical role in a video coder, testing such a module is of priority concern. While focusing on the testing of ME in a video coding system, this work presents an error detection and data recovery (EDDR) design, based on the residue-and-quotient (RQ) code, to embed into ME for video coding testing applications. An error in processing Elements (PEs), i.e. key components of a ME, can be detected and recovered effectively by using the proposed EDDR design. The proposed EDDR design for ME testing can detect errors and recover data with an acceptable area overhead and timing penalty. Index Terms Area overhead, data recovery, error detection, motion estimation, reliability, residueand-quotient (RQ) code. 1. INTRODUCTION Multimedia applications are flexible and reliable when we used advances in semiconductors and communication technologies.h.264 video standard is a good example, it is also known as MPEG-4(Motion Picture Experts Group-4) Part10 Advanced Video Coding, it is widely regarded as the next generation video compression standard. Video Compression reduces the total data amount required for transmitting or storing video data which is necessary in a wide range of applications. Motion estimation (ME) explores the temporal redundancy, it is inherent in video sequences and represents a basis for lossy video compression. Other than video compression, motion estimation can also be used as the basis for powerful video analysis and video processing. A ME (motion estimation) generally consists of PEs (Processing elements) with a size of 4 x 4. Additionally, the visual quality and peak signal-to-noise ratio (PSNR) at a given bit rate are influenced if an error occurred in ME process. As a commercial chip, it is absolutely necessary for the ME to introduce design for testability (DFT). Device testing is increased by using DFT which gives high reliability of a system. DFT methods rely on reconfiguration of a circuit under test (CUT) to improve testability. Systems have meant that built-in self-test (BIST) schemes have rapidly become necessary in the digital world. BIST does not expensive test equipment, ultimately lowering test costs. The built-in testing approaches not only detect faults but also specify their locations for error correcting. Thus, BIST extended scheme referred to as built-in self-diagnosis and built-in self correction have been developed recently. The extended BIST schemes generally focus on testing-related issues, memory circuits of video coding have seldom been addressed. 2. PROPOSED EDDR ARCHITECTURE DESIGN Fig. 1 shows the proposed EDDR scheme, which depends on error detection circuit (EDC) and data recovery circuit (DRC), to detect errors and recover the corresponding data in a specific CUT. The test code generator (TCG) utilizes RQ code to generate the corresponding test codes for error detection and data recovery. DRC is in charge of recovering data from TCG and a selector is enabled to export error-free data or data-recovery results. This work adopts the systolic ME as a CUT to demonstrate the feasibility of the proposed EDDR architecture. A ME consists of many PEs (processing elements) incorporated in a 1-D or 2-D array for video encoding applications. A PE generally consists of two ADDs (i.e. an 8-b ADD and a 12-b ADD) and an accumulator (ACC). Next, the 8-b ADD (a pixel has 8-b data) is used to estimate the addition of the current pixel (Cur pixel) and reference pixel (Ref pixel). Additionally, a 12-b ADD and an ACC are required to accumulate the results from the 8- b ADD in order to determine the sum of absolute difference (SAD) value for video encoding applications [20]. Notably, some registers and latches may exist in ME to complete the data shift and storage. Fig. 2 shows an example of the proposed EDDR circuit design for a specific of a ME. Fig. 1. Conceptual view of the proposed EDDR architecture. IJCSIET-ISSUE4-VOLUME3-SERIES3 Page 1

2 which N is coded as a pair ( ). Notably, is 3. MAIN MODULES OF EDDR ARCHITECTURE the residue N of modulo m. the residue code can detect a bit error and it cannot be recovered effectively. a) PROCESSING ELEMENT Therefore quotient code is derived from residue code to b) RQ CODE GENERATION detect multiple errors and recovering errors. c) TEST CODE GENERATION d) ERROR DETECTION CIRCUIT 3c. TEST CODE GENERATIONS e) D ATA RECOVERY CIRCUIT 3a. PROCESSING ELEMENT (PE) ME consists of many PEs incorporated in a 1-D or 2-D array for video encoding applications.pe generally consists of two adders (i.e. an 8-b ADD and a 12-b ADD) and an accumulator (ACC). Next, the 8-b Adder (a pixel has 8-b data) is used to estimate the addition of the current pixel (Cur pixel) and reference pixel (Ref pixel). Additionally, a 12-b ADD and an ACC are required to accumulate the results from the 8- b ADD in order to determine the sum of absolute difference (SAD) value for video encoding applications. The specific estimates the absolute difference between the Cur pixel and Ref pixel. Thus, by utilizing PEs, SAD shown in as follows, in a macro block with size of N X N can be evaluated: In proposed EDDR architecture TCG is an important component.the design of TCG is based on the RQCG circuit to generate corresponding test codes in order to detect errors and recover data. The specific PE (processing element) estimates the absolute difference between the Cur pixel and the Ref pixel. The residue code generates the RQ code ( ) from TCG. N 1 N 1 i 0 j 0 ( q xij. m r xij ) ( q yij. m r Where, and, denote the corresponding RQ code of and modulo. 3b. RQ CODE GENERATION Coding approaches are like this as Berger code, parity code, and residue code which is destined to detect circuit errors. Residue code is a generally separable arithmetic codes which estimates residue for data and appending it to data. Separate residue code is typically derived through error detection logic for operations, which makes an easy and simply implemented. It can detect only a bit error and additionally an error cannot be recovered effectively by using the residue code. Therefore, this work presents a quotient code, it is derived from the residue code, which detect the multiple errors and recovering errors. For instance, assume that N denotes an integer, N_1and N_2 represent data words, and m refers to the modulus value. A separate residue code of interest is one in yij ) IJCSIET-ISSUE4-VOLUME3-SERIES3 Page 2 And

3 results from the DRC is selected by a multiplexer (MUX) to pass to the next species for subsequent testing. Fig. 2. A specific testing processes of the proposed EDDR architecture. 4. Numerical Example A numerical example of the 16 pixels for a 4 x 4 macroblock in a specific of a ME is described as follows. Fig. 5 presents an example of pixel values of the Cur_pixel and Ref_pixel.The SAD value of the 4 x 4 macroblock is Fig. 4. Example of pixel values. Fig. 3. Circuit design of the TCG. 3d. ERROR DETECTION CIRCIUT (EDC) The operations of error detection in a specific is achieved by using EDC, based on the outputs between TCG and in order to determine whether errors have occurred. If the values of and/or, then the errors in a specific can be detected. The EDC output is then used to generate a 0/1 signal to indicate that the tested is errorfree/errancy. = (128-1) + (128-1)+ + (128-5) = e. DATA RECOVERY CIRCUIT (DRC) DRC generates error free output by the quotient multiply with constant value and add to reminder code. During the data recovery, the circuit DRC plays a significant role in recovering RQ code from TCG. The proposed EDDR design executes the error detection and data recovery operations simultaneously and also error-free data from the tested or data recovery that IJCSIET-ISSUE4-VOLUME3-SERIES3 Page 3

4 5. CONCLUSION This work presents EDDR architecture for detecting the errors and recovering the data of PEs in a ME. By using RQ code, a RQCG-based TCG design is developed to generate the corresponding test codes to detect errors and recover data. Experimental results indicate that that the proposed EDDR architecture can effectively detect errors and recover data in PEs of a ME with reasonable area overhead and only a slight time penalty. Fig. 5. Proposed EDDR architecture design for a ME. Fig. 6 RTL diagram of proposed EDDR Fig. 7.Simulation results of proposed EDDR TABLE 1 ESTIMATION OF AREA OVERHEAD AND TIME PENALTY OPERATION TIME(ns) Number of input LUT S REFERENCES [1] Chang-Hsin Cheng, Yu Liu, and Chun-Lung Hsu, Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications, ieee transactions on very large scale integration (vlsi) systems, vol. 20, no. 4, april 2012 [2] Advanced Video Coding for Generic Audiovisual Services, ISO/IEC :2005 (E), Mar.2005, ITU- T Rec. H.264 (E). [3] Information Technology-Coding of Audio-Visual Objects Part 2: Visual, ISO/IEC ,1999. [4] Y.W.Huang, B.Y.Hsieh, S.Y.Chien, S.Y.Ma, and L.G.Chen, Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC, IEEE Trans.Circuits Syst. Video Technol., vol. 16, no. 4, pp , Apr [5] C. Y. Chen, S. Y. Chien, Y. W. Huang, T. C. Chen, T. C. Wang, and L. G. Chen, Analysis and architecture design of variable block-size motion estimation for H.264/AVC, IEEE Trans. Circuits Syst. I, Reg.Papers, vol. 53, no. 3, pp , Mar [6]T.H.Wu,Y.L.Tsai,andS.J.Chang, An efficient design-for-testability scheme for motionestimation in H.264/AVC, in Proc. Int. Symp.VLSI Design, Autom. Test, Apr. 2007, pp [7] M. Y. Dong, S. H. Yang, and S. K. Lu, Designfor-testability techniques for motion estimation computing arrays, in Proc. Int. Conf.Commun., Circuits Syst., May 2008, pp [8] Y. S. Huang, C. J. Yang, and C. L. Hsu, C-testable motion estimation design for video coding systems, J. Electron. Sci. Technol., vol. 7, no.4, pp , Dec [9] D. Li, M. Hu, and O. A. Mohamed, Built-in selftest design of motion estimation computing array, in Proc. IEEE Northeast Workshop CircuitsSyst., Jun. 2004, pp [10] Y. S. Huang, C. K. Chen, and C. L. Hsu, Efficient built-in self-test for video coding cores: A case study on motion estimation computing array, in Proc. IEEE Asia Pacific Conf. Circuit Syst., Dec. 2008, pp [11] W. Y Liu, J. Y. Huang, J. H. Hong, and S. K. Lu, Testable design and BIST techniques for systolic motion estimators in the transform domain, in Proc. IEEE Int. Conf. Circuits Syst., Apr. 2009, pp IJCSIET-ISSUE4-VOLUME3-SERIES3 Page 4

5 [12] J. M. Portal, H. Aziza, and D. Nee, EEPROM memory: Threshold voltage built in self diagnosis, in Proc. Int. Test Conf., Sep. 2003, pp [13] J. F. Lin, J. C. Yeh, R. F. Hung, and C. W. Wu, A built-in self-repair design for RAMs with 2-D redundancy, IEEE Trans. Vary Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp , Jun [14] C. L. Hsu, C. H. Cheng, and Y. Liu, Built-in selfdetection/correction architecture for motion estimation computing arrays, IEEE Trans.Vary Large Scale Integr. (VLSI) Systs., vol. 18, no. 2, pp , Feb [15] C. H. Cheng, Y.Liu, and C. L.Hsu, Low-cost BISDC design for motion estimation computing array, in Proc. IEEE Circuits Syst. Int.Conf., 2009, pp [16] S. Bayat-Sarmadi and M. A. Hasan, On concurrent detection of errors in polynomial basis multiplication, IEEE Trans. Vary Large Scale Integr.(VLSI) Systs., vol. 15, no. 4, pp , Apr [17] C. W. Chiou, C. C. Chang, C. Y. Lee, T. W. Hou, and J. M. Lin, Concurrent error detection and correction in Gaussian normal basis multiplier over GF, IEEE Trans. Comput., vol.58, no. 6, pp , Jun [18] L. Breveglieri, P. Maistri, and I. Koren, A note on error detection in an RSA architecture by means of residue codes, in Proc. IEEE Int.Symp.On-Line Testing, Jul. 2006, [19] S. J. Piestrak, D. Bakalis, and X. Kavousianos, On the design of selftesting checkers for modified Berger codes, in Proc.IEEE Int. WorkshopOn-Line Testing, Jul. 2001, pp [20] S. Surin and Y. H. Hu, Frame-level pipeline motion estimation array processor, IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 2,pp , Feb [21] D. K. Park, H. M. Cho, S. B. Cho, and J. H. Lee, A fast motion estimation algorithm for SAD optimization in sub-pixel, in Proc. Int. Symp.Integr. Circuits, Sep. 2007, pp IJCSIET-ISSUE4-VOLUME3-SERIES3 Page 5