Advantages of MIPI Interfaces in IoT Applications

Transcription

1 Advantages of MIPI Interfaces in IoT Applications IoT DevCon Conference Hezi Saar April 27, 2017

2 Abstract In addition to sensors, high-resolution cameras are key enablers of IoT devices. The challenge for IoT designers is to find a solution that delivers low power consumption and high performance, while meeting cost constraints. MIPI CSI-2 is a proven interface in the mobile market, and because of its successful implementation, it is being utilized in new applications like IoT and virtual/augmented reality devices. The new MIPI specification delivers a cost-effective solution that enables multiple sensor connectivity in a simplified architecture. This presentation defines the MIPI CSI-2 and specifications, and describes their implementation, as well as power and performance advantages in IoT SoCs Synopsys, Inc. 2

3 Agenda Implementation of MIPI interfaces in mobile applications and beyond Advantages of MIPI CSI-2, DSI,, D-PHY specifications Summary 2017 Synopsys, Inc. 3

4 MIPI Specifications in New Applications IoT / Wearables, Virtual / Augmented Reality, Automotive 2017 Synopsys, Inc. 4

5 From the Edge to the Cloud IoT Edge Devices (Smart Devices) Aggregation Layers (Hubs/Gateways) Remote Processing (Cloud Based) Things with sensors & actuators that monitor and control Connectivity & Interfaces to aggregate the edge data to send to the cloud Applications to analyze the data and offer cloud services 2017 Synopsys, Inc. 5

6 IoT Devices Getting More Complex Low DSP Processing, No Display Single Sensor Battery Life < 7 days Higher DSP Processing + Display Voice, Image, Multiple Sensors Battery Life Up to 14 days More capabilities, complex features, and high performance Higher level of Discrete user and sensor interaction Devices with longer battery life Ability to turn on/off certain functionalities to reduce power 2017 Synopsys, Inc. 6

7 High End SoC for Always-on IoT Common Characteristics Applications IoT wearables, smart energy hubs USB 2.0 Host OTG w/charge Detect Radio (WiFi, Bluetooth Smart, ) Security NVM (eflash / MTP) Data Fusion IP Subsystem MIPI CSI2 Host Health / fitness devices Wireless audio (Bluetooth low energy) Common system components RTOS or bare metal ROM SRAM ARC EMxD Processor I 2 C/ I 3 C SPI H/W Accel ADC UART Timers GPIO MIPI DSI Host AA/Coin, lithium Bluetooth, , Zigbee, Wi-Fi Unique technology & IP needs Embedded NVM (Flash/MTP) Connectivity, sensors, multimedia and security 2017 Synopsys, Inc. 7

8 Implementation of Widely-Used MIPI Specifications CSI-2, DSI, D-PHY 2017 Synopsys, Inc. 8

9 MIPI CSI-2 Over D-PHY Overview Packet Builder Data Format Definition V C Virtual Channel Identification D T WC Payload byte size ECC ECC protecting the header Data CRC processing CRC CSI-2 Receiver CSI-2 Transmitter Frame Buffer Packet Decoder CSI-2 Packet Lane Merger CSI-2 Packet Clk+ Clk- L0+ L0- L1+ L1- Clk+ Clk- L0+ L0- L1+ L1- D P H Y D P H Y Lane Distribution D-PHY HS Burst D-PHY HS Burst CSI-2 Packet Packet Builder CSI-2 Packet Frame Buffer CSI-2 Host CCI Master CCI Slave CSI-2 Device SCL SCL SDA SDA 2017 Synopsys, Inc. 9

10 MIPI CSI-2 Packets Short packets used for frame synchronization Image data Short packets used for frame synchronization Frame Start Packet First Packet of Data Last Packet of Data Frame End Packet SoT FS EoT LPS SoT PH Data PF EoT SoT PH Data PF EoT LPS SoT FE EoT VVALID HVALID DVALID Low power states between image lines KEY: SoT Start of Transmission PH Packet Header FS Frame Start LS Line Start EoT End of Transmission LPS Low Power State PF Packet Footer + Filler (if applicable) FE Frame End LE Line End 2017 Synopsys, Inc. 10

11 MIPI DSI Over D-PHY DSI Video Mode Example DPI Interface DSI Receiver DSI Transmitter Packet Decoder Valid Image VSS HSE Line Lane merger Clk+ Clk- L0+ L0- L1+ Clk+ Clk- L0+ L0- L1+ D P H Y D P H Y Lane distribution D-PHY HS HS Burst D-PHY HS HS Burst Packet Builder VSS HSE DSI SPacket LPacket L1- L1- DSI SPacket LPacket Valid Image Line Packet Builder SHORT LONG Packet Data Format Data Format definition definition V C Virtual Virtual Channel Channel Identification Identification D T WC DATA0 Payload byte size ECC DATA1 ECC ECC protecting the ECC protecting the short header packet Data CRC processing CRC 2017 Synopsys, Inc. 11

12 MIPI DSI Over D-PHY DSI Video Mode Example DPI Interface DSI Receiver DSI Transmitter Packet Decoder Valid Image VSS HSE Line Lane merger Clk+ Clk- L0+ L0- L1+ Clk+ Clk- L0+ L0- L1+ D P H Y D P H Y Lane distribution D-PHY HS HS Burst D-PHY HS HS Burst Packet Builder VSS HSE DSI SPacket LPacket L1- L1- DSI SPacket LPacket Valid Image Line Packet Builder SHORT LONG Packet Data Format Data Format definition definition V C Virtual Virtual Channel Channel Identification Identification D T WC DATA0 Payload byte size ECC DATA1 ECC ECC protecting the ECC protecting the short header packet Data CRC processing CRC 2017 Synopsys, Inc. 12

13 D-PHY Architecture The Popular Physical Layer Used for CSI-2 and DSI Specifications Synchronous Forwarded DDR clock link architecture One clock and multiple data lanes configuration Static/dynamic de-skew supported through calibration No encoding overhead Low-power and high-speed modes Primarily targeting camera and display Spread spectrum clocking supported for EMI/EMC considerations Large eco-system, proven in millions of phones, wearables and cars Two Data Lane Configuration 2017 Synopsys, Inc. 13

14 Complete Camera and Display Solution Single-Vendor Solution, Production-Proven, Interoperable Secret Sauce I2C now soon 2017 Synopsys, Inc. 14

15 Implementation of New MIPI Specification Standardizing Sensor Interface 2017 Synopsys, Inc. 15

16 Why? Challenge of Integrating Multiple Sensors with Different Requirements Today Smartphones typically have sensors 2017 Synopsys, Inc. 16 Which require pins So many I/Os required!! Different Sensors have different requirements Fingerprint vs Compass Typical approach is to connect sensors using a mix of I2C and SPI I2C for lower data rates and SPI for higher data rates Multiple side band signals For interrupts, chip selects, power Images are courtesy of the MIPI Alliance management No Standard driver for these fragmented interfaces This will increase the package size and add complexity which translates into additional costs

17 MIPI Standardized Sensor Interface You Can do More with Two Wire communication interface, Clock (SCL) and Data (SDA) It takes the goodness of I2C Two-wire, Simple It takes the goodness of SPI Low Power and Speed Adds features such as In-band interrupt/command support Dynamic addressing Advanced power management High data rates While maintaining support for legacy I2C sensors Evolutionary, not revolutionary I/Os reduced to just two!! Images are courtesy of the MIPI Alliance 2017 Synopsys, Inc. 17

18 Enhanced Capabilities is a Sophisticated Protocol As Opposed to I2C Built-in CCC commands allow efficient bus management Each device has its own attributes (speed capabilities, latency requirements, etc) Master can use these commands to query and store device attributes Master uses all this information to schedule traffic accordingly and broadcast instructions (enter HDR, enable/disable interrupts, etc.) Built-in CCC commands enable advanced use cases Secondary master role for sensor hub applications Timing control and time-stamping With, user application is not involved in low level protocol details Complexity in managing multiple sensor is significantly reduced with Image courtesy of MIPI Alliance 2017 Synopsys, Inc. 18

19 Transfers Legacy I2C,Typical SDR, SDR CCC Broadcast, SDR Direct CCC and HDR All communication occurs within a frame. The frame begins with a START, followed by one or more transfers, and a STOP Legacy I2C messages remain unchanged Three types SDR messages: The address in the address header matches the Slave s dynamic address The address in the address header is 7 h7e (the broadcast address) Direct CCC or Broadcast CCC HDR messages: After broadcast address, EnterHDR CCCs is issued indicating that the Master is entering an HDR mode. Each HDR mode has its own EnterHDR CCC 2017 Synopsys, Inc. 19

20 Slave Requests Slave Interrupt Request IBI With or Without Data Slave shall wait for the bus available condition and then issue START by pulling the SDA line low In response, the main master shall start the clock on the SCL line, while leaving the SDA line free at high level The Slave shall then drive the SDA with its own address, followed by an RnW bit of 1. Master accepts the IBI by providing the ACK bit If the Slave s BCR[2] bit is set to 1, IBI has data and Master shall read the mandatory data byte that follows S Slave_addr_as_IBI/R Master_ACK SCL HIGH Slave Byte T P MASTER SLAVE DYNAMIC ADDR SECY MASTER SLAVE I2C SLAVE 2017 Synopsys, Inc. 20

21 Use Cases Examples Sensor Hub Sensor Subsystem Image Sensors Accelerometer Accelerometer Primary camera module Pixels Application Processor master Gyroscope Gyroscope Image sensor Sensor Hub secondary master Magnetometer Ambient Light Pressure Humidity Application Processor master Magnetometer Ambient Light Pressure Humidity Lens actuators/ controllers Secondary camera module Host processor/ ISP Temperature Temperature Image sensor/ SoC Others Others Pixels 2017 Synopsys, Inc. 21

22 Enables Efficient System Architectures Lower Power, More Efficient System, Faster Data Transfer Accelerometer Application Processor master Gyroscope Magnetometer Sensor Hub secondary master Ambient Light Pressure Humidity Temperature Others 2017 Synopsys, Inc. 22

23 Summary 2017 Synopsys, Inc. 23

24 Complete MIPI CSI-2, DSI, & D-PHY IP for IoT Complete Single-Vendor Solution, Production-Proven, Interoperable MIPI CSI-2, DSI, D-PHY and protocols Enables new set of power efficient applications in AR/VR, IoT markets Lowers integration risk for application processors, bridge ICs and multimedia coprocessors Future proof IP supporting variety of speeds, proven in silicon Reduces cost & power for multiple instantiations Testability features enable low cost manufacturing DSI Device Controller D-PHY CSI-2 Host Controller D-PHY CSI-2 Host Controller D-PHY SoC Image Signal Processing CSI-2 Device Controller D-PHY DSI Host Controller D-PHY Industry s first MIPI Demo 2017 Synopsys, Inc. 24