W27E257 32K 8 ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION FEATURES PIN CONFIGURATIONS BLOCK DIAGRAM PIN DESCRIPTION
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1 32K 8 ELECTRICLLY ERSBLE EPROM GENERL DESCRIPTION The W27E257 is a high-speed, low-power Electrically Erasable and Programmable Read Only Memory organized as bits that operates on a single 5 volt power supply. The W27E257 provides an electrical chip erase function. This part was the same EPROM Writer's utilities as the W27E256. FETURES High speed access time: 00/20/50 ns (max.) Read operating current: 5 m (typ.) Erase/Programming operating current m (typ.) Standby current: 5 µ (typ.) Single 5V power supply PIN CONFIGURTIONS +4V erase/+2v programming voltage Fully static operation ll inputs and outputs directly TTL/CMOS compatible Three-state outputs vailable packages: 28-pin 600 mil DIP and 32-pin PLCC BLOCK DIGRM VPP Q0 Q Q2 GND pin DIP V CC OE 0 CE Q7 Q6 Q5 Q4 4 5 Q3 CE OE VCC GND V PP CONTROL DECODER OUTPUT BUFFER CORE RRY Q0.. Q NC Q Q 2 5 Q 2 V P P 6 32-pin PLCC G N D N C 7 N C V C C Q 3 Q 4 Q NC OE 0 CE Q7 Q6 PIN DESCRIPTION SYMBOL DESCRIPTION 0 4 Inputs Q0 Q7 Data Inputs/Outputs CE Chip Enable OE Output Enable VPP Program/Erase Supply Voltage VCC Power Supply GND Ground NC No Connection Publication Release Date: January Revision 3
2 FUNCTIONL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27E257 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TCC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if TCC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27E257 uses electrical erasure. Generally, the chip can be erased within 00 ms by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (4V), VCC = VCE (5V), OE = VIH (2V or above but lower than VCC), 9 = VHH (4V), 0 = VIL (0.8V or below but higher than GND), and all other address pins equal VIL and data input pins equal VIH. Pulsing CE low starts the erase operation. Erase Verify Mode fter an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VPP = VPE (4V), CE = VIH, and OE = VIL. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "" to "0." The program mode is entered when VPP is raised to VPP (2V), VCC = VCP (5V), OE = VIH, the address pins equal the desired address, and the input pins equal the desired inputs. Pulsing CE low starts the programming operation. Program Verify Mode ll of the bytes in the chip must be verified to check whether or not they have been successfully programmed with the desired data. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (2V), CE = VIH, and OE = VIL. Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE = VIH, erasing or programming of non-target chips is inhibited, so that except for the CE and OE pins, the W27E257 may have common inputs
3 Standby Mode The standby mode significantly reduces VCC current. This mode is entered when CE = VIH. In standby mode, all outputs are in a high impedance state, independent of OE. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27E257 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations EPROM power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0. µ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. dditionally, for every eight devices, a 4.7 µf electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. TBLE OF OPERTING MODES (VPP = 2V, VPE = 4V, VHH = 2V, VCP = 5V, X = VIH or VIL) MODE PINS CE OE 0 9 VCC VPP OUTPUTS Read VIL VIL X X VCC VCC DOUT Output Disable VIL VIH X X VCC VCC High Z Standby (TTL) VIH X X X VCC VCC High Z Standby (CMOS) VCC ±0.3V X X X VCC VCC High Z Program VIL VIH X X VCP VPP DIN Program Verify VIH VIL X X VCP VPP DOUT Program Inhibit VIH VIH X X VCP VPP High Z Erase VIL VIH VIL VPE VCC VPE DIH Erase Verify VIH VIL X X VCC VPE DOUT Erase Inhibit VIH VIH X X VCP VPP High Z Product Identifier-manufacturer VIL VIL VIL VHH VCC VCC D (Hex) Product Identifier-device VIL VIL VIH VHH VCC VCC 02 (Hex) Publication Release Date: January Revision 3
4 DC CHRCTERISTICS bsolute Maximum Ratings PRMETER RTING UNIT mbient Temperature with Power pplied -55 to +25 C Storage Temperature -65 to +25 C Voltage on all pins with Respect to Ground Except VPP, 9 and VCC pins -0.5 to VCC +0.5 V Voltage on VPP Pin with Respect to Ground -0.5 to +4.5 V Voltage on 9 Pin with Respect to Ground -0.5 to +4.5 V Voltage on VCC Pin with Respect to Ground -0.5 to +7 V Note: Exposure to conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics (T = 25 C ±5 C, VCC = 5.0V ±0%) PRMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MX. Input Load Current ILI VIN = VIL or VIH -0-0 µ VCC Erase Current ICP CE = VIL m VPP Erase Current IPP CE = VIL m Input Low Voltage VIL V Input High Voltage VIH V Output Low Voltage (Verify) VOL IOL = 2. m V Output High Voltage (Verify) VOH IOH = -0.4 m Erase Voltage VID V VPP Erase Voltage VPE V VCC Supply Voltage (Erase) VCE V Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. CPCITNCE (VCC = 5V, T = 25 C, f = MHz) PRMETER SYMBOL CONDITIONS MX. UNIT Input Capacitance CIN VIN = 0V 6 pf Output Capacitance COUT VOUT = 0V 2 pf - 4 -
5 C CHRCTERISTICS C Test Conditions PRMETER CONDITIONS Input Pulse Levels 0.45V to 2.4V Input Rise and Fall Times 0 ns Input and Output Timing Reference Level 0.8V/2.0V Output Load CL = 00 pf, IOH/IOL = -0.4 m/2. m C Test Load and Waveform +.3V (IN94) 3.3K ohm DOUT 00 pf (Including Jig and Scope) Input Output 2.4V 0.45V Test Points 2.0V 0.8V 2.0V 0.8V Test Points Publication Release Date: January Revision 3
6 RED OPERTION DC CHRCTERISTICS (VCC = 5.0V ±0%, T = 0 to 70 C) (W27E257-0, S-0, K-0, P-0: VCC, min. = 3.0V and max. = 5.5V) PRMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MX. Input Load Current ILI VIN = 0V to VCC -5-5 µ Output Leakage Current ILO VOUT = 0V to VCC -0-0 µ VCC Standby Current ISB CE = VIH m VCC Operating Current ICC CE = VIL IOUT = 0 m f = 5 MHz ISB CE = VCC ±0.2V µ m VPP Operating Current IPP VPP = VCC µ Input Low Voltage VIL V Input High Voltage VIH VCC +0.5 V Output Low Voltage VOL IOL = 2. m V Output High Voltage VOH IOH = -0.4 m V VPP Operating Voltage VPP - VCC VCC V RED OPERTION C CHRCTERISTICS (VCC = 5.0V ±0%, T = 0 to 70 C) PRMETER SYM. W27E257-0 W27E257-2 W27E257-5 UNIT MIN. MX. MIN. MX. MIN. MX. Read Cycle Time TRC ns Chip Enable ccess Time TCE ns ccess Time TCC ns Output Enable ccess Time TOE ns OE High to High-Z Output TDF ns Output Hold from Change TOH ns Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP
7 DC PROGRMMING CHRCTERISTICS (VCC = 5.0V ±0%, T = 25 C ±5 C) PRMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MX. Input Load Current ILI VIN = VIL or VIH -0-0 µ VCC Program Current ICP CE = VIL m VPP Program Current IPP CE = VIL m Input Low Voltage VIL V Input High Voltage VIH V Output Low Voltage (Verify) VOL IOL = 2. m V Output High Voltage (Verify) VOH IOH = -0.4 m V 9 Silicon I.D. Voltage VID V VPP Program Voltage VPP V VCC Supply Voltage (Program) VCP V C PROGRMMING/ERSE CHRCTERISTICS (VCC = 5.0V ±0%, T = 25 C ±5 C) PRMETER SYM. LIMITS UNIT MIN. TYP. MX. VPP Setup Time TVPS µs Setup Time TS µs Data Setup Time TDS µs CE Program Pulse Width TPWP µs CE Erase Pulse Width TPWE ms Data Hold Time TDH µs OE Setup Time TOES µs Data Valid from OE TOEV ns OE High to Output High Z TDFP 0-30 ns Hold Time TH µs Hold Time after CE High (Erase) THC µs Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. Publication Release Date: January Revision 3
8 TIMING WVEFORMS C Read Waveform VIH Valid CE TCE OE T DF T CC T OE T OH Outputs High Z Valid Output High Z Erase Waveform Read Manufacturer Read Device SID SID 9 = 2.0V Chip Erase 9 = 4.0V Erase Verify Blank Check Read Verify 0= VIH Others = VIL Others = 0 = VIL Others = VIL T CC T CC T S T RC Stable T DFP Stable Stable T CC Data D 02 Data ll One D OUT D OUT D OUT 4.0V T DS T HC T H 5.0V T VPS 5V V PP T CE CE OE T OE T OE T PWE T OES T OE T OEV - 8 -
9 Timing Waveforms, continued Programming Waveform Program Program Verify Read Verify Stable Stable Valid T S T DFP T CC Data Data In Stable D OUT D OUT D OUT T DS T DH T H 2.0V V PP 5.0V T VPS 5V CE OE T PWP T OES T OEV T OE Publication Release Date: January Revision 3
10 SMRT PROGRMMING LGORITHM Start = First Location Vcc = 5V Vpp = 2V X = 0 Program One 00 S Pulse µ Increment X X = 25? Yes No Fail Verify One Byte Verify One Byte Fail Pass Pass Increment No Last? Yes Vcc = 5V Vpp = 5V Compare ll Bytes to Original Data Fail Pass Pass Device Fail Device - 0 -
11 SMRT ERSE LGORITHM Start X = 0 Vcc = 5V Vpp = 4V 9 = 4V; 0 = VIL Chip Erase 00 ms Pulse = First Location Increment X Erase Verify Fail No X = 20? Increment No Pass Last? Yes Yes Vcc = 5V Vpp = 5V Compare ll Bytes to FFs (HEX) Fail Pass Pass Device Fail Device Publication Release Date: January Revision 3
12 ORDERING INFORMTION PRT NO. CCESS TIME (ns) POWER SUPPLY CURRENT MX. (m) STNDBY VCC CURRENT MX. (µ) PCKGE W27E mil DIP W27E mil DIP W27E mil DIP W27E257P pin PLCC W27E257P pin PLCC W27E257P pin PLCC Notes:. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure
13 PCKGE DIMENSIONS 28-pin P-DIP E 2 L 28 S B B D e 5 4 Base Plane Seating Plane a E e c Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. 2 B B c D E E e L a e S Notes:. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E does not include interlead flash. 3. Dimension D & E include mold mismatch and are determined at the mold parting line. 4. Dimension B does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 32-pin PLCC H E E D H D c G D Symbol 2 b b c D E e G D G E H D H E L y q Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max L θ Seating Plane e G E b b 2 y Notes:. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. Publication Release Date: January Revision 3
14 Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III, Rm. 803, World Trade Square, Tower II, Science-Based Industrial Park, 23 Hoi Bun Rd., Kwun Tong, Hsinchu, Taiwan Kowloon, Hong Kong TEL: TEL: FX: FX: Voice & Fax-on-demand: Taipei Office F, No. 5, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: FX: Winbond Electronics North merica Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab Orchard Parkway, San Jose, C 9534, U.S.. TEL: FX: Note: ll data and specifications are subject to change without notice
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