Flynn s Classification

Transcription

1 Flynn s Classification SISD (Single Instruction Single Data) Uniprocessors MISD (Multiple Instruction Single Data) No machine is built yet for this type SIMD (Single Instruction Multiple Data) Examples: Illiac-IV, CM-2 Each processor has its own data memory Only a single inst. memory and control processor Less flexible Use special-purpose microprocessors MIMD (Multiple Instruction Multiple Data) Examples: SPARCCenter, T3D Flexible Use off-the-shelf microprocessors Chapter 8 page 1 CS 5515

2 Small-Scale, Centralized Share-Memory Multiprocessors Memory: centralized with uniform access time ( uma ) and bus interconnect Examples: SUN SPARCCenter, SGI Challenge Chapter 8 page 2 CS 5515

3 Large-Scale, Distributed-Memory Multiprocessors Memory: distributed with nonuniform access time ( numa ) and scalable interconnect (distributed memory) Examples: T3D, Exemplar, Paragon, CM-5 1 cycle 40 cycles 100 cycles Low Latency High Reliability Chapter 8 page 3 CS 5515

4 Communication Models Shared Memory Processors communicate with a shared address space Applicable to centralized or distributed shared-memory MPs Advantages: Ease of programming -- dealing with a single address space Lower overhead for communication (e.g., via hardware) Better use of bandwidth when communicating small items Easier to use hardware controlled caching Message passing Processors have private memories & communicate via messages -- normally being called as multicomputers. MPI (message-passing interface) standards available Advantages: Simpler hardware, e.g., no cache coherence issues communication is explicit so force programmer to pay attention on costly non-local operations (a drawback too). Chapter 8 page 4 CS 5515

5 Small-Scale MPs -- Centralized Shared-Memory Caches serve to: Reduce bandwidth requirements of bus/memory Reduce latency of access Valuable for both private data (used by a single processor) and shared data Problem: cache coherence Chapter 8 page 5 CS 5515

6 The Problem of Cache Coherency Chapter 8 page 6 CS 5515

7 What Does Coherency Mean? Informally: Any read of a data item returns the most recently written value of that data item Two aspects to be addressed: Coherence: what values can be returned by a read Consistency: when a written value will be returned by a read A system is coherent if Any write is eventually seen by a read All writes are seen in the same order ( serialization ) Two rules to ensure this: If P writes x and P1 reads it, P s write will be seen if the read and write are sufficiently far apart Writes to the same location are serialized, i.e., two writes to the same location by any two processors are seen in the same order by all processors -- a property called write serialization. Chapter 8 page 7 CS 5515

8 Potential Solutions to Coherency Snooping Protocols (Snoopy Bus): Send all requests for data to all processors Processors snoop to see if they have a copy and respond accordingly Requires broadcast, since caching information is at processors Works well with bus (natural broadcast medium) Dominates for small scale machines (most of the market) Directory-Based Protocols Keep track of what is being shared in one centralized place Distributed memory => distributed directory (avoids bottlenecks) Send point-to-point requests to processors Used for distrubuted share-memory MPs (discussed in 8.4) Scales better than Snoop Chapter 8 page 8 CS 5515

9 Write Invalidate Protocol: Basic Snooping Protocols Multiple readers, single writer Write to shared data: an invalidate is sent to all caches which snoop and invalidate any copies Read Miss: Write-through: memory is always up-to-date Write-back: snoop in caches to find the most recent copy Write Update Protocol: Write to shared data: broadcast on bus, processors snoop, and update copies Read miss: memory is always up-to-date In either case, write serialization is enforced because the bus is a single point of arbitration and it serializes all write requests to the same data item Chapter 8 page 9 CS 5515

10 Basic Snoopy Protocols Write Invalidate versus Write Update (Broadcast): Invalidate requires only one invalidation broadcast for multiple writes while Update requires multiple write broadcasts For a multi-word cache block, Invalidate only invalidates it once for the first write while Update updates it for each word written Update has lower latency between write and read Update Trades BW requirement (increased) for latency (decreased) Name Protocol Type Memory-write policy Machines using Write Once Write invalidate Write back First snoopy protocol. after first write Synapse N+1 Write invalidate Write back 1st cache-coherent MPs Berkeley Write invalidate Write back Berkeley SPUR Illinois Write invalidate Write back SGI Power and Challenge Firefly Write update Write back private, Write through shared SPARCCenter 2000 protocol of choice nowadays Chapter 8 page 10 CS 5515

11 An Example Snooping Protocol Invalidation protocol, write-back cache Each block of memory is in one state: Clean in all caches and up-to-date in memory OR Dirty in exactly one cache OR Not in any caches Each cache block is in one state: Shared: cache has one copy the same as in the memory and there may be other copies in other caches OR Exclusive: cache has only copy, it s writeable, and dirty OR Invalid: block contains no data Read misses: cause all caches to snoop A write to a cache block in the shared state will cause a write miss -- assumed although can be improved Chapter 8 page 11 CS 5515

12 State machine for a cache block based on requests from CPU Boldface is used to specify bus actions Snoopy-Cache State Machine-I CPU Write: Place write miss on bus Invalid CPU Read: Place read miss on bus CPU read miss for another block: Write back block; place read miss on bus CPU read miss for another block: Place read miss on bus Shared (read only) CPU read hit CPU Write: Place write miss on Bus CPU read hit CPU write hit Exclusive (read/write) CPU write miss for another blcok: Write back cache block Place write miss on bus Chapter 8 page 12 CS 5515

13 Snoopy-Cache State Machine-II Cache State machine based on requests from the bus Invalid Write miss for the block Shared (read only) Write miss for this block: Write back block; abort memory access Read miss for this block: Write back block; abort memory access Exclusive (read/write) Chapter 8 page 13 CS 5515

14 Snoop Cache: State Machine (Fig. 8.12) A possible extension (e.g., Problem 8.4): Adding a 4th state called Clean Private: the cache contains the only copy the same as the memory copy Clean Private -> Exclusive on CPU write hit Clean Private -> Shared on read miss received from the bus Chapter 8 page 14 CS 5515

15 CPU read hit Write miss for this block Write-back block Write miss for block CPU read Invalid Place read miss on bus Place write miss on bus CPU write CPU read miss Write-back data; place read miss on bus Read miss for block Write-back block Place write miss on bus CPU write Shared (read only) CPU read miss Place read miss on bus CPU write hit CPU read hit Exclusive (read/write) CPU write miss Write-back data Place write miss on bus FIGURE 8.12 Cache-coherence state diagram with the state transitions induced by the local processor shown in black and by the bus activities shown in gray.

16 . An Example of Basic Snooping Protocol p1: write(a1,10) p3:read(a2) p2:write(a2,20) t1 t2 t3 t4 t5 p2:read(a1) Assume that A1 and A2 map to same cache block timep 2 p2: replaces the cache block on a read miss s t e p time processor p1 processor p2 processor p3 S t a t e A d d r S t a t e t1 exclusive invalid invalid t2 shared invalid shared t3 shared shared shared t4 invalid exclusive invalid t5 invalid *shared invalid A d d r V a l u e A ct io n P r o c A d d r P 1 V a l u e A d d r V a l u e note that the state of this cache block is not for the block containing A1 and A2 any more; it is for another block Chapter 8 page 15 CS 5515

17 Snooping Protocol Variations Berkeley Protocol Owned Exclusive Owned Shared Shared Invalid Basic Protocol Exclusive Shared Invalid Illinois Protocol Private Dirty Private Clean Shared Invalid A new bus operation called invalidation is introduced, so that Shared -> Owned Exclusive can be achieved by broadcasting invalidate operations and there is no need to generate a write-miss on write hit If read sourced from memory, then Private Clean if read sourced from other cache, then Shared Can write in cache if held private clean or dirty However, write hit on a Shared cache still generates write miss broadcast to the bus Chapter 8 page 16 CS 5515

18 Scaleable MPs Separate Memory per Processor bus bandwidth cannot support a large # of processors replacing bus with a general ICN; however; snooping protocols will be expensive because the cost of broadcasting is high A simple software solution: make shared data uncacheable simple hardware but poor performance Alternative: Use a directory to track the state of every memory block in caches Which caches have a copies of the block, dirty vs. clean,... Prevent directory as bottleneck: distribute directory entries with memory, each keeping track of which caches have copies of their blocks there will make the directory associated with a memory block at a known location to avoid the cost of broadcasting Chapter 8 page 17 CS 5515

19 Processor + cache Processor + cache Processor + cache Processor + cache Memory I/O Memory I/O Memory I/O Memory I/O Directory Directory Directory Directory Interconnection network Directory Directory Directory Directory Memory I/O Memory I/O Memory I/O Memory I/O Processor + cache Processor + cache Processor + cache Processor + cache FIGURE 8.22 A directory is added to each node to implement cache coherence in a distributed-memory machine.

20 Directory Protocol Similar to Snoopy Protocol: 3 states Shared: Some processors have data, memory up to date Uncached: No processor has a copy Exclusive: 1 processor(owner) has data; memory out of date In addition to cache state, must track which processor (Shared or Exclusive) has a copy: Use a bit vector to maintain a Sharer set (one such set per memory block) Terms: Local node is the node where a request originates Home node is the node where the memory location of an address resides Remote node is the node that has a copy of a cache block, whether exclusive or shared. Chapter 8 page 18 CS 5515

21 Message type Source Destination Message contents Function of this message Read miss Local cache Home directory Write miss Local cache Home directory Invalidate Home directory Fetch Fetch/invalidate Data value reply Data write back Home directory Home directory Home directory Remote cache P, A Processor P has a read miss at address A; request data and make P a read sharer. P, A Processor P has a write miss at address A; request data and make P the exclusive owner. Remote caches A Invalidate a shared copy of data at address A. Remote cache A Fetch the block at address A and send it to its home directory; change the state of A in the remote cache to shared. Remote cache A Fetch the block at address A and send it to its home directory; invalidate the block in the cache. Local cache Data Return a data value from the home memory. Home directory A, Data Write back a data value for address A. FIGURE 8.23 The possible messages sent among nodes to maintain coherence.

22 Directory Protocol Message sent to directory causes 2 actions: update the directory and send messages to caches to satisty request Block is in Uncached state: the copy in memory is the only copy so possible requests for that block are: Read miss: requesting processor is sent back the data from memory and the requestor is the only sharing node. The state of the block is made Shared. Write miss: requesting processor is sent the value and becomes the Sharing node. The block is made Exclusive to indicate that the only valid copy is cached. Sharers indicates the identity of the owner. Block is Shared, the memory value is up-to-date: Read miss: requesting processor is sent back the data from memory & requesting processor is added to the sharing set. Write miss: requesting processor is sent the value. All processors in the set Sharers are sent invalidate messages, & Sharers set is to identity of requesting processor. The state of the block is made Exclusive. Chapter 8 page 19 CS 5515

23 Directory Protocol Block is Exclusive: current value of the block is held in the cache of the processor identified by the set Sharers (the owner), & 3 possible directory requests: Read miss: owner processor is sent a data fetch message, which causes state of block in owner s cache to transition to Shared and causes owner to send data to directory, where it is written to memory and sent back to the requesting processor. Identity of requesting processor is added to set Sharers, which still contains the identity of the processor that was the owner (since it still has a readable copy). Data write-back: owner processor is replacing the block and hence must write it back. This makes the memory copy up-to-date (the home directory essentially becomes the owner), the block is now uncached, and the Sharer set is empty. Write miss: block has a new owner. A message is sent to old owner causing the cache to send the value of the block to the directory from which it is send to the requesting processor, which becomes the new owner. Sharers is set to identity of new owner, and state of block is made Exclusive. Chapter 8 page 20 CS 5515

24 State Transition Diagram for the Home Directory that Tracks the Status of A Memory Block Three States: Uncached, Shared and Exclusive All actions are in gray color since they all are externally caused. Italics indicates the action taken by the directory in response to the request. Bold italics indicate an action that updates the sharing set, Sharers, as opposed to sending a message. Chapter 8 page 21 CS 5515

25 Sharers={} Data write-back Uncached Data value reply; Sharers={P} Write miss Data value reply; Sharers={P} Read miss Read miss Fetch; data value reply; Sharers=Sharers+{P} Write miss Invalidate; Sharers={P}; data value reply Shared (read only) Read miss Data value reply Sharers=Sharers+{P} Exclusive (read/write) Write miss Fetch/invalidate Data value reply Sharers={P} FIGURE 8.25 The state transition diagram for the directory has the same states and structure as the transition diagram for an individual cache.

26 State Transition Diagram for an Individual Cache Block in a Directory Based System The states are identical to those in the snoopingcase and the transactions are very similar, with explicit invalidate and write-back requests replacing the write misses that were formerly broadcast on the bus. Colors in the figure black: requests from the CPU gray: requests from the home directory Chapter 8 page 22 CS 5515

27 CPU read hit Invalidate Invalid CPU read Send read miss message Shared (read only) Fetch invalidate Data write-back Send write miss message CPU write CPU read miss Data write-back; read miss Fetch Data write-back Send write miss message CPU write CPU read miss Read miss CPU write hit CPU read hit Exclusive (read/write) CPU write miss Data write-back Write miss FIGURE 8.24 State transition diagram for an individual cache block in a directorybased system.

28 . An Example of Directory-Based Protocol p1: write(a1,10) p3:read(a2) p2:write(a2,20) t1 t2 t3 t4 t5 p2:read(a1) Assume that A1 and A2 map to same cache block s t e p time processor p1 processor p2 processor p3 S t a t e A d d r S t a t e t1 exclusive invalid invalid t2 shared invalid shared t3 shared shared shared t4 invalid exclusive invalid t5 invalid *shared invalid A d d r V a l u e A ct io n P r o c A d d r P 1 timep 2 p2: replaces the cache block on a read miss V a l u e A d d r home directory exclusive shared shared exclusive uncached note that the state of this cache block is not for the block containing A1 and A2 any more; it is for another block Chapter 8 page 23 CS 5515

29 Miss Rates for Snooping Protocol 4th C: Conflict, Capacity, Compulsory and Coherency Misses More processors: increase coherency misses while decreasing capacity misses (cache size increases for fixed problem size) Cache behavior of Five Parallel Programs: FFT Fast Fourier Transform: Matrix transposition + computation LU factorization of dense 2D matrix (linear algebra) Barnes-Hut n-body algorithm solving galaxy evolution problem Ocean simulates influence of eddy & boundary currents on largescale flow in ocean: dynamic arrays per grid VolRend is parallel volume rendering: scientific visualization Chapter 8 page 24 CS 5515

30 Miss Rates for Snooping Protocols High Capacity Misses Miss Rate Miss Rate 20% 18% 16% 14% 12% 10% 8% 8% 8% 8% 8% 8% 18% 14% 15% 13% 9% Big differences in miss rates among the programs 6% 4% 2% 0% # of processors 2% 2% 2% 2% 2% 1% 1% 1% 1% 1% Ocean 1% 1% 1% 1% 1% fft lu barnes ocean volrend Cache size is 64KB, 2-way set associative, with 32B blocks. With the exception of Volrend, the misses in these applications are generated by accesses to data that is potentially shared. Except for Ocean, data is heavily shared; in Ocean only the boundaries of the subgrids are shared, though the entire grid is treated as a shared data object. Since the boundaries change as we increase the processor count (for a fixed size problem), different amounts of the grid become shared. The anomalous increase in miss rate for Ocean in moving from 1 to 2 processors arises because of conflict misses in accessing the subgrids. Chapter 8 page 25 CS 5515

31 % Misses Caused by Coherency Traffic vs. # of Processors Miss Rate 80% 70% 60% 50% 40% 30% 20% 10% 0% 80% of misses due to coherency misses! FFT Processor Count fft lu barnes LU Barnes Ocean Volrend % cache misses caused by coherency transactions typically rises when a fixed size problem is run on more processors. The absolute number of coherency misses is increasing in all these benchmarks, including Ocean. In Ocean, however, it is difficult to separate out these misses from others, since the amount of sharing of the grid varies with processor count. Invalidation increases significantly; In FFT, the miss rate arising from coherency misses increases from nothing to almost 7%. ocean volrend Chapter 8 page 26 CS 5515

32 Miss Rates vs. Cache Size Per Processor Miss Rate Miss Rate 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Ocean LU Cache Size in KB FFT Ocean and FFT strongly influenced by capacity misses Cache Size Volrend Barnes fft lu barnes ocean volrend Miss rate drops as the cache size is increased, unless the miss rate is dominated by coherency misses. The block size is 32B & the cache is 2-way set-associative. The processor count is fixed at 16 processors. Chapter 8 page 27 CS 5515

33 % Misses Caused by Coherency Traffic vs. Cache Size 80% (small absolute miss rate < 2%) Barnes Miss Rate 70% 60% 50% 40% 30% (large absolute miss rates > 8%) LU Ocean FFT 20% 10% 0% Volrend Cache Size in KB fft lu barnes ocean volrend Reduction of capacity misses with increasing cache size Chapter 8 page 28 CS 5515

34 Note: Miss Rate vs. Block Size: Miss Rate Mostly Decreases with Increasing Block Size Overall, miss rate drops as block size increases due to the decrease in capacity misses Since a cache block holds multiple words, coherence misses can increase with a larger block because of a higher probability of the block being invalidated False sharing arises from the use of an invalidation-based coherency algorithm. It occurs when a block is invalidated (and a subsequent reference causes a miss) because some word in the block, other than the one being read, is written into. False sharing would not arise if each cache block contains only one word. 14% 12% 10% 8% 6% 4% 2% 13% 8% fft lu barnes ocean volrend Chapter 8 page 29 CS % 4% 4% 2% 1% 0% 1% 1% 1% 1% 13% 9% 6% 5% % 1% 1% 1%

35 Bus Traffic vs. Block Size Bytes per data ref Ocean FFT LU Huge Increases in bus traffic due to coherency! fft lu barnes ocean volrend Volrend Bus traffic climbs steadily as the block size is increased. Volrend: the increase is more than a factor of 10, although the low miss rate keeps the absolute traffic small. The factor of 3 increase in traffic for Ocean is the best argument against larger block sizes. Remember that our protocol treats ownership misses the same as other misses, slightly increasing the penalty for large cache blocks: in both Ocean and FFT this effect accounts for less than 10% of the traffic. Chapter 8 page 30 CS 5515

36 Miss Rates for Directory-Based Protocols Miss Rate 7% 6% Ocean 7% 6% Cache size is 128 KB, 2-way set associative, with 64B blocks. Ocean only the boundaries of the Miss Rate 5% 4% 3% 2% 5% 5% 5% 5% 4% 3% Since the boundaries change as we increase the processor count (for a fixed size problem), different amounts of the 1% 0% 1% 1% 1% 1% 1% 1% 1% 0% 0% 0% 0% fft lu barnes ocean volrend 1% to 64 processors arises because of conflict misses in accessing small # of Processors Chapter 8 page 31 CS 5515

37 18% 16% 14% 12% 10% 8% 6% 4% 2% Miss Rates vs. Cache Size per Processor for Directory-Based Protocols 9% 8% 7% 5% 4% 2% 2% 2% 1% 1% 1% 1% 0% 0% 0% 18% 13% 9% 7% 5% Miss rate drops as the cache size is increased, unless the miss rate is dominated by coherency misses. The block size is 64B and the cache is 2-way setassociative. The processor count is fixed at 16 processors. 1% 1% 1% 1% 1% fft lu barnes ocean volrend Chapter 8 page 32 CS 5515

38 Block Size Effect for Directory Protocols Assumes 128 KB cache & 64 processors Use larger cache size to deal with higher memory latencies than snoop caches 14% 13% 12% 12% 10% 9% 8% 7% 7% 6% 5% 5% 4% 3% 3% 2% 2% 1% 0% 0% 0% 0% 0% 1% 1% 1% 1% fft lu barnes ocean volrend Chapter 8 page 33 CS 5515