phycore -RK3288 Hardware Manual

Transcription

1 phycore -RK Hardware Manual Document No.: L-e_ SOM Prod. No.: PCM-0 SOM PCB. No.:.,. CB Prod. No.: PCM- CB PCB. No.:. Edition: March 0 A product of a PHYTEC Technology Holding company

2 phycore -RK [PCM-0] Copyrighted products are not explicitly indicated in this manual. The absence of the trademark (, or ) and copyright ( ) symbols does not imply that a product is not protected. Additionally, registered patents and trademarks are similarly not expressly indicated in this manual. The information in this document has been carefully checked and is considered to be entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages that might result. Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout and/or design of the hardware without prior notification and accepts no liability for doing so. Copyright 0 PHYTEC Messtechnik GmbH, D- Mainz. Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and storage or processing in computer systems, in whole or in part - are reserved. No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH. Address: Ordering Information: Technical Support: EUROPE NORTH AMERICA FRANCE PHYTEC Messtechnik GmbH Robert-Koch-Str. D- Mainz GERMANY + - sales@phytec.de + - support@phytec.de PHYTEC America LLC 0 Parfitt Way SW Bainbridge Island, WA 0 USA sales@phytec.com support@phytec.com PHYTEC France, place Saint-Etienne F-0 Sillé-le-Guillaume FRANCE + info@phytec.fr support@phytec.fr Fax: Web Site: Address: Ordering Information: Technical Support: Fax: INDIA PHYTEC Embedded Pvt. Ltd. No., th A Cross, th Main, nd Sector, HSR Layout, Bangalore-00 INDIA / sales@phytec.in /0 support@phytec.in CHINA PHYTEC Information Technology (Shenzhen) Co. Ltd. 0A, Block A, Tianxia Jinniu Square, Taoyuan Road, Nanshan District, 0 Shenzhen CHINA sales@phytec.cn support@phytec.cn Web Site: st Edition March 0 PHYTEC Messtechnik GmbH 0 L-e_

3 Contents List of Figures... iv List of Tables... v Conventions, Abbreviations and Acronyms... ix Preface... xii Introduction.... Features of the phycore-rk.... Block Diagram.... phycore-rk Component Placement.... Minimum Requirements to operate the phycore-rk... Pin Description... Jumpers... 0 Power.... Primary System Power (VDD_IN_OTG_OUT, VBATT+).... Power Management IC (PMIC) (U)..... Power Domains..... Built-in Real Time Clock (RTC) PMIC Interrupt Power Management...0. Supply Voltages for external Devices... Reset... System Boot... System Memory.... DDR-SDRAM (U-U).... emmc Flash Memory (U).... I²C EEPROM (U0)..... EEPROM Write Protection Control (J).... SPI NOR Flash Memory (U)... SD/MM Card Interfaces... SDIO Card Interface... 0 Serial Interfaces Universal Asynchronous Interfaces USB OTG Interface USB Host Interface USB HSIC Interface Ethernet Interface Ethernet PHY (U) Ethernet Interface Voltage Software Reset of the Ethernet Controller MAC Address RGMII Interface SPI Interface I C Interfaces I S Audio Interface SPDIF Interface... PHYTEC Messtechnik GmbH 0 L-e_ i

4 phycore -RK [PCM-0] General Purpose I/Os... Analog Inputs... User LED... 0 Debug Interface... Display Interfaces.... Parallel Display Interface.... LVDS Display Interface.... Supplementary Signals.... MIPI Display Interfaces... High-Definition Multimedia Interface (HDMI)... Mobile Industry Processor Interface (MIPI)... Camera Interfaces.... Parallel Camera Interface (CIF PP).... MIPI CSI- Camera Interfaces... Technical Specifications Product Temperature Grades.... Connectors on the phycore-rk... 0 Hints for Integrating and Handling the phycore-rk Integrating the phycore-rk Handling the phycore-rk... The phycore-rk on the phycore Carrier Board.... Concept of the phycore Carrier Board.... Features.... Overview of the phycore Carrier Board Peripherals Connectors and Pin Header..... Switches..... LEDs..... Jumpers.... Functional Components on the phycore Carrier Board..... phycore-rk SOM Connectivity (X)..... Power (X, X, X0, X) Power Supply Options Power Supply via Wall Adapter Input (X) Power Supply via Pin Connector X Power Supply via Battery Connector (X0) Power Supply via Micro-USB Connector (X) Current, Temperature and Voltage Supervision Battery Charging / Discharging Current Sensing Battery Pack Temperature Monitoring Supply Voltage Monitoring..... RS- Connectivity (X, X)..... Ethernet Connectivity (X)... ii PHYTEC Messtechnik GmbH 0 L-e_

5 Contents.. USB OTG Connectivity (X)..... USB Host Connectivity (X, X) USB HSIC Connectivity (X)..... Display / Touch Connectivity Phytec Display Interface (PDI) (X) Phytec Display Interface (PDI) Data Connector (X) Phytec Display Interface (PDI) Power Connector (X) DDG Display and Touch Connectivity (X, X, X0, X, X) DDG LVDS Data Connector (X) DDG Display Backlight Connector (X) DDG Resistive Touch Connector (X0) DDG Display Optional Connector (X) DDG Display Extra LVDS Connector (X) Phytec Audio/Video (A/V) Connectors (X, X) Audio/Video (A/V) Connector # (X) Audio/Video (A/V) Connector # (X) Resistive Touch Control at U..... High-Definition Multimedia Interface (HDMI) (X)..... Mobile Industry Processor Interface (MIPI) (X, X) Camera Interface (X, X) phycam-s(+) (LVDS) Camera Interfaces (X) MIPI CSI- Camera Interface (X) phycam-p or Parallel Camera Interface..... Audio Interface (X, X, X, X)..... I C Connectivity (X, X0, X, X, X) SPI Connectivity (X, X)..... User-programmable GPIOs..... User-programmable LEDs..... User-programmable Buttons (S, S)..... User-definded Temperature Sensing..... Secure Digital Memory Card/ MultiMedia Card (X)..... Wi-Fi/Bluetooth Connector (X) Boot Switches (S, S)..... System Reset Button (S)..... System Power On/Off/Wake Button (S) System Sleep Button (S) JTAG Interface (X0)..... RTC at U..... I C EEPROM at U Setting the EEPROM Address Bits (J, J, J) EEPROM Write Protection Control (JP)..... Expansion Connector (X)... Revision History... Index... PHYTEC Messtechnik GmbH 0 L-e_ iii

6 phycore -RK [PCM-0] List of Figures Figure : Block Diagram of the phycore-rk... Figure : phycore-rk Component Placement (PCB., top view)... Figure : phycore-rk Component Placement (PCB., bottom view)... Figure : Pinout of the phycore-connector (top view)... 0 Figure : Typical Jumper Pad Numbering Scheme... 0 Figure : Jumper Locations (PCB., top view)... Figure : Jumper Locations (PCB., bottom view)... Figure : Powering Scheme of the phycore-rk... Figure : User LED Location (PCB., top view)... 0 Figure 0: Camera Connectivity of the RK... Figure : Camera Interfaces at the phycore-connector Parallel bit and MIPI CSI-... Figure : Signals optionally usable with the Camera Interface... Figure : Physical Dimensions (top view)... 0 Figure : Footprint of the phycore-rk... Figure : phycore Carrier Board Overview of Connectors,Buttons and Switches... 0 Figure : phycore Carrier Board Overview of the LEDs... Figure : Typical Jumper Numbering Scheme... Figure : phycore Carrier Board Jumper Locations... Figure : phycore- RK SOM Connectivity to the Carrier Board... Figure 0: Powering Scheme... Figure : Power Connector corresponding to Wall Adapter Input (X)... Figure : RS- Interface Connectors X and X... Figure : RS- Connector X (DB-M) Signal Mapping (UART0)... Figure : RS- Connector X (DB-F) Signal Mapping (UART)... Figure : Ethernet Interfaces at Connectors X... Figure : USB OTG Interface at Connector X... Figure : Components supporting the USB Host Interfaces... Figure : Phytec Display Interface (PDI) at Connector X...00 Figure : HDMI Interface at Connector X... Figure 0: Camera Interface at Connector X and X... Figure : Implementation of a phycam-s+ and two MIPI Interfaces on the phycore Carrier Board... Figure : Implementation of a phycam-p or parallel Camera Interface together with two MIPI Interfaces on a Custom Carrier Board... iv PHYTEC Messtechnik GmbH 0 L-e_

7 Contents Figure : Audio Interface at Connectors X, X, X, X... Figure : SPI Connectivity at Connectors X and X... Figure : SD/MM Card Interfaces at Connector X... Figure : Wi-Fi/Bluetooth Connector X... Figure : JTAG Connector X0... Figure : RTC with Battery Buffer... List of Tables Table : Signal Types used in this Manual... x Table : Abbreviations and Acronyms used in this Manual...xi Table : Pinout of the phycore-connector X, Row A... Table : Pinout of the phycore-connector X, Row B... Table : Pinout of the phycore-connector X, Row C... Table : Pinout of the phycore-connector X, Row D... Table : Jumper Settings... Table : External Supply Voltages... Table : Voltages generated by the on-board PMIC (U)... Table 0: Power Management Signals...0 Table : Supply Voltages for external Devices... Table : EEPROM Write Protection States via J... Table : Location of the SD/MM Card Interface Signals... Table : Location of the SDIO Card Interface Signals... Table : Supply Voltage for SDIO Card via J0... Table : Location of the UART Signals... Table : Location of the USB OTG Signals...0 Table : Location of the USB Host Signals...0 Table : HSIC Interface Signal Location... Table 0: Location of the Ethernet Signals... Table : Ethernet Interface Voltage via J... Table : Location of the RGMII Interface Signals... Table : SPI Interface Signal Location... Table : I C Interface Signal Location... Table : I S Interface Signal Location... Table : SPDIF Interface Signal Location... PHYTEC Messtechnik GmbH 0 L-e_ v

8 phycore -RK [PCM-0] Table : GPIOs for unrestricted Use... Table : Additional GPIOs usable with Restrictions... Table : Location of the Analog Inputs... Table 0: Debug Interface Signal Location... Table : Parallel Display Interface Signal Location... Table : LVDS Display Interface Signal Location... Table : Supplementary Signals to support the Display Connectivity... Table : HDMI Interface Signal Location at X... Table : MIPI DSI/CSI Signal Location... Table : Parallel Camera Interface (CIF PP) Signal Location... Table : Technical Specifications... Table : Product Temperature Grades... Table : phycore Carrier Board Connectors and Pin Headers... Table 0: phycore Carrier Board Push Buttons Descriptions... Table : phycore Carrier Board LEDs Descriptions... Table : phycore Carrier Board Jumper Descriptions... Table : Specifically used Pins on the phycore-connector... Table : Voltage Domains on the Carrier Board... Table : Power LEDs on the phycore-tk Carrier Board... Table : Power Supply Conditions of the Carrier Board... Table : Battery Connector X0 Signal Description... 0 Table : Voltages Selection at U for Monitoring... Table : Hardware Default Configuration of HSIC Hub Controller U.... Table 0: Table : Table : PDI Data Connector X Signal Description...0 Auxiliary Interfaces at PDI Data Connector X...0 PDI Power Connector X Signal Description...0 Table : DDG LVDS Data Connector X Signal Description...0 Table : JP Selecting the Supply Voltage at DDG LVDS Data Connector X...0 Table : Table : DDG Display Backlight Connector X Signal Description...0 JP and JP Selecting the Supply Voltage at DDG Display Backlight Connector X...0 Table : DDG Resistive Touch Connector X0 Signal Description...0 Table : DDG Display Optional Connector X Signal Description...0 Table : DDG Display Extra LVDS Connector X Signal Description...0 Table 0: Phytec A/V Connector # (X) Signal Location...0 vi PHYTEC Messtechnik GmbH 0 L-e_

9 Contents Table : Phytec A/V Connector # (X) Signal Location...0 Table : Resistive Touch Controller U I²C Address Configuration (J0)... Table : HDMI Connector X... Table : J Selecting the Shield at Connector X... Table : MIPI Connector X... Table : Phytec phycam-s+ Camera Connector X... Table : phycore-rk Carrier Board Audio Connectors...0 Table : I C Connectivity...0 Table : IC, IC and IC Addresses in Use... Table 0: SPI Interface Connector Selection... Table : User-programmable LEDs on the Carrier Board... Table : Wi-Fi/Bluetooth Connector X... Table : phyflex Carrier Board DIP Switches S and S Descriptions... Table : JTAG Connector X0... Table : Coin Cell at BAT, JP... Table : U EEPROM I²C Address via J, J and J... Table : EEPROM Write Protection States via JP... Table : Phytec Expansion Connector X... PHYTEC Messtechnik GmbH 0 L-e_ vii

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11 Conventions, Abbreviations and Acronyms Conventions, Abbreviations and Acronyms This hardware manual describes the PCM-0 System on Module in the following referred to as phycore -RK. The manual specifies the phycore -RK's design and function. Precise specifications for the Rockchip Electronics RK microcontrollers can be found in the enclosed microcontroller Data Sheet/User's Manual. Note: We refrain from providing detailed part specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products. Please read the paragraph "Product Change Management and information in this manual on parts populated on the SOM" within the Preface. The BSP delivered with the phycore -RK usually includes drivers and/or software for controlling all components such as interfaces, memory, etc. Therefore programming close to hardware at register level is not necessary in most cases. For this reason, this manual contains no detailed description of the controller's registers, or information relevant for software development. Please refer to the RK Technical Reference Manual, if such information is needed to connect customer designed applications. Conventions The conventions used in this manual are as follows: Signals that are preceded by an "n", "/", or # character (e.g.: nrd, /RD, or #RD), or that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low, or are driving low. A "0" indicates a logic zero or low-level signal, while a "" represents a logic one or high-level signal. The hex-numbers given for addresses of I C devices always represent the MSB of the address byte. The correct value of the LSB which depends on the desired command (read (), or write (0)) must be added to get the complete address byte. E.g. given address in this manual 0x => complete address byte = 0x to read from the device and 0x to write to the device Tables which describe jumper settings show the default position in bold, blue text. Text in blue italic indicates a hyperlink within, or external to the document. Click these links to quickly jump to the applicable URL, part, chapter, table, or figure. References made to the phycore-connector always refer to the high density Samtec connector on the undersides of the phycore-rk System on Module. PHYTEC Messtechnik GmbH 0 L-e_ ix

12 phycore -RK [PCM-0] Types of Signals Different types of signals are brought out at the phycore-connector. The following table lists the abbreviations used to specify the type of a signal. Signal Type Description Abbr. Analog Analog input Analog Power Supply voltage input PWR_I Power Supply voltage output PWR_O Ref-Voltage Reference voltage output REF_O Input Digital input I Output Digital output O IO Bidirectional input/output I/O OD-Bidir PU Open drain input/output with pull up OD-BI OC-Output Open collector output without pull up, requires an external OC pull up V Input PD V tolerant input with pull down V_PD LVDS Input Differential line pairs 00 Ohm LVDS level input LVDS_I LVDS Output Differential line pairs 00 Ohm LVDS level output LVDS_O TMDS Output Differential line pairs 00 Ohm TMDS level output TMDS_O USB IO Differential line pairs 0 Ohm USB level bidirectional USB_I/O input/output ETHERNET Differential line pairs 00 Ohm Ethernet level input ETH_I Input ETHERNET Differential line pairs 00 Ohm Ethernet level output ETH_O Output ETHERNET IO Differential line pairs 00 Ohm Ethernet level bidirectional ETH_I/O input/output PCIe Input Differential line pairs 00 Ohm PCIe level input PCIe_I PCIe Output Differential line pairs 00 Ohm PCIe level output PCIe_O PWM Output Pulse-width modulation output PWM MIPI CSI- Differential line pairs 00 Ohm MIPI CSI- level input CSI-_I Input MIPI Input/Output Differential line pairs 00 Ohm MIPI CSI- level input and DSI level output MIPI_I/O Table : Signal Types used in this Manual x PHYTEC Messtechnik GmbH 0 L-e_

13 Conventions, Abbreviations and Acronyms Abbreviations and Acronyms Many acronyms and abbreviations are used throughout this manual. Use the table below to navigate unfamiliar terms used in this document. Abbreviation Definition BSP Board Support Package (Software delivered with the Development Kit including an operating system (Windows, or Linux) preinstalled on the module and Development Tools). CB Carrier Board; used in reference to the phycore Development Kit Carrier Board. DFF D flip-flop. EMB External memory bus. EMI Electromagnetic Interference. GPI General purpose input. GPIO General purpose input and output. GPO General purpose output. IRAM Internal RAM; the internal static RAM on the Rockchip Electronics RK microcontroller. J Solder jumper; these types of jumpers require solder equipment to remove and place. JP Solderless jumper; these types of jumpers can be removed and placed by hand with no special tools. PCB Printed circuit board. PDI PHYTEC Display Interface; defined to connect PHYTEC display adapter boards, or custom adapters PEB PHYTEC Extension Board PMIC Power management IC PoE Power over Ethernet POR Power-on reset PWM Pulse-width modulation RTC Real-time clock. SMT Surface mount technology. SOM System on Module; used in reference to the PCM-0 /phycore - RK module Sx User button Sx (e.g. S, S, etc.) used in reference to the available user buttons, or DIP-Switches on the carrier board. Sx_y Switch y of DIP-Switch Sx; used in reference to the DIP-Switch on the carrier board. Table : Abbreviations and Acronyms used in this Manual PHYTEC Messtechnik GmbH 0 L-e_ xi

14 phycore -RK [PCM-0] Preface As a member of PHYTEC's phycore product family the phycore-rk is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers and hence offers various functions and configurations. PHYTEC supports a variety of -/- and -bit controllers in two ways: () as the basis for Rapid Development Kits which serve as a reference and evaluation platform () as insert-ready, fully functional phycore OEM modules, which can be embedded directly into the user s peripheral hardware design. Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows you to focus on hardware peripherals and firmware without expending resources to "re-invent" microcontroller circuitry. Furthermore, much of the value of the phycore module lies in its layout and test. Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce your development time and risk and allow you to focus on your product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative full system solution you will be able to bring your new ideas to market in the most timely and cost-efficient manner. For more information go to: or xii PHYTEC Messtechnik GmbH 0 L-e_

15 Preface Ordering Information The part numbering of the phycore has the following structure: PCM- 0-xxxxxx.Ay Product number (consecutive) Assembly options (depending on model) Version number Product Specific Information and Technical Support In order to receive product specific information on changes and updates in the best way also in the future, we recommend registering at: or For technical support and additional information concerning your product, please visit the product page on our web site which provides product specific information, as well as links to the download section with errata sheets, application notes, etc., and links to FAQs. or : Assembly options include choice of Controller; RAM (Size/Type); Size of NAND Flash, SPI Flash etc.; Interfaces available; Vanishing; Temperature Range; and other features. Please contact our sales team to get more information on the ordering options available. PHYTEC Messtechnik GmbH 0 L-e_ xiii

16 phycore -RK [PCM-0] Declaration of Electro Magnetic Conformity of the PHYTEC phycore -RK PHYTEC System on Module (henceforth products) are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments. Caution! PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence, may only be unpacked, handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD-dangers. It is also necessary that only appropriately trained personnel (such as electricians, technicians and engineers) handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product's pin header rows are longer than m. PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Conformity only in accordance to the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row connectors, power connector and serial interface to a host-pc). Note: Implementation of PHYTEC products into target devices, as well as user modifications and extensions of PHYTEC products, is subject to renewed establishment of conformity to, and certification of, Electro Magnetic Directives. Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems. xiv PHYTEC Messtechnik GmbH 0 L-e_

17 Preface Product Change Management and information in this manual on parts populated on the SOM / SBC With the purchase of a PHYTEC SOM / SBC, you will, in addition to our HW and SW offerings, receive free obsolescence maintenance service for the HW we provide. Our PCM (Product Change Management) Team of developers is continuously processing all incoming PCNs (Product Change Notifications) from vendors and distributors concerning parts which are being used in our products. Possible impacts to the functionality of our products, due to changes of functionality or obsolesce of a certain part, are being evaluated in order to take the right measures in purchasing or within our HW/SW design. Our general philosophy here is: We never discontinue a product as long as there is demand for it. Therefore we have established a set of methods to fulfill our philosophy: Avoiding strategies: Avoid changes by evaluating long-livety of parts during design-in phase. Ensure availability of equivalent second source parts. Stay in close contact with part vendors to be aware of roadmap strategies. Change management in the rare event of an obsolete and non-replaceable part: Ensure long term availability by stocking parts through last time buy management according to product forecasts. Offer long term frame contract to customers. Change management in case of functional changes: Avoid impacts on product functionality by choosing equivalent replacement parts. Avoid impacts on product functionality by compensating changes through HW redesign or backward compatible SW maintenance. Provide early change notifications concerning functional relevant changes of our products. Therefore we refrain from providing detailed part specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products. In order to receive reliable, up to date and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual. PHYTEC Messtechnik GmbH 0 L-e_ xv

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19 Introduction Introduction The phycore-rk belongs to PHYTEC s phycore System on Module family. The phycore SOMs represent the continuous development of PHYTEC System on Module technology. Like its mini-, micro- and nanomodul predecessors, the phycore boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments. As independent research indicates that approximately 0 % of all EMI (Electro Magnetic Interference) problems stem from insufficient supply voltage grounding of electronic components in high frequency environments, the phycore board design features an increased pin package. The increased pin package allows dedication of approximately 0 % of all connector pins on the phycore boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phycore boards even in high noise environments. phycore boards achieve their small size through modern SMD technology and multi-layer design. In accordance with the complexity of the module, 00-packaged SMT components and laser-drilled microvias are used on the boards, providing phycore users with access to this cutting edge miniaturization technology for integration into their own design. The phycore-rk is a subminiature ( mm x mm) insert-ready System on Module populated with the Rockchip Electronics RK microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to high-density pitch (0. mm) connectors aligning two sides of the board, allowing it to be plugged like a "big chip" into a target application. Precise specifications for the controller populating the board can be found in the applicable controller technical reference manual or datasheet. The descriptions in this manual are based on the Rockchip Electronics RK. No description of compatible microcontroller derivative functions is included, as such functions are not relevant for the basic functioning of the phycore-rk. Note: Most of the controller pins have multiple multiplexed functions. As most of these pins are connected directly to the phycore-connector the alternative functions are available by using the RK's pin muxing options. However, the following list of features is in regard to the specification of the phycore-rk and the functions defined therein. Therefore the indicated number of certain interfaces, CS signals, etc. is perhaps smaller than available on the controller. PHYTEC Messtechnik GmbH 0 L-e_

20 phycore -RK [PCM-0] Please refer to the RK Technical Reference Manual to get to know about alternative functions. In order to utilize a specific pin's alternative function the corresponding registers must be configured within the appropriate driver of the BSP.. Features of the phycore-rk The phycore-rk offers the following features: Insert-ready, sub-miniature ( mm x mm) System on Module (SOM) subassembly in low EMI design, achieved through advanced SMD technology Populated with the Rockchip Electronics RK microcontroller (FCBGALD packaging) Max.. GHz core clock frequency Boot from different memory devices (NAND Flash (standard)) Controller signals and ports extend to two 0-pin high-density (0. mm) Samtec connectors aligning two sides of the board, enabling the phycore-rk to be plugged like a "big chip" into target application Single supply voltage of + V with on-board power management Option to power the module by battery All controller required supply voltages are generated on board Supply voltages for components on a carrier board available on the phycore- Connector Battery charging functionality Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins Two banks with GB (up to GB ) DDR SDRAM GB (up to GB ) on-board emmc (MLC) MB SPI NOR Flash kb I C EEPROM (up to kb ) Three serial interfaces (TTL). Two with lines allowing simple hardware handshake High-speed USB OTG.0 interface Two High-Speed USB host.0 interfaces One HSIC interface (USB.0 compliant) 0/00/000 Mbit/s Ethernet interface. Either with an Ethernet transceiver on the phycore-rk, allowing for direct connection to an existing Ethernet network, or without on-board transceiver and provision of the RGMII signals at TTL-level at the phycore-connector instead Four I C interfaces Three SPI interfaces One I S interface with one input and four output channels : The maximum memory size listed is as of the printing of this manual. Please contact PHYTEC for more information about additional, or new module configurations available. : Please refer to the order options described in the Preface, or contact PHYTEC for more information about additional module configurations. PHYTEC Messtechnik GmbH 0 L-e_

21 Introduction One SPDIF output Two LVDS LCD interfaces with up to five data lanes each, or one -bit wide parallel LCD interface One HDMI interface One -bit wide parallel camera interface Two MIPI interfaces with data lanes and clock lane each (one as camera interface and one as camera, or display interface) One SDIO card interface ( bit) One SD/MM card interface ( bit) Several dedicated GPIOs Two PWM outputs Three analog inputs (0 bit) One user-programmable LED Power Management IC (PMIC) One Wake Up input Two inputs for temperature measurement Available for different temperature grades (section.) Caution! Samtec connectors guarantee optimal connection and proper insertion of the phycore-rk. Please make sure that the phycore-rk is fully plugged into the mating connectors of the carrier board. Otherwise individual signals may have bad, or no contact. : Almost every controller port which connects directly to the phycore-connector may be used as GPIO by using the RK's pin muxing options. PHYTEC Messtechnik GmbH 0 L-e_

22 phycore -RK [PCM-0]. Block Diagram Figure : Block Diagram of the phycore-rk : The specified direction indicated refers to the standard phycore use of the pin. PHYTEC Messtechnik GmbH 0 L-e_

23 Introduction. phycore-rk Component Placement C C0 C C C C C C U C0 C U R R C C D C C C C0 Z Q J R R0 R C0 U0 R U C C0 C C R TP C C C C U R R0 U R R R0 C0 XT R L R C R R C C0 C U R C C C C C R R C U DMC J J J J0 J J R R R C C C C C L C L C00 U C C R R0 R R R0 C0 C0 C C Z Q R C R Q C0 R J J0 J J J J J J R R R R C C R C0 U J R R R R R J J J J C C C U U C R R0 R J C0 C L C C C C U C L C R L L R XT C C0 C0 C0 C0 C C R C C C C R C0 C0 Figure : phycore-rk Component Placement (PCB., top view) : The layout is identical for. except some minor changes. PHYTEC Messtechnik GmbH 0 L-e_

24 phycore -RK [PCM-0] PHYTEC Messtechnik GmbH 0 L-e_ Figure : phycore-rk Component Placement (PCB., bottom view) C C C C C C C C C C0 C C C C C C C C C C0 C C C C C C C C C C0 C C C C C C C C C C0 C C C C C C C C C C0 C C C C C C C C C C0 D D D D D D D D D D0 D D D D D D D D D D0 D D D D D D D D D D0 D D D D D D D D D D0 D D D D D D D D D D0 D D D D D D D D D D0 X X TP TP Q TP0 TP C Q DMC TP TP TP J TP TP C Q TP X TP TP RN TP TP U Q TP Z Q TP TP0 TP XT X C TP U TP RN J C Z TP L TP C TP C C0 R R R R R R R0 R C C C C R C C C0 R0 C C C R C00 C C C0 C C0 C C C C0 C C R C0 C0 C R0 R R C R C R R C R0 R C R R0 R R R0 C C C C R C R C C C R C C C C C C R R C R R C C C C R C C0 R0 R R R C R C C C C R R C R R C R C C C C C C R R R R0 R0 R0 R R R R C C R C C0 C R C C R R R0 R0 R0 C C R R C0 C C C C0 R R R0 R C C C R C C C C0 C0 C C0 C C C0 C C C C C C C C R C C0 C R C C C C C C C C C C C C C C R R R00 R C C R R C0 C C C0 C C C0 C C C C C R U B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 J J J J0 J C C C0 C C C C C C C0 C C C J C C

25 Introduction. Minimum Requirements to operate the phycore-rk Basic operation of the phycore-rk only requires supply of a +.0 V input voltage with at least A output current and the corresponding GND connection. These supply pins are located at the phycore-connector X: VDD_IN_OTG_OUT: X C, C, D, D0 Connect all + V VCC input pins to your power supply and at least the matching number of GND pins. Corresponding GND: X C, C0, D, D Please refer to section for information on additional GND pins located at the phycore-connector X. Caution! We recommend connecting all available + V input pins to the power supply system on a custom carrier board housing the phycore-rk and at least the matching number of GND pins neighboring the + V pins. In addition, proper implementation of the phycore-rk module into a target application also requires connecting all GND pins. Please refer to section for more information. PHYTEC Messtechnik GmbH 0 L-e_

26 phycore -RK [PCM-0] PHYTEC Messtechnik GmbH 0 L-e_

27 Pin Description Pin Description Please note that all module connections are not to exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller manuals/data sheets. As damage from improper connections varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals. As Figure indicates, all controller signals selected extend to surface mount technology (SMT) connectors (0. mm) lining two sides of the module (referred to as phycore-connector). This allows the phycore-rk to be plugged into any target application like a "big chip". The numbering scheme for the phycore-connector is based on a two dimensional matrix in which column positions are identified by a letter and row position by a number. The pin numbering values increase moving down on the board (Figure ). The numbered matrix can be aligned with the phycore-rk (viewed from above; phycore-connector pointing down), or with the socket of the corresponding phycore Carrier Board/user target circuitry. The upper left-hand corner of the numbered matrix (pin XA) is thus covered with the corner of the phycore-rk. The numbering scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module. The numbering scheme is thus consistent for both the module s phycore-connector as well as the mating connector on the phycore Carrier Board or target hardware, thereby considerably reducing the risk of pin identification errors. Since the pins are exactly defined according to the numbered matrix previously described, the phycore-connector is usually assigned a single designator for its position (X for example). In this manner the phycore-connector comprises a single, logical unit regardless of the fact that it could consist of more than one physical socketed connector. The following figure illustrates the numbered matrix system. It shows a phycore-rk with both SMT phycore-connectors on its underside (defined as dashed lines) mounted on a carrier board. In order to facilitate understanding of the pin assignment scheme, the diagram presents a cross-view of the phycore-rk module showing the phycore- Connector mounted on the underside of the module s PCB. PHYTEC Messtechnik GmbH 0 L-e_

28 phycore -RK [PCM-0] Table to Table provide an overview of the pinout of phycore-connector X with signal names and descriptions specific to the phycore-rk. They also provide the appropriate voltage level, signal type (ST) and a functional grouping of the signals. The signal type includes also information about the signal direction. A description of the signal types can be found in Table. Figure : Pinout of the phycore-connector (top view) Caution! The Rockchip Electronics RK is a multi-voltage operated microcontroller and as such special attention should be paid to the interface voltage levels to avoid unintentional damage to the microcontroller and other on-board components. Please refer to the Rockchip Electronics RK Technical Reference Manual for details on the functions and features of controller signals and port pins. It is mandatory to avoid voltages at the IO pins of the phycore-rk which are sourced from the supply voltage of peripheral devices attached to the SOM during power-up, or power down. These voltages can cause a current flow into the controller, especially if peripheral devices attached to the interfaces of the RK are supposed to be powered while the phycore-rk is in suspend mode, or turned off. To avoid this bus switches either supplied by VDD_SYS on the phycore side, or having their output enable to the SOM controlled by the VDD_SYS signal (section.) must be used. : The specified direction indicated refers to the standard phycore use of the pin. 0 PHYTEC Messtechnik GmbH 0 L-e_

29 Pin Description Note: Most of the controller pins have multiple multiplexed functions. As most of these pins are connected directly to the phycore-connector the alternative functions are available by using the RK's pin muxing options. Signal names and descriptions in Table to Table however, are in regard to the specification of the phycore-rk and the functions defined therein. Please refer to the RK Technical Reference Manual, or the schematic to get to know about alternative functions. In order to utilize a specific pin's alternative function the corresponding registers must be configured within the appropriate driver of the BSP. The following tables describe the full set of signals available at the phycore-connector according to the phycore-rk specification. However, the availability of some interfaces is order-specific (e.g. Ethernet). Thus, some signals might not be available on your module. If the phycore-rk is delivered with a carrier board the pin muxing might be changed within the appropriate BSP in order to support all features of the carrier board. Table lists all pins with functions different from what is described in the following pinout tables. PHYTEC Messtechnik GmbH 0 L-e_

30 phycore -RK [PCM-0] Pin # Signal ST SL Description A X_IC_SCL OD_BI. V IC_SENSOR clock A X_PWM0 PWM. V PWM0 output A X_PWM PWM. V PWM output A X_PMUGPIO0_B I/O. V PMUGPIO0 B A GND - - Ground 0 V A X_SPI_CSN0 I/O. V SPI chip select 0 A X_SPI_RXD I. V SPI master input/slave output (MISO) A X_SPI_TXD O. V SPI master output/slave input (MOSI) A X_SPI_CLK I/O. V SPI clock signal A0 GND - - Ground 0 V A X_CIF_D I. V Camera interface input pixel data A X_CIF_D I. V Camera interface input pixel data A X_CIF_D I. V Camera interface input pixel data A X_CIF_D I. V Camera interface input pixel data A GND - - Ground 0 V A X_CIF_D I. V Camera interface input pixel data A X_CIF_D I. V Camera interface input pixel data A X_CIF_VSYNC I. V Camera interface vertical synchronization A X_CIF_CLKIN I. V Camera interface input pixel clock A0 GND - - Ground 0 V A X_SPI_CSN O. V SPI chip select A X_ADC_IN0 Analog max. V AD-Converter input 0 (SARADC_AIN[0]) A X_ADC_IN Analog max. V AD-Converter input (SARADC_AIN[]) A X_ADC_IN Analog max. V AD-Converter input (SARADC_AIN[]) A GND - - Ground 0 V A X_nEMMC_BOOT_DIS I. V EMMC boot disable A X_IS_SCLK I/O. V I S/PCM bit clock A X_IS_SDO0 O. V I S/PCM serial data output 0 A X_IS_SDO O. V I S/PCM serial data output A0 GND - - Ground 0 V A X_IS_SDI I. V I S/PCM serial data input A X_IS_LRCK_RX I/O. V I S/PCM frame clock for receiving serial data A X_IS_LRCK_TX I/O. V I S/PCM frame clock for transmitting serial data A X_IS_CLK O. V I S/PCM master clock A GND - - Ground 0 V A X_IS_SDO O. V I S/PCM serial data output Table : Pinout of the phycore-connector X, Row A PHYTEC Messtechnik GmbH 0 L-e_

31 Pin # Signal ST SL Description A X_IS_SDO O. V I S serial data output A X_GPIO_B I/O. V GPIO B A X_GPIO_B0 I/O. V GPIO B0 A0 GND - - Ground 0 V Pin Description A X_UART0_RX I. V UART0 serial data receive signal A X_UART0_TX O. V UART0 serial data transmit signal A X_UART0_CTSN I. V UART0 clear to send input A X_UART0_RTSN O. V UART0 request to send output A GND - - Ground 0 V A A A A X_GPIO_A0/MAC_CRS X_PMUGPIO0_B0/MAC_RXCLK X_ETH0_A+/TX0+/MAC_TXD X_ETH0_A-/TX0-/MAC_TXD I/O I I/O I ETH_I/O O ETH_I/O O A0 GND - - Ground 0 V A A A A X_ETH0_B+/RX0+/MAC_TXD X_ETH0_B-/RX0-/MAC_TXD0 X_ETH0_LED0/MAC_RXD X_ETH0_LED/MAC_RXD ETH_I/O O ETH_I/O O OC I OC I A GND - - Ground 0 V A A A A X_ETH0_C+/MAC_TXCLK X_ETH0_C-/MAC_TXEN X_ETH0_D+/MAC_RXDV X_ETH0_D-/MAC_CLK ETH_I/O O ETH_I/O O ETH_I/O I ETH_I/O I/O A0 GND - - Ground 0 V. V GPIO A0. V 0 GMAC RGMII carrier sense signal. V PMU GPIO0 B0. V 0 GMAC RGMII receive clock input. V 0 ETH0 data A+ GMAC RGMII transmit data. V 0 ETH0 data A- GMAC RGMII transmit data. V 0 ETH0 data B+ GMAC RGMII transmit data. V 0 ETH0 data B- GMAC RGMII transmit data 0. V 0 ETH0 link LED control output GMAC RGMII receive data. V 0 ETH0 activity LED control output GMAC RGMII receive data. V 0 ETH0 data C+ (Gbit) GMAC RGMII transmit clock output. V 0 ETH0 data C- (Gbit) GMAC RGMII transmit data enable. V 0 ETH0 data D+ (Gbit) GMAC RGMII receive data valid. V 0 ETH0 data D- (Gbit) GMAC RGMII clock Table : Pinout of the phycore-connector X, Row A (continued) : In order to support all features of the phycore-rk Carrier Board, these pins are used as GPIOs in the standard BSP. Use of these pins in their original function requires changing the BSP. : Caution! If the supply voltage for the SDIO card interface (VDD_SDIO) is configured to. V via jumper J0 the signal level at the UART0 interface is also changed to. V (section ). 0: The voltage level at these pins depends on the configuration of jumper J and can be changed to. V if a different Ethernet PHY is used. PHYTEC Messtechnik GmbH 0 L-e_

32 phycore -RK [PCM-0] Pin # Signal ST SL Description B X_IC_SDA OD_BI. V IC_SENSOR data B X_SPDIF_TX O. V SPDIF output B GND - - Ground 0 V B X_IC_SDA OD_BI. V IC_TP data B X_IC_SCL OD_BI. V IC_TP clock B X_IC_SDA OD_BI. V IC_CAM data B X_IC_SCL OD_BI. V IC_CAM clock B GND - - Ground 0 V B X_CIF_CLOCKOUT O. V Camera interface output work clock B0 X_CIF_D0 I. V Camera interface input pixel data 0 B X_CIF_D I. V Camera interface input pixel data B X_CIF_D I. V Camera interface input pixel data B GND - - Ground 0 V B X_CIF_D I. V Camera interface input pixel data B X_CIF_D I. V Camera interface input pixel data B X_CIF_D0 I. V Camera interface input pixel data 0 B X_CIF_HREF I. V Camera interface horizontal synchronization signal B GND - - Ground 0 V B X_SPI_CLK I/O. V SPI clock signal B0 X_SPI_CSN0 I/O. V SPI chip select 0 B X_SPI_RXD I. V SPI master input/slave output (MISO) B X_SPI_TXD O. V SPI master output/slave input (MOSI) B GND - - Ground 0 V B X_SDIO0_D0 I/O. V SDIO card data 0 B X_SDIO0_D I/O. V SDIO card data B X_SDIO0_D I/O. V SDIO card data B X_SDIO0_D I/O. V SDIO card data B GND - - Ground 0 V B X_SDIO0_CLK O. V SDIO card clock B0 X_SDIO0_CMD I/O. V SDIO card command B X_SDIO0_WRPT I. V SDIO card write protect, =protected B X_SDIO0_PWREN O. V SDIO card power-enable B GND - - Ground 0 V B X_SDIO0_BKPWR O. V Back-end power supply for embedded device B X_SDIO0_INTN O. V SDIO card interrupt indication B X_SDIO0_DET I. V SDIO card detect (active low) Table : Pinout of the phycore-connector X, Row B : The supply voltage for the SDIO card interface (VDD_SDIO) can be changed with jumper J0 to. V. Caution! Changing jumper J0 will also change the signal level at the UART0 interface to. V (section ). PHYTEC Messtechnik GmbH 0 L-e_

33 Pin Description Pin # Signal ST SL Description B X_SPI0_CSN0 I/O. V SPI0 chip select 0 B GND - - Ground 0 V B X_SPI0_CLK I/O. V SPI0 clock signal B0 X_SPI0_TXD O. V SPI0 master output/slave input (MOSI) B X_SPI0_RXD I. V SPI0 master input/slave output (MISO) B X_SPI0_CSN O. V SPI0 chip select B GND - - Ground 0 V B B B B X_GPIO_B/MAC_COL X_PMUGPIO0_A/MAC_RXD0 X_PMUGPIO0_A/MAC_RXD X_GPIO_B/MAC_RXER I/O I I/O I I/O I I/O I/O. V GPIO B. V 0 GMAC RGMII collision signal. V PMU GPIO0 A/. V 0 GMAC RGMII receive data 0. V PMU GPIO0 A. V 0 GMAC RGMII receive data. V GPIO B. V 0 PHY interrupt / PWD control B GND - - Ground 0 V B X_IC_SDA OD_BI. V IC_AUDIO data B0 X_IC_SCL OD_BI. V IC_AUDIO clock B X_PMIC_SNSP I PMIC internal Battery current sense+ B X_PMIC_SNSN I PMIC internal Battery current sense- B GND - - Ground 0 V B X_PMIC_BAT_TS I PMIC internal Thermistor input B X_PMIC_CLKOUT O. V. khz clock output B X_PMIC_nPWRON I. V Power on, 0=on B X_GPIO_A/PMIC_EXT_TS I/O I. V PMIC internal GPIO_A/ Thermistor input B GND - - Ground 0 V B X_MAC_MDC O. V 0 GMAC management interface clock B0 X_MAC_CMD I/O. V 0 GMAC management interface command Table : Pinout of the phycore-connector X, Row B (continued) : Must be enabled by programming the PMIC via the I C interface. : J selects the signal which is connected to pin XB. GPIO_A is brought out in the default configuration (section ). PHYTEC Messtechnik GmbH 0 L-e_

34 phycore -RK [PCM-0] Pin # Signal ST SL Description C X_USBHOST_DM USB_I/O RK internal USB host data minus C X_USBHOST_DP USB_I/O RK internal USB host data plus C X_USBOTG_DM USB_I/O RK internal USB OTG data minus C X_USBOTG_DP USB_I/O RK internal USB OTG data plus C GND - - Ground 0 V C X_UART_RX I. V UART serial data receive signal C X_UART_TX O. V UART serial data transmit signal C X_UART_CTSN I. V UART clear to send input C X_UART_RTSN O. V UART request to send output C0 X_PMUGPIO0_B I/O. V PMU GPIO0 B C GND - - Ground 0 V C X_UART_RX I. V UART serial data receive signal C X_UART_TX O. V UART serial data transmit signal C X_LCDC0_VSYNC O. V LCDC0 vertical synchronization C GND - - Ground 0 V C X_LCDC0_DCLK O. V LCDC0 display clock C X_LCDC0_DEN O. V LCDC0 display enable C C X_LDCD0_D/LVDS_D0N X_LDCD0_D0/LVDS_D0P O LVDS_O O LVDS_O. V/ RK internal. V/ RK internal LCDC0 transmit data LVDS transmit data0- LCDC0 transmit data0 LVDS transmit data0+ C0 GND - - Ground 0 V C C C C X_LDCD0_D/LVDS_DN X_LDCD0_D/LVDS_DP X_LDCD0_D/LVDS_DN X_LDCD0_D/LVDS_DP O LVDS_O O LVDS_O O LVDS_O O LVDS_O. V/ RK internal. V/ RK internal. V/ RK internal. V/ RK internal C GND - - Ground 0 V C C C C X_LDCD0_D/LVDS_DN X_LDCD0_D/LVDS_DP X_LDCD0_D/LVDS_DN X_LDCD0_D/LVDS_DP O LVDS_O O LVDS_O O LVDS_O O LVDS_O. V/ RK internal. V/ RK internal. V/ RK internal. V/ RK internal LCDC0 transmit data LVDS transmit data- LCDC0 transmit data LVDS transmit data+ LCDC0 transmit data LVDS transmit data- LCDC0 transmit data LVDS transmit data+ LCDC0 transmit data LVDS transmit data- LCDC0 transmit data LVDS transmit data+ LCDC0 transmit data LVDS transmit data- LCDC0 transmit data LVDS transmit data+ Table : Pinout of the phycore-connector X, Row C PHYTEC Messtechnik GmbH 0 L-e_

35 Pin # Signal ST SL Description C0 GND - - Ground 0 V C C X_LDCD0_D/LVDS_CLKN X_LDCD0_D/LVDS_CLKP O LVDS_O O LVDS_O. V/ RK internal. V/ RK internal LCDC0 transmit data LVDS transmit clock- LCDC0 transmit data LVDS transmit clock+ Pin Description C X_MIPI_TXRX_CLKN MIPI_I/O RK internal MIPI D-PHY TXRX clock- C X_MIPI_TXRX_CLKP MIPI_I/O RK internal MIPI D-PHY TXRX clock+ C GND - - Ground 0 V C X_MIPI_TXRX_DN MIPI_I/O RK internal MIPI D-PHY TXRX data - C X_MIPI_TXRX_DP MIPI_I/O RK internal MIPI D-PHY TXRX data + C X_MIPI_RX_DP CSI-_I RK internal MIPI D-PHY RX0 receive data + C X_MIPI_RX_DN CSI-_I RK internal MIPI D-PHY RX0 receive data - C0 GND - - Ground 0 V C X_MIPI_RX_CLKP CSI-_I RK internal MIPI D-PHY RX0 receive clock+ C X_MIPI_RX_CLKN CSI-_I RK internal MIPI D-PHY RX0 receive clock- C X_MIPI_RX_DP CSI-_I RK internal MIPI D-PHY RX0 receive data + C X_MIPI_RX_DN CSI-_I RK internal MIPI D-PHY RX0 receive data - C GND - - Ground 0 V C X_HDMI_CEC I/O. V HDMI CEC C X_HDMI_HPD I/O. V HDMI hot plug detect C X_HDMI_SDA OD_BI. V HDMI I C data (IC_SDA) C X_HDMI_SCL OD_BI. V HDMI I C clock(ic_scl) C0 GND - - Ground 0 V C X_HDMI_TX0P TMDS_O RK internal HDMI transmit data 0+ C X_HDMI_TX0N TMDS_O RK internal HDMI transmit data 0- C X_HDMI_TCP TMDS_O RK internal HDMI transmit clock+ C X_HDMI_TCN TMDS_O RK internal HDMI transmit clock- C GND - - Ground 0 V C VDD_SD PWR_O VDD_SD Power SD-card C X_nRESET I/O. V Module reset (active low) C VDD_IN_OTG_OUT PWR_I/O V Main supply input, USB OTG power in/out C VDD_IN_OTG_OUT PWR_I/O V Main supply input, USB OTG power in/out C0 GND - - Ground 0 V Table : Pinout of the phycore-connector X, Row C (continued) PHYTEC Messtechnik GmbH 0 L-e_

36 phycore -RK [PCM-0] Pin # Signal ST SL Description D X_USBHOST_DM USB_I/O RK internal USB host data minus D X_USBHOST_DP USB_I/O RK internal USB host data plus D X_USBOTG_ID I. V USB OTG ID pin D GND - - Ground 0 V D X_HSIC_STROBE I/O. V USB HSIC strobe D X_HSIC_DATA I/O. V USB HSIC data D X_USBOTG_VBUS PWR_I V USB OTG VBUS input D GND - - Ground 0 V D X_SDMMC0_DECTN I. V SD/MMC card detect (0=no card) D0 X_SDMMC0_CMD I/O. V SD/MMC command D X_SDMMC0_CLKOUT O. V SD/MMC clock (JTAG TDO) D X_SDMMC0_D0 I/O. V SD/MMC data 0 (JTAG TMS) D GND - - Ground 0 V D X_SDMMC0_D I/O. V SD/MMC data (JTAG TRSTN) D X_SDMMC0_D I/O. V SD/MMC data (JTAG TDI) D X_SDMMC0_D I/O. V SD/MMC data (JTAG TCK) D X_LCDC0_HSYNC O. V LCDC0 horizontal synchronization D GND - - Ground 0 V D D0 D D X_LDCD0_D/LVDS_DN X_LDCD0_D/LVDS_DP X_LDCD0_D/LVDS_DN X_LDCD0_D/LVDS_DP O LVDS_O O LVDS_O O LVDS_O O LVDS_O. V/ RK internal. V/ RK internal. V/ RK internal. V/ RK internal D GND - - Ground 0 V D D D D X_LDCD0_D/LVDS_DN X_LDCD0_D/LVDS_DP X_LDCD0_D/LVDS_DN X_LDCD0_D/LVDS_DP O LVDS_O O LVDS_O O LVDS_O O LVDS_O. V/ RK internal. V/ RK internal. V/ RK internal. V/ RK internal D GND - - Ground 0 V D X_LDCD0_D/LVDS_CLK0N O LVDS_O. V/ RK internal LCDC0 transmit data LVDS transmit data - LCDC0 transmit data LVDS transmit data + LCDC0 transmit data LVDS transmit data - LCDC0 transmit data LVDS transmit data + LCDC0 transmit data LVDS transmit data - LCDC0 transmit data LVDS transmit data + LCDC0 transmit data LVDS transmit data - LCDC0 transmit data LVDS transmit data + LCDC0 transmit data LVDS transmit clock 0- Table : Pinout of the phycore-connector X, Row D PHYTEC Messtechnik GmbH 0 L-e_

37 Pin Description Pin # Signal ST SL Description D0 D D X_LDCD0_D0/LVDS_CLK0P X_LDCD0_D/LVDS_DN X_LDCD0_D0/LVDS_DP O LVDS_O O LVDS_O O LVDS_O. V/ RK internal. V/ RK internal. V/ RK internal LCDC0 transmit data 0 LVDS transmit clock 0+ LCDC0 transmit data LVDS transmit data - LCDC0 transmit data 0 LVDS transmit data + D GND - - Ground 0 V D X_MIPI_TXRX_DN MIPI_I/O RK internal MIPI D-PHY TXRX data - D X_MIPI_TXRX_DP MIPI_I/O RK internal MIPI D-PHY TXRX data + D X_MIPI_TXRX_DN MIPI_I/O RK internal MIPI D-PHY TXRX data - D X_MIPI_TXRX_DP MIPI_I/O RK internal MIPI D-PHY TXRX data + D GND - - Ground 0 V D X_MIPI_TXRX_D0N MIPI_I/O RK internal MIPI D-PHY TXRX data 0- D0 X_MIPI_TXRX_D0P MIPI_I/O RK internal MIPI D-PHY TXRX data 0+ D X_MIPI_RX_DP CSI-_I RK internal MIPI D-PHY RX0 receive data + D X_MIPI_RX_DN CSI-_I RK internal MIPI D-PHY RX0 receive data - D GND - - Ground 0 V D X_MIPI_RX_D0P CSI-_I RK internal MIPI D-PHY RX0 receive data 0+ D X_MIPI_RX_D0N CSI-_I RK internal MIPI D-PHY RX0 receive data 0- D X_HDMI_TXP TMDS_O RK internal HDMI transmit data + D X_HDMI_TXN TMDS_O RK internal HDMI transmit data - D GND - - Ground 0 V D X_HDMI_TXP TMDS_O RK internal HDMI transmit data + D0 X_HDMI_TXN TMDS_O RK internal HDMI transmit data - D VDD_HDMIV PWR_O V HDMI power out D VDD_V_IO PWR_O. V V I/O power out D GND - - Ground 0 V D VDD_BAT+ PWR_I/O Bat_level Battery positive pin D VDD_BAT+ PWR_I/O Bat_level Battery positive pin D VDD_BAT+ PWR_I/O Bat_level Battery positive pin D VDD_SYS PWR_O VDD_SYS PMIC system voltage out D GND - - Ground 0 V D VDD_IN_OTG_OUT PWR_I/O V Main supply input, USB OTG power in/out D0 VDD_IN_OTG_OUT PWR_I/O V Main supply input, USB OTG power in/out Table : Pinout of the phycore-connector X, Row D (continued) PHYTEC Messtechnik GmbH 0 L-e_

38 phycore -RK [PCM-0] Jumpers For configuration purposes, the phycore-rk has several solder jumpers, some of which have been installed prior to delivery. Figure illustrates the numbering of the solder jumper pads, while Figure and Figure indicate the location and the default configuration of the solder jumpers on the board. Table provides a functional summary of the solder jumpers which can be changed to adapt the phycore-rk to your needs. It shows their default positions, and possible alternative positions and functions. A detailed description of each solder jumper can be found in the applicable chapter listed in the table. Note: Jumpers not listed should not be changed as they are installed with regard to the configuration of the phycore-rk. closed e.g.: J e.g.: J e.g.: J Figure : Typical Jumper Pad Numbering Scheme If manual jumper modification is required please ensure that the board, as well as surrounding components and sockets, remains undamaged while de-soldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. Carefully heat neighboring connections in pairs. After a few alternations, components can be removed with the solder-iron tip. Alternatively, a hot air gun can be used to heat and loosen the bonds. : Due to the small size of the components' footprint it is generally not recommended to change the configuration of the module. If necessary please contact our sales team to get to know how to order the configuration required. 0 PHYTEC Messtechnik GmbH 0 L-e_

39 Jumpers C C0 C C C C C C U C0 C U R R C C D C C C C0 Z Q J R R0 R C0 U0 R U C C0 C C R TP C C C C U R R0 U R R R0 C0 XT R L R C R R C C0 C U R C C C C C R R C U J J J J0 J J DMC R R R C C C C C L C L C00 U C C R R0 R R R0 C0 C0 C C Z Q R C R Q C0 R J J0 J J J J J J R R R R C C R C0 U J R R R R R J J J J C C C U U C R R0 R J C0 C L C C C C U C L C R L L R XT C C0 C0 C0 C0 C C R C C C C R C0 C0 Figure : Jumper Locations (PCB., top view) : The layout is identical for. except some minor changes. PHYTEC Messtechnik GmbH 0 L-e_

40 phycore -RK [PCM-0] PHYTEC Messtechnik GmbH 0 L-e_ Figure : Jumper Locations (PCB., bottom view) TP TP Q TP0 TP C Q DMC TP TP TP J TP TP C Q TP X TP TP RN TP TP U Q TP Z Q TP TP0 TP XT X C TP U TP RN J C Z TP L TP C TP X X C C0 R R R R R R R0 R C C C C R C C C0 R0 C C C R C00 C C C0 C C0 C C C C0 C C R C0 C0 C R0 R R C R C R R C R0 R C R R0 R R R0 C C C C R C R C C C R C C C C C C R R C R R C C C C R C C0 R0 R R R C R C C C C R R C R R C R C C C C C C R R R R0 R0 R0 R R R R C C R C C0 C R C C R R R0 R0 R0 C C R R C0 C C C C0 R R R0 R C C C R C C C C0 C0 C C0 C C C0 C C C C C C C C R C C0 C R C C C C C C C C C C C C C C R R R00 R C C R R C0 C C C0 C C C0 C C C C C R U B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 J J J J0 J C C C0 C C C C C C C0 C C C J C C

41 Jumpers Please pay special attention to the TYPE column in the following table to ensure you are using the correct type of jumper (0 Ω, 0 kω, etc ). The jumpers are 00 package with a / W or better power rating. The jumpers (J = solder jumper) have the following functions: Jumper Description Type Chapter J J - J + + J allows to change the voltage for the Ethernet interface from. V to. V. VDD_V (. V) used for driving the Ethernet interface VDD_V_IO (. V) used for driving the Ethernet interface J through J connect the RGMII interface of the RK either to the on-board Ethernet PHY at U, or to the phycore-connector, to allow use of an external PHY on the carrier board. J to J also allow attaching six RK GPIOs to the phycore- Connector instead of the Ethernet signals. J J + GPIOs are connected to the phycore-connector + RGMII signals are brought out at the phycore- Connector J J open RGMII signals connect to the on-board Ethernet PHY J closed RGMII signals are brought out at the phycore- Connector J connects the write control input of the on-board EEPROM with GND. If this jumper is not populated, the EEPROM is write protected. closed EEPROM is not write protected open EEPROM is write protected Table : Jumper Settings 0 Ω (00) 0 Ω (00) 0 Ω (00) : Caution! The GbE PHY (U) must not be populated on the SOM if the RMII interface is used to connect an external PHY. : Default settings are in bold blue text PHYTEC Messtechnik GmbH 0 L-e_

42 phycore -RK [PCM-0] Jumper Description Type Chapter J J J selects the signal which is brought out on pin XB of the phycore-connector GPIO_A of the RK is connected to phycore- Connector pin XB Thermistor input TS of the PMIC at U is connected to phycore-connector pin XB J0 allows to change the voltage for the SDIO interface (VDD_SDIO) from. V to. V. VDD_V_IO connected to VDD_SDIO.. V used for driving the SDIO card interface + VDD_V connected to VDD_SDIO.. V used for driving the SDIO card interface 0 Ω (00) 0 Ω (00) Table : Jumper Settings (continued) : Caution! If VDD_SDIO is set to. V the signal level at the UART0 interface is also changed to. V. PHYTEC Messtechnik GmbH 0 L-e_

43 Power Power The phycore-rk operates with a USB-level supply voltage ( V) and also offers the option to be powered by a battery. The following sections of this chapter discuss the primary power pins on the phycore-connector X in detail.. Primary System Power (VDD_IN_OTG_OUT, VBATT+) The phycore-rk operates off of a primary voltage supply with a nominal value of + V. On-board switching regulators generate the.0 V,. V,. V,. V,. V and. V voltage supplies required by the RK MCU and on-board components from the primary voltage supplied to the SOM. For proper operation the phycore-rk must be supplied with a voltage source of V % with at least. A output current connected to the VCC pins of phycore- Connector X. VDD_IN_OTG_OUT: X C, C, D, D0 Connect all + V input pins to your power supply and at least the matching number of GND pins. Corresponding GND: X C, C0, D, D Please refer to section for information on additional GND Pins located at the phycore-connector X. Caution! As a general design rule we recommend connecting all GND pins neighboring signals which are being used in the application circuitry. For maximum EMI performance all GND pins should be connected to a solid ground plane. Note: The phycore-rk can also be supplied by a battery pack 0 connected to pins VBATT+ (XD, XD und XD) and GND (XD) at the phycore-connector. In this case the VDD_IN_OTG_OUT pins can serve as source to supply a USB OTG device. : The output current required from the voltage source strongly depends on the module's usage and the load produced. The given value refers to the basic usage of the module. Please see Table for more details. 0: Yet, no battery pack suitable for the phycore-rk- could be approved. Because of that the battery functions are not described herein. Please refer to the RK Power Management System Specifications. PHYTEC Messtechnik GmbH 0 L-e_

44 phycore -RK [PCM-0]. Power Management IC (PMIC) (U) The phycore-rk provides an on-board Power Management IC (PMIC) at position U to generate different voltages required by the microcontroller and the on-board components. Figure presents a graphical depiction of the powering scheme. The PMIC has an on-chip RTC and features different power management functions such as dynamic voltage control, different low power modes and regulator supervision. The PMIC also provides a battery management function, including current and temperature sensing as well as accurate capacity gauging of the battery. In case a battery is attached, it will be charged unless the phycore-rk uses more power than provided by the supply. In this case the battery will discharge and function as an additional power source for the phycore-rk 0. If the phycore-rk is supplied by a battery, a USB device can be supplied with + V via the VDD_IN_OTG_OUT pins, drawing the necessary power from the battery. The RK s X_USBOTG_VBUS is used to determine, whether a + V source is connected to the VDD_IN_OTG_OUT pins. The PMIC is connected to the RK via the on-board I C bus (IC0_PMU). The I C address of the PMIC is 0xC... Power Domains The PMIC has two input voltage rails VDD_IN_OTG_OUT and VBATT+, as can be seen in Figure. VDD_IN_OTG_OUT is supplied from the primary voltage input pins XC, XC, XD, XD0 of the phycore-rk. A battery pack connected to VBATT+ (XD, XD und XD) and GND (XD) can optionally be used to supply the phycore-rk in addition to the voltage source connected to VDD_IN_OTG_OUT, or stand-alone. The following tables summarize the relation between the different voltage rails and the devices on the phycore-rk: Voltage Name Description Connected to VDD_IN_OTG_OUT VDD_BATT+ Table : V main system power supply. V to. V optional battery supply External Supply Voltages U PMIC PHYTEC Messtechnik GmbH 0 L-e_

45 PMIC Output Voltage Name Voltage Connected to BOOST_SW CHARGE_SW_ CHARGE_SW_ POWPATH_VSYS POWPATH_VSYS SW_ SW_ SW_ SW_ VDD_SYS VDD_LOG VDD_GPU. V -. V 0. V -.0 V 0. V -.0 V SW VDD_DDR. V SW VDD_V_IO. V VLDO VDD_ETH_V. V VLDO VDD_V0.0 V VLDO VDD_V_LCD_LDO. V U (PMIC) VCC VCC U (VDD_CPU supply) VIN_ VIN_ U (VDD_MISC_V supply) VIN U (VDD_V_AO supply) VIN phycore-connector XD RK (LOGIC_VDD0 LOGIC_VDD) RK (GPU_VDD0 GPU_VDD) Power RK (DDR0_VDDAO, DDR_VDDAO) VDD_DDRC over Q U (VDD_CPU supply) Enable DDR0_CK, DDR0_CKN over C DDR_CK, DDR_CKN over C VREFAO_DDR0, VREFAO_DDR over voltage dividers R, R and R, R U, U, U, U (DDR-SDRAM) VDD VDD, VDDQ VDDQ RK (USB_AVDD_V, APIO_VDD, APIO_VDD, APIO_VDD, APIO_VDD, LCDC_VDD, DVPIO_VDD, LVDS_AVDD_V) U (PMIC) VCC, VCC VDD_SDIO via J0 (+) U0 (EEPROM) VCC and nwc pull-up D (User LED) U (SPI Flash) VCC, pull-up nhold, nwp U (emmc) VCC VCC phycore-connector XD U VDDAP_0, VDDAP_ Switch VDD_ETH_V over Q and Q from VDD_MISC_V RK (PMU_VDD_V0, USB_AVDD_V0, PLL_AVDD_V0, HSIC_VDD_V ) Switch VDD_V_LCD over Q and Q from VDD_MISC_V Table : Voltages generated by the on-board PMIC (U) : Only PCB. PHYTEC Messtechnik GmbH 0 L-e_

46 phycore -RK [PCM-0] PMIC Output Voltage Name Voltage Connected to VLDO VDD_V0_LCD.0 V VLDO VDD_V_LDO. V RK (EDP_AVDD_V0, HDMI_AVDD_V0, LVDS_AVDD_V0) Switch VDD_V over Q and Q from VDD_MISC_V VLDO VDD_V_EN. V U (VDD_V supply) Enable VLDO VDD_IO_SD. V RK SDMMC0_VDD and SDMMC0 pull-ups VSWOUT VDD_SD. V phycore-connector XC HDMI_V/0mA VDD_HDMIV V phycore-connector XD USB/OTG_0.A_ USB/OTG_0.A_ VDD_IN_OTG_OUT V phycore-connector XC, XC, XD, XD0 BAT_ BAT_ VDD_BATT+. V -. V phycore-connector XD, XD, XD Table : Voltages generated by the on-board PMIC (U) (continued) : Only PCB.. PHYTEC Messtechnik GmbH 0 L-e_

47 Power PMIC RK LDO TP OTG switch LDO VDD_ETH_V HDMI switch LDO VDD_V0 Battery charger power path control LDO LDO VDD_V_LCD_LDO TP VDD_SYS LDO LDO VDD_V0_LCD VDD_V_LDO VDD_SYS Boost converter LDO LDO VSWOUT VDD_V_EN* VDD_IO_SD Buck Buck Buck Buck VDD_LOG VDD_GPU VDD_DDR TLV0 VDD_MISC_V VDD_V_IO FAN VDD_CPU VDD_HDMIV VDD_IN_OTG_OUT VDD_BATT+ VDD_SYS VDD_SD Direct solder connect or Samtec connector X * only PCB. Figure : Powering Scheme of the phycore-rk PHYTEC Messtechnik GmbH 0 L-e_

48 phycore -RK [PCM-0].. Built-in Real Time Clock (RTC) The PMIC populated at U on the module, provides a Real Time Clock (RTC) with alarm and timekeeping functions. It stores the time (seconds/minutes/hours) and date (day/month/ year) information in binary-coded decimal (BCD) code, and can generate one programmable interrupts The timer interrupt is a periodically generated interrupt ( second/ minute/ hour), while the alarm interrupt can be generated a precise time of the day to initiate a wake-up of the platform. The RTC provides to clock outputs. The first clock output (PMIC_CLKKOUT) is always enabled and connected to the RK. The second output (X_PMIC_CLKOUT) is connected to the phycore-connector (XB). It must be enabled by programming the PMIC via the I C interface... PMIC Interrupt The active low interrupt of the PMIC can be triggered by different events that occur on the device (e.g. an alarm from the on-chip RTC). It is available at the interrupt output nint_oc of the PMIC which is connected to the RK's GPIO0_A... Power Management The PMIC provides different power management functions. A signal to control the poweron/off state of the system (X_PMIC_nPWRON) is available at the phycore-connector. The following table shows the power management signal and its function. Signal Pin# Description X_PMIC_nPWRON XB External switch-on control (ON button). The PMIC's response to this signal can be configured in the PMIC registers. See the PMIC's datasheet for more information. Table 0: Power Management Signals : All special functions of the PMIC such as RTC interrupts, use of power groups, etc. require the PMIC to be programmed via I C interface. At the time of delivery only the generation of the required voltages is implemented. Please refer to the Power Management IC's datasheet for more information on how to program the PMIC. 0 PHYTEC Messtechnik GmbH 0 L-e_

49 Power. Supply Voltages for external Devices Several supply voltages are brought out at the phycore-connector to allow supplying components on a carrier board. Use of these supply voltages ensures that the power-up and power down sequencing mandatory for the RK are complied for components on a carrier board, too. The following table lists the supply voltages, the intended purpose and the maximum output current. Voltage Table : Max. output current Pin VDD_HDMIV 0 ma XD VDD_SYS. A XD VDD_SD. A XC Supply Voltages for external Devices Description Derived from VDD_SYS for external HDMI power All internal voltage levels are derived from this voltage Derived from VDD_SYS for SD-card power VDD_V_IO. A XD Supply for general I/O purposes VDD_IN_OTG_OUT 00 A XC, XC, XD, XD0 Power source for USB-OTG appliances (only if the phycore-rk is supplied by a battery) All internal voltage levels on the phycore-rk are derived from VDD_SYS, which in turn is derived from VDD_IN_OTG_OUT and the variable VDD_BATT+. Hence VDD_SYS has a voltage range from. V to. V. In order to follow the power-up and power down sequencing mandatory for the RK, external devices have to be supplied by VDD_SYS, which is brought out at pin XD of the phycore-connector. Use of VDD_SYS ensures that external components are only supplied when the supply voltages of the RK are stable. Caution! Please pay attention to the maximum current output of the supply voltages (Table ) to avoid any disfunction or damage of the module. If devices with a higher power consumption,individual, or in sum, are to be connected to the phycore-rk they should be switched on and off by use of the supply voltages from the module. This way the power-up and power down sequencing will be considered even if the devices are not supplied directly by the supply voltages available from the SOM. Supplying level shifters with the supply voltages from the module allows also converting the signals according to the needs on the custom target hardware. PHYTEC Messtechnik GmbH 0 L-e_

50 phycore -RK [PCM-0] Reset Pin XC on the phycore-connector is designated as active low reset input/output. If used as reset input a reset of the module can be triggered. For this purpose the external reset signal must be connected to the X_nRESET signal and pulled low. When used as reset output, the power down routine of the PMIC must be triggered by the RK. After completion of the power down routine, the PMIC will pull X_nRESET low, effectively resetting the module. In case of a reset, the PMIC will power up the voltage channels in a predetermined order and ms intervals. After powering up all voltages is completed, X_nRESET will be pulled high by the PMIC. PHYTEC Messtechnik GmbH 0 L-e_

51 System Boot System Boot The RK starts its booting sequence by getting the first instructions from internal ROM at address 0xffff0000. Next it steps through all bootable memory devices and checks the ID block. This occurs in a set order and cannot be altered by the user. In order to boot from a desired memory device, devices prior in the preset order can be temporarily shut off. The boot device order is:. NAND Flash. emmc device. SPI NOR Flash. SPI NAND Flash. SD/MM card. USB port Finding a correct ID block in one of these devices will result in the initialization of the DDR- RAM and subsequent running of the boot image. Two signals (X_nEMMC_BOOT_DIS and X_SPI_CLK) can be used to boot from a memory device even though other memory devices prior in the boot order already include a correct ID block. E.g. to boot from SPI NOR Flash even though the emmc device includes a correct ID block already, X_nEMMC_BOOT_DIS must be tied to Ground. To boot from USB port while the emmc memory, the SPI NOR Flash and the SD card contain an ID block, X_nEMMC_BOOT_DIS and X_SPI_CLK must be tied to Ground, and the SD card must be removed. : Not available on the phycore-rk PHYTEC Messtechnik GmbH 0 L-e_

52 phycore -RK [PCM-0] System Memory The phycore-rk provides four types of on-board memory: Banks DDR SDRAM: GB DDR SDRAM (up to GB) emmc (MCL) : GB (up to GB) I²C-EEPROM: kb (up to kb) SPI NOR Flash: MB (up to MB) The following sections of this chapter detail each memory type used on the phycore-rk.. DDR-SDRAM (U-U) The RAM memory of the phycore-rk is comprised of two -bit wide banks, each with two -bit wide DDR-SDRAM chips (U-U bank 0 and U-U bank ). The chips are connected to the special DDR interface called Dynamic Memory Interface (DMC) of the RK microcontroller. The DDR memory is accessible from address 0x to 0xFF Typically the DDR-SDRAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the RAM protocol controller (PCTL) and the PHY controller (PHYCLT) must be initialized by accessing the appropriate configuration registers on the RK controller. Refer to the RK Technical Reference Manual for accessing and configuring these registers.. emmc Flash Memory (U) Use of Flash as non-volatile memory on the phycore-rk provides an easily reprogrammable means of code storage. The emmc Flash memory is connected to the -bit emmc interface of the RK s Mobile Storage Host Controller. The control registers for emmc are mapped between 0xFF0F 0000 and 0xFF For detailed information, please see the RK Technical Reference Manual. The emmc device is programmable with. V. No dedicated programming voltage is required. : The maximum memory size listed is as of the printing of this manual. Please contact PHYTEC for more information about additional, or new module configurations available. PHYTEC Messtechnik GmbH 0 L-e_

53 System Memory. I²C EEPROM (U0) The phycore-rk is populated with a non-volatile kb I C EEPROM at U0. This memory can be used to store configuration data or other general purpose data. This device is accessed through I C port 0 on the RK. The control registers for I C port 0 (IC_PMU) are mapped between addresses 0xFF 0000 and 0xFF Please see the RK Reference Manual for detailed information on the registers. The three lower address bits are fixed to zero. Thus the resulting addresses are 0x0 for the memory array and 0x for the additional ID page. Write protection to the device is accomplished via jumper J. Refer to section.. for further details... EEPROM Write Protection Control (J) Jumper J controls write access to the EEPROM (U0) device. Closing this jumper allows write access to the device, while removing this jumper will cause the EEPROM to enter write protect mode, thereby disabling write access to the device. The following configurations are possible: EEPROM Write Protection State Write access allowed EEPROM is write protected. The protection can be changed by the EEPROM_WP signal (GPIO_) J closed open Table : EEPROM Write Protection States via J. SPI NOR Flash Memory (U) The SPI NOR Flash Memory of the phycore-rk at U is available on most standard configurations of the SOM, and can be used to store configuration data or any other general purpose data. Beside this it can also be used as boot device, and is thus suitable for applications which require a small code footprint or small RTOSes. The NOR Flash memory at U is connected to the third SPI interface SPI of the RK and can be accessed through SPI_CSN0. The control registers for SPI are mapped between addresses 0xFF 0000 and 0xFF Please see the RK Technical Reference Manual for detailed information on the registers. : Defaults are in bold blue text PHYTEC Messtechnik GmbH 0 L-e_

54 phycore -RK [PCM-0] Due to pull-up resistor R the SPI Flash is not write protected in the standard configuration. In order to write protect the SPI Flash R must be removed and a 0 kω resistor must be installed at R. As of the printing of this manual these SPI NOR Flash devices generally have a life expectancy of at least 00,000 erase/program cycles and a data retention rate of 0 years. This makes the SPI Flash a reliable and secure solution to store first and second level bootloaders. PHYTEC Messtechnik GmbH 0 L-e_

55 SD / MMC Card Interfaces SD/MM Card Interfaces The phycore-rk features an SD/MM Card interface. On the phycore-rk the interface signals extend from the controllers Mobile Storage Host Controller to the phycore-connector. Table shows the location of the different interface signals on the phycore-connector. The Mobile Storage Host Controller is fully compatible with SD/Memory Card specifications SD.0 and MMC ver.. The SD/MMC interface supports four data channels, one clock channel, one command channel and one card detect detection channel. Signal Pin # ST SL Description X_SDMMC0_DECTN XD I. V SD/MMC card detect, 0=no card X_SDMMC0_CMD XD0 I/O. V SD/MMC command X_SDMMC0_CLKOUT XD O. V SD/MMC clock X_SDMMC0_D0 XD I/O. V SD/MMC data 0 X_SDMMC0_D XD I/O. V SD/MMC data X_SDMMC0_D XD I/O. V SD/MMC data X_SDMMC0_D XD I/O. V SD/MMC data Table : Location of the SD/MM Card Interface Signals Note: The SD/MM card signals of the Rockchip Electronics RK are multiplexed with the JTAG signals, please see the RK Technical Reference Manual. In the standard configuration the SD/MM card interface is enabled by default. PHYTEC Messtechnik GmbH 0 L-e_

56 phycore -RK [PCM-0] SDIO Card Interface The RK's Mobile Storage Host Controller features two SDIO card interfaces SDIO0 and SDIO. They are fully compatible with the SDIO.0 protocol. The signals of the first interface SDIO0 are available at the phycore-connector of the phycore-rk. The SDIO interface supports four data channels and all necessary control signals (card lock, command, write protect, power-enable, back-end power supply, interrupt indication and detection). Table shows the location of the different interface signals on the phycore-connector. Signal Pin # ST SL Description X_SDIO0_D0 XB I/O. V SDIO0 card data 0 X_SDIO0_D XB I/O. V SDIO0 card data X_SDIO0_D XB I/O. V SDIO0 card data X_SDIO0_D XB I/O. V SDIO0 card data X_SDIO0_CLK XB O. V SDIO0 card clock X_SDIO0_CMD XB0 I/O. V SDIO0 card command output and response input X_SDIO0_WRPT XB I. V SDIO0 card write protect, =protected X_SDIO0_PWREN XB O. V SDIO0 card power-enable X_SDIO0_BKPWR XB O. V Back-end power supply for embedded device X_SDIO0_INTN XB I. V SDIO0 card interrupt indication X_SDIO0_DET XB I. V SDIO0 card detect (active low) Table : Location of the SDIO Card Interface Signals Jumper J0 allows changing the voltage for the SDIO card interface from. V to. V. SDIO Card Supply Voltage J0 VDD_V_IO connected to VDD_SDIO.. V used for driving the SDIO card + interface VDD_V connected to VDD_SDIO.. V used for driving the SDIO card interface + Table : Supply Voltage for SDIO Card via J0 : The supply voltage for the SDIO card interface (VDD_SDIO) can be changed with jumper J0 to. V (Table ). : Caution! If VDD_SDIO is set to. V the signal level at the UART0 interface is also changed to. V. : Defaults are in bold blue text PHYTEC Messtechnik GmbH 0 L-e_

57 Serial Interfaces 0 Serial Interfaces The phycore-rk provides numerous dedicated serial interfaces some of which are equipped with a transceiver to allow direct connection to external devices:. Three high-speed Universal Asynchronous Receiver/Transmitter (UART) interfaces at TTL level derived from UART0, UART and UART of the RK with up to Mbit/s, and IrDA support. Two of them, UART0 and UART, provide hardware flow control (RTS and CTS signals). High-speed Universal Serial Bus On-The-Go (USB OTG).0 interface (extended directly from the RK s USB OTG PHY). Two high-speed USB host.0 interfaces (extended directly from the RK USB host PHY). One High-Speed Inter Chip (HSIC) interface (USB.0 compliant). One Auto-MDIX enabled 0/00/000 Mbit/s Ethernet interface implemented using an Ethernet PHY attached to therk's RGMII interface. Four I C interfaces I C (derived from I C ports,, and of the RK). Three Serial Peripheral Interface (SPI) interface (extended from the three SPI controllers of the RK). I S audio interface with one input and four output channels. One SPDIF interface The following sections of this chapter detail each of these serial interfaces and any applicable configuration jumpers. 0. Universal Asynchronous Interfaces The phycore-rk provides three high-speed universal asynchronous interfaces with up to Mbit/s and two with additional hardware flow control (RTS and CTS signals). The following table shows the location of the signals on the phycore-connector. Signal Pin # ST SL Description X_UART0_RX XA I. V UART0 serial data receive signal X_UART0_TX XA O. V UART0 serial data transmit signal X_UART0_CTSN XA I. V UART0 clear to send input X_UART0_RTSN XA O. V UART0 request to send output X_UART_RX XC I. V UART serial data receive signal X_UART_TX XC O. V UART serial data transmit signal X_UART_RX XC I. V UART serial data receive signal X_UART_TX XC O. V UART serial data transmit signal X_UART_CTSN XC I. V UART clear to send input X_UART_RTSN XC O. V UART request to send output Table : Location of the UART Signals PHYTEC Messtechnik GmbH 0 L-e_

58 phycore -RK [PCM-0] Caution! If the supply voltage for the SDIO card interface (VDD_SDIO) is configured to. V via jumper J0 the signal level at the UART0 interface is also changed to. V (section ). The signals extend from UART0, UART and UART of the RK directly to the phycore- Connector without conversion to RS- level. External RS- transceivers must be attached by the user if RS- levels are required. 0. USB OTG Interface The phycore-rk provides a high-speed USB OTG interface which uses the RK embedded high-speed USB OTG PHY. An external USB Standard-A (for USB host), USB Standard-B (for USB device), or USB mini-ab (for USB OTG) connector is all that is needed to interface the phycore-rk USB OTG functionality. The applicable interface signals can be found on the phycore-connector X as shown in Table. Signal Pin # ST SL Description X_USBOTG_DM XC USB_I/O RK internal USB OTG data minus X_USBOTG_DP XC USB_I/O RK internal USB OTG data plus X_USBOTG_ID XD I. V USB OTG ID pin X_USBOTG_VBUS XD PWR_I V USB OTG VBUS input Table : Location of the USB OTG Signals 0. USB Host Interface The phycore-rk provides two high-speed USB host interfaces, which use the RK s embedded high-speed USB host PHYs. An external USB Standard-A (for USB host) connector is all that is needed to interface the phycore-rk USB host functionality. The applicable interface signals can be found on the phycore-connector X as shown in Table. If overcurrent and power enable signals are needed for the USB host interface, the functionality can be easily implemented with GPIOs (please see the phycore-rk Carrier Board schematics for a reference circuit). Signal Pin # ST SL Description X_USBHOST_DM XC USB_I/O RK internal USB host data minus X_USBHOST_DP XC USB_I/O RK internal USB host data plus X_USBHOST_DM XD USB_I/O RK internal USB host data minus X_USBHOST_DP XD USB_I/O RK internal USB host data plus Table : Location of the USB Host Signals 0 PHYTEC Messtechnik GmbH 0 L-e_

59 Serial Interfaces Note: USB host does not support USB.! 0. USB HSIC Interface The phycore-rk provides an USB.0 High-Speed Inter-Chip interface (HSIC). The HSIC interface is a chip-to-chip variant of USB.0 that eliminates the conventional analog transceivers found in normal USB. It is compliant with the High-Speed Inter-Chip Electrical Specification and the Enhanced Host Controller Interface (EHCI) Specification.0. The interface supports highspeed (0 Mbps) transfers and uses only two contacts on phycore-connector X as shown in Table. Note: During development of a custom carrier board ensure the routing distance between the phycore-connector and the device connected to the USB HSIC interface is as short as possible. The maximum PCB trace length for HSIC is 0 cm. Signal Pin # ST SL Description X_HSIC_STROBE XD I/O. V USB HSIC strobe X_HSIC_DATA XD I/O. V USB HSIC data Table : HSIC Interface Signal Location 0. Ethernet Interface Connection of the phycore-rk to the World Wide Web or a local area network (LAN) is possible using the on-board Gigabit Ethernet PHY at U. It is connected to the RGMII interface of the RK. The PHY operates with a data transmission speed of 0 Mbit/s, 00 Mbit/s or 000 Mbit/s. Alternatively the RGMII interface signals are available on the phycore-connector and can be used to connect an external PHY. In this case, the on-board GbE PHY at U must not be populated (section 0..). 0.. Ethernet PHY (U) With an Ethernet PHY mounted at U the phycore-rk has been designed for use in 0Base-T, 00Base-T and 000Base-T networks. The 0/00/000Base-T interface with its LED signals extends to the phycore-connector X. The following table shows the location of the signals on the phycore-connector. PHYTEC Messtechnik GmbH 0 L-e_

60 phycore -RK [PCM-0] Signal Pin # ST SL Description X_ETH0_A+/TX0+/MAC_TXD XA ETH_I/O. V ETH0 data A+ X_ETH0_A-/TX0-/MAC_TXD XA ETH_I/O. V ETH0 data A- X_ETH0_B+/RX0+/MAC_TXD XA ETH_I/O. V ETH0 data B+ X_ETH0_B-/RX0-/MAC_TXD0 XA ETH_I/O. V ETH0 data B- X_ETH0_LED0/MAC_RXD XA OC. V ETH0 link LED control output X_ETH0_LED/MAC_RXD XA OC. V ETH0 activity LED control output X_ETH0_C+/MAC_TXCLK XA ETH_I/O. V ETH0 data C+ (Gbit) X_ETH0_C-/MAC_TXEN XA ETH_I/O. V ETH0 data C- (Gbit) X_ETH0_D+/MAC_RXDV XA ETH_I/O. V ETH0 data D+ (Gbit) X_ETH0_D-/MAC_CLK XA ETH_I/O. V ETH0 data D- (Gbit) Table 0: Location of the Ethernet Signals The on-board GbE PHY supports HP Auto-MDIX technology, eliminating the need for the consideration of a direct connect LAN cable, or a cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an Auto-negotiation to automatically determine the best speed and duplex mode. The Ethernet PHY is connected to the RGMII interface of the RK. Please refer to the RK Technical Reference Manual for more information about this interface. In order to connect the module to an existing 0/00/000Base-T network adding an RJ connector and appropriate magnetic devices to your design is required. The required termination resistors on the analog signals (ETH0_A±, ETH0_B±, ETH0_C±, and ETH0_D±) are integrated in the chip, hence there is no need to connect external termination resistors to these signals. Connection to an external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C- and D+/D- signals should be routed as 00 Ohm differential pairs. The same applies for the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals. If you are using the applicable carrier board for the phycore-rk (part number PCM-), the external circuitry mentioned above is already integrated on the board (section..). Note: During development of a custom carrier board ensure the routing distance between the phycore-connector and the Ethernet connector is as short as possible. PHYTEC Messtechnik GmbH 0 L-e_

61 Serial Interfaces Caution! Please see the datasheet of the Ethernet PHY when designing the Ethernet transformer circuitry or request the schematic of the applicable carrier board (PCM-.x) as reference Ethernet Interface Voltage Jumper J allows to change the voltage for the Ethernet interface from. V to. V. SD Card Supply Voltage VDD_V (. V) used for driving the Ethernet interface + VDD_V_IO (. V) used for driving the Ethernet interface + Table : Ethernet Interface Voltage via J 0 J Software Reset of the Ethernet Controller The Ethernet PHY at U can be reset by software. The reset input of the Ethernet PHY is permanently connected to the signal MAC_COL of the RK. 0.. MAC Address In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the Internet, a table is used to convert the assigned IP number to the hardware s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phycore-rk is located on the bar code sticker attached to the module. This number is a -digit HEX value. 0.. RGMII Interface In order to use an external Ethernet PHY instead of the on-board GbE PHY at U, the RMII interface of the RK is brought out at phycore-connector X as shown in Table. In order to route the RGMII signals to X jumpers J to J must be configured. J to J must be set to +, while jumpers J to J must be closed. Please see Table for more information. 0: Defaults are in bold blue text PHYTEC Messtechnik GmbH 0 L-e_

62 phycore -RK [PCM-0] Caution! The GbE PHY (U) must not be populated on the module and the jumper configuration must be adapted as described above if the RMII interface is used to connect an external PHY. Note: It is strongly recommended to place the Ethernet PHY on the carrier board close to the pins of the SOM's Ethernet interface to achieve a trace length of less than 00 mm. Signal Pin # ST SL Description X_MAC_MDC XB O. V GMAC management interface clock X_MAC_CMD XB0 I/O. V GMAC management interface command X_GPIO_A0/MAC_CRS XA I. V GMAC RGMII carrier sense signal X_PMUGPIO0_B0/MAC_RXCLK XA I. V GMAC RGMII receive clock input X_ETH0_A+/TX0+/MAC_TXD XA O. V GMAC RGMII transmit data X_ETH0_A-/TX0-/MAC_TXD XA O. V GMAC RGMII transmit data X_ETH0_B+/RX0+/MAC_TXD XA O. V GMAC RGMII transmit data X_ETH0_B-/RX0-/MAC_TXD0 XA O. V GMAC RGMII transmit data 0 X_ETH0_LED0/MAC_RXD XA I. V GMAC RGMII receive data X_ETH0_LED/MAC_RXD XA I. V GMAC RGMII receive data X_ETH0_C+/MAC_TXCLK XA O. V GMAC RGMII transmit clock output X_ETH0_C-/MAC_TXEN XA O. V GMAC RGMII transmit data enable X_ETH0_D+/MAC_RXDV XA I. V GMAC RGMII receive data valid X_ETH0_D-/MAC_CLK XA I/O. V GMAC RGMII clock X_GPIO_B/MAC_COL XB I. V GMAC RGMII collision signal X_PMUGPIO0_A/MAC_RXD0 XB I. V GMAC RGMII receive data 0 X_PMUGPIO0_A/MAC_RXD XB I. V GMAC RGMII receive data X_GPIO_B/MAC_RXER XB I. V PHY interrupt / PWD control Table : Location of the RGMII Interface Signals : Due to the small size of the components' footprint it is not recommended to change the configuration of the module. Please contact our sales team to get to know how to order the configuration required. : The voltage level at these pins depends on the configuration of jumper J and can be changed to. V if a different Ethernet PHY is used. PHYTEC Messtechnik GmbH 0 L-e_

63 Serial Interfaces 0. SPI Interface The Serial Peripheral Interface (SPI) interface is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The RK includes three SPI controllers which are master/slave configurable. The phycore provides the signals of all three SPI controllers on the phycore-connector X. SPI provides one chip select signal, while SPI0 and SPI provide two chip select signals each. The following table lists the SPI signals on the phycore-connector X. Signal Pin # ST SL Description X_SPI0_CSN0 XB I/O. V SPI0 chip select 0 X_SPI0_CLK XB I/O. V SPI0 clock signal X_SPI0_TXD XB0 O. V SPI0 master output/slave input (MOSI) X_SPI0_RXD XB I. V SPI0 master input/slave output (MISO) X_SPI0_CSN XB O. V SPI0 chip select X_SPI_CSN0 XA I/O. V SPI chip select 0 X_SPI_RXD XA I. V SPI master input/slave output (MISO) X_SPI_TXD XA O. V SPI master output/slave input (MOSI) X_SPI_CLK XA I/O. V SPI clock signal X_SPI_CSN XA O. V SPI chip select X_SPI_CLK XB I/O. V SPI clock signal X_SPI_CSN0 XB0 I/O. V SPI chip select 0 X_SPI_RXD XB I. V SPI master input/slave output (MISO) X_SPI_TXD XB O. V SPI master output/slave input (MOSI) Table : SPI Interface Signal Location Note: When using the SPI interface it must be considered that the on-board SPI Flash is connected to this interface, too. The SPI Flash is accessed through SPI_CSN0 (section.). PHYTEC Messtechnik GmbH 0 L-e_

64 phycore -RK [PCM-0] 0. I C Interfaces The Inter-Integrated Circuit (I C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The RK contains six identical and independent multimaster fast-mode I C controller with up to 00 Kbit/s data rate. The interface of the second, third, fourth and fifth controller (IC_SENSOR, IC_AUDIO, IC_CAM and IC_TP) are available on the phycore- Connector. The first I C controller (IC0_PMU) connects to the on-board EEPROM at U0 (section.), the PMIC at U (section.), the programmable voltage regulator at U, and the -bit MCU at U. Note: To ensure the proper functioning of the I C interface external pull resistors matching the load at the interface must be connected. There are no pull up resistors mounted on the module. The following table lists the pins of the I C ports on the phycore-connector. Signal Pin # ST SL Description X_IC_SCL XA OD_BI. V IC_SENSOR clock X_IC_SDA XB OD_BI. V IC_SENSOR data X_IC_SDA XB OD_BI. V IC_AUDIO data X_IC_SCL XB0 OD_BI. V IC_AUDIO clock X_IC_SDA XB OD_BI. V IC_CAM data X_IC_SCL XB OD_BI. V IC_CAM clock X_IC_SDA XB OD_BI. V IC_TP data X_IC_SCL XB OD_BI. V IC_TP clock Table : I C Interface Signal Location As I C devices on the SOM connect to IC0_PMU of the RK, I C interfaces IC to IC are fully available for connecting external I C devices to the phycore-rk. PHYTEC Messtechnik GmbH 0 L-e_

65 Serial Interfaces 0. I S Audio Interface The Inter-IC Sound interface (I²S) of the phycore-rk is a serial interface that allows to communicate with a variety of serial devices, such as standard codecs, digital signal processors (DSPs), microprocessors, peripherals, and popular industry audio codecs that implement the Inter-IC Sound bus standard. It provides four output and one input channel with a sample rate of up to khz and an audio resolution from to bit. The three supported I²S formats are normal, left-justified and right-justified. In addition the RK supports also PCM mode surround audio output (up to. channel) and stereo input. For detailed information on the I²S/PCM audio interface please see the RK Technical Reference Manual. Table shows the I²S signals on the phycore-connector X. Signal Pin # ST SL Description X_IS_SCLK XA I/O. V I S/PCM bit clock X_IS_SDO0 XA O. V I S/PCM serial data output 0 X_IS_SDO XA O. V I S/PCM serial data output X_IS_SDI XA I. V I S/PCM serial data input X_IS_LRCK_RX XA I/O. V I S/PCM frame clock for receiving serial data X_IS_LRCK_TX XA I/O. V I S/PCM frame clock for transmitting serial data X_IS_CLK XA O. V I S/PCM serial master clock X_IS_SDO XA O. V I S/PCM serial data output X_IS_SDO XA O. V I S/PCM serial data output Table : I S Interface Signal Location 0. SPDIF Interface The SPDIF transmitter of the RK provides a self-clocking, serial, unidirectional interface with two channels. The SPDIF interface can be used to connect digital audio equipment and other compliant devices for consumer and professional applications, using linear PCM coded audio samples. Table shows the SPDIF signal on phycore-connector X. Signal Pin # ST SL Description X_SPDIF_TX XB O. V SPDIF output Table : SPDIF Interface Signal Location : In order to support all features of the phycore-rk Carrier Board, these pins are used as GPIOs in the standard BSP. Use of these pins in their original function requires changing the BSP. PHYTEC Messtechnik GmbH 0 L-e_

66 phycore -RK [PCM-0] General Purpose I/Os Even though many of the phycore-rk pins which are directly connected to the RK can be configured to act as GPIO, five pins have been especially dedicated as GPIOs Table lists the pins defined as GPIO. Signal Pin # ST SL Description X_PMUGPIO0_B XA I/O. V PMU GPIO0 B X_PMUGPIO0_B XC0 I/O. V PMU GPIO0 B X_GPIO_B XA I/O. V GPIO B X_GPIO_B0 XA I/O. V GPIO B0 X_GPIO_A/PMIC_EXT_TS XB I/O. V GPIO A Table : GPIOs for unrestricted Use The phycore-rk also offers additional GPIOs, which are available when the on-board Ethernet PHY is used. Table shows the signals on X. Signal Pin # ST SL Description X_PMUGPIO0_A/MAC_RXD XB I/O. V PMU GPIO0 A X_PMUGPIO0_A/MAC_RXD0 XB I/O. V PMU GPIO0 A X_PMUGPIO0_B0/MAC_RXCLK XA I/O. V PMU GPIO0 B0 X_GPIO_B/MAC_RXER XB I/O. V GPIO B X_GPIO_B/MAC_COL XB I/O. V GPIO B X_GPIO_A0/MAC_CRS XA I/O. V GPIO A0 Table : Additional GPIOs usable with Restrictions Note: To support all features of the phycore-rk Carrier Board special functions have been assigned to the GPIOs in the BSP delivered with the module. In order to otherwise utilize the GPIOs the software must be changed. Table lists the functions assigned to the GPIO pins. : J allows selecting the signal which is connected to pin XB. GPIO_A is brought out in the default configuration. Alternatively PMIC_EXT_TS can be brought out at pin XB (section ). PHYTEC Messtechnik GmbH 0 L-e_

67 Analog Inputs Analog Inputs The phycore-rk provides three analog input signals. The analog inputs connect to the -channel signal-ended 0-bit Successive Approximation Register (SAR) analog/digital converter of the Rockchip RK. Table lists the location of the analog input signals. Signal Pin # ST SL Description X_ADC_IN0 XA Analog max.. V AD-Converter input 0 (SARADC_AIN[0]) X_ADC_IN XA Analog max.. V AD-Converter input (SARADC_AIN[]) X_ADC_IN XA Analog max.. V AD-Converter input (SARADC_AIN[]) Table : Location of the Analog Inputs Note: Care should be taken in designing the carrier board layout to isolate these analog signals from noise such as from power supplies or other digital signals PHYTEC Messtechnik GmbH 0 L-e_

68 phycore -RK [PCM-0] User LED The phycore-rk provides one green user LED (D) on board. It can be controlled by setting GPIO_A to the desired output level. A high-level turns the LED on, a low-level turns it off. C C0 C C C C C C U C0 C U R R C C D C C C C0 Z Q J R R0 R C0 U0 R U C C0 C C R TP C C C C U R R0 U R R R0 C0 XT R L R C R R C C0 U C R C C C C C R R C U J J J J0 J J DMC R R R C C C C C L C L C00 U C C R R0 R R R0 C0 C0 C C Z Q C R R Q C0 R J J0 J J J J J J R R R R C C R C0 U J R R R R R J J J J C C C U U R R0 R C J C0 C L C C C C U C L C R L L R C C0 C0 C0 C0 C C R C C C C XT R C0 C0 Figure : User LED Location (PCB., top view) : The layout is identical for. except some minor changes. 0 PHYTEC Messtechnik GmbH 0 L-e_

69 Debug Interfaces Debug Interface The phycore-rk is equipped with a JTAG interface for downloading program code into the external flash, internal controller RAM or for debugging programs currently executing. The Rockchip RK supports also Serial Wire Debug (SWD) which is a -pin alternative to the traditional IEEE. compliant interface (JTAG). Note: The JTAG signals of the Rockchip Electronics RK are multiplexed with the SD/MM card signals and disabled by default. In order to utilize the JTAG interface of the phycore-rk at phycore-connector X the software must be changed. For detailed information on the process of enabling the JTAG interface, please see the RK Technical Reference Manual. Table 0 shows the location of the JTAG pins on the phycore-connector. Signal Pin # ST SL Description X_SDMMC0_CLKOUT XD O. V JTAG Test Data Output (TDO) JTAG Test Mode Select (TMS) X_SDMMC0_D0 XD I. V Serial Wire Debug (SWD) interface data input/output X_SDMMC0_D XD I. V JTAG Test Reset Input (TRSTN) (active low) X_SDMMC0_D XD I. V JTAG Test Data Input (TDI) X_SDMMC0_D XD I. V JTAG Test Clock Input (TCK) Serial Wire Debug (SWD) interface clock input Table 0: Debug Interface Signal Location PHYTEC Messtechnik GmbH 0 L-e_

70 phycore -RK [PCM-0] Display Interfaces The phycore-rk provides a configurable parallel display interface with up to data bits, as well as backlight control. It is also possible to convert the signals by the RK's on-chip LVDS transmitters. Two LVDS interfaces with five data lanes and one clock lane each are available at the same pins of the phycore Connector as the parallel display interface. In addition one MIPI display interface (MIPI D-PHY TXRX) of the RK is brought out at the phycore Connector (section.).. Parallel Display Interface The parallel display signals from the integrated Visual Output Processor (VOP) of the RK are brought out at the phycore-connector X. Thus an LCD interface with up to -bit bus width can be connected directly to the phycore-rk. The table below shows the location of the applicable interface signals. Signal Pin # ST SL Description X_LCDC0_DCLK XC O. V LCDC0 display clock X_LCDC0_DEN XC O. V LCDC0 display enable X_LCDC0_VSYNC XC O. V LCDC0 vertical synchronization X_LCDC0_HSYNC XD O. V LCDC0 horizontal synchronization X_LDCD0_D0/LVDS_D0P XC O. V LCDC0 transmit data 0 X_LDCD0_D/LVDS_D0N XC O. V LCDC0 transmit data X_LDCD0_D/LVDS_DP XD0 O. V LCDC0 transmit data X_LDCD0_D/LVDS_DN XD O. V LCDC0 transmit data X_LDCD0_D/LVDS_DP XD O. V LCDC0 transmit data X_LDCD0_D/LVDS_DN XD O. V LCDC0 transmit data X_LDCD0_D/LVDS_DP XD O. V LCDC0 transmit data X_LDCD0_D/LVDS_DN XD O. V LCDC0 transmit data X_LDCD0_D/LVDS_DP XD O. V LCDC0 transmit data X_LDCD0_D/LVDS_DN XD O. V LCDC0 transmit data X_LDCD0_D0/LVDS_CLK0P XD0 O. V LCDC0 transmit data 0 X_LDCD0_D/LVDS_CLK0N XD O. V LCDC0 transmit data X_LDCD0_D/LVDS_DP XC O. V LCDC0 transmit data X_LDCD0_D/LVDS_DN XC O. V LCDC0 transmit data X_LDCD0_D/LVDS_DP XC O. V LCDC0 transmit data X_LDCD0_D/LVDS_DN XC O. V LCDC0 transmit data Table : Parallel Display Interface Signal Location PHYTEC Messtechnik GmbH 0 L-e_

71 Display Interfaces Signal Pin # ST SL Description X_LDCD0_D/LVDS_DP XC O. V LCDC0 transmit data X_LDCD0_D/LVDS_DN XC O. V LCDC0 transmit data X_LDCD0_D/LVDS_DP XC O. V LCDC0 transmit data X_LDCD0_D/LVDS_DN XC O. V LCDC0 transmit data X_LDCD0_D0/LVDS_DP XD O. V LCDC0 transmit data 0 X_LDCD0_D/LVDS_DN XD O. V LCDC0 transmit data X_LDCD0_D/LVDS_CLKP XC O. V LCDC0 transmit data X_LDCD0_D/LVDS_CLKN XC O. V LCDC0 transmit data Table : Parallel Display Interface Signal Location (continued). LVDS Display Interface The LVDS signals from both channels of the RK on-chip LVDS transmitter are brought out at phycore-connector X. Thus up to two LVDS displays, with five data lanes and one clock lane each, can be connected directly to the phycore-rk. The signals comply with TIA/EIA--A LVDS standard. The location of the applicable interface signals can be found in Table : below. Signal Pin # ST SL Description X_LDCD0_D/LVDS_CLK0N XD LVDS_O RK internal LVDS transmit clock0- X_LDCD0_D0/LVDS_CLK0P XD0 LVDS_O RK internal LVDS transmit clock0+ X_LDCD0_D/LVDS_D0N XC LVDS_O RK internal LVDS transmit data 0- X_LDCD0_D0/LVDS_D0P XC LVDS_O RK internal LVDS transmit data 0+ X_LDCD0_D/LVDS_DN XD LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_DP XD0 LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN XD LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_DP XD LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN XD LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_DP XD LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN XD LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_DP XD LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_CLKN XC LVDS_O RK internal LVDS transmit clock - X_LDCD0_D/LVDS_CLKP XC LVDS_O RK internal LVDS transmit clock + X_LDCD0_D/LVDS_DN XC LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_DP XC LVDS_O RK internal LVDS transmit data + Table : LVDS Display Interface Signal Location PHYTEC Messtechnik GmbH 0 L-e_

72 phycore -RK [PCM-0] Signal Pin # ST SL Description X_LDCD0_D/LVDS_DN XC LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_DP XC LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN XC LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_DP XC LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN XC LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_DP XC LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN XD LVDS_O RK internal LVDS transmit data - X_LDCD0_D0/LVDS_DP XD LVDS_O RK internal LVDS transmit data + Table : LVDS Display Interface Signal Location (continued) The LVDS transmitter can work in single or double channel mode. LVDS transmit clock0 is needed for data lanes 0 to and LVDS transmit clock is needed for data lanes to. It is possible to use a single display with all ten data lanes, nevertheless both transmit clocks must be connected for this purpose.. Supplementary Signals The two PWM signals X_PWM0 and X_PWM can be used to control the display brightness. Pin # Signal ST SL Description XA X_PWM0 PWM. V PWM0 output (e.g. to control the brightness) XA X_PWM PWM. V PWM output (e.g. to control the brightness) Table : Supplementary Signals to support the Display Connectivity Note: In addition a GPIO, e.g. GPIO_A as on the phycore-rk Carrier Board, can be used to enable or disable a display.. MIPI Display Interfaces The RK includes three D-PHYs which are compliant with the MIPI D-PHY interface specification, revision.. One is for DSI (D-PHY TX0), one is for CSI (D-PHY RX0) and the third one can be configure d to DSI or CSI (D-PHY TXRX). On the phycore_rk only D-PHY RX0 and D-PHY TXRX are available at phycore Connector X with four data lanes and one clock lane each (Table ). D-PHY TXRX can be used to connect a display to the phycore-rk. Please refer to section for additional information about the location of the MIPI signals on the phycore Connector. PHYTEC Messtechnik GmbH 0 L-e_

73 High-Definition Multimedia Interface (HDMI) High-Definition Multimedia Interface (HDMI) The High-Definition Multimedia Interface (HDMI) of the phycore-rk is compliant to HDMI.a and HDMI.0a operation. It supports a maximum pixel clock of up to 00 MHz, HDTV resolutions of up to 00p at 0 Hz, or k x k at 0 Hz, and a graphic display resolutions of up to 0x (QXGA). Please refer to the RK Technical Reference Manual for more information. The following table shows the location of the HDMI signals on the phycore-connector X. Signal Pin # ST SL Description X_HDMI_TCP XC TMDS_O RK internal HDMI transmit clock+ X_HDMI_TCN XC TMDS_O RK internal HDMI transmit clock- X_HDMI_TX0P XC TMDS_O RK internal HDMI transmit data0+ X_HDMI_TX0N XC TMDS_O RK internal HDMI transmit data0- X_HDMI_TXP XD TMDS_O RK internal HDMI transmit data + X_HDMI_TXN XD0 TMDS_O RK internal HDMI transmit data - X_HDMI_TXP XD TMDS_O RK internal HDMI transmit data + X_HDMI_TXN XD TMDS_O RK internal HDMI transmit data - X_HDMI_CEC XC I/O - HDMI CEC X_HDMI_HPD XC I/O VDD_V_IO HDMI hot plug detect X_HDMI_SDA XC OD_BI VDD_V_IO HDMI I C data (IC_SDA) X_HDMI_SCL XC OD_BI VDD_V_IO HDMI I C clock (IC_SCL) VDD_HDMIV XD PWR_O VDD_HDMIV HDMI power out Table : HDMI Interface Signal Location at X As the signals extend directly from the RK's HDMI PHY a standard HDMI connector, a V level shifter for the DDC (HDMI_SDA, HDMI_SCL) and the CEC signals and an optional ESD circuit protection device is all that is needed to interface the phycore-rk's HDMI functionality. PHYTEC Messtechnik GmbH 0 L-e_

74 phycore -RK [PCM-0] Mobile Industry Processor Interface (MIPI) The RK includes three D-PHYs which are compliant with the MIPI D-PHY interface specification, revision.. One is for DSI (D-PHY TX0), one is for CSI (D-PHY RX0) and the third one can be configure d to DSI or CSI (D-PHY TXRX). The D-PHYs are intended for the digital data transmission between a host processor and display drivers or camera interfaces in mobile applications, supporting a maximum effective bit rate of. Gbps per lane. Please refer to the RK Technical Reference Manual for more information. On the phycore_rk only D-PHY RX0 and D-PHY TXRX are available at phycore Connector X with four data lanes and one clock lane each (Table ). Signal Pin # ST SL Description X_MIPI_TXRX_CLKN XC MIPI_I/O RK internal MIPI D-PHY TXRX clock- X_MIPI_TXRX_CLKP XC MIPI_I/O RK internal MIPI D-PHY TXRX clock+ X_MIPI_TXRX_D0N XD MIPI_I/O RK internal MIPI D-PHY TXRX data 0- X_MIPI_TXRX_D0P XD0 MIPI_I/O RK internal MIPI D-PHY TXRX data 0+ X_MIPI_TXRX_DN XC MIPI_I/O RK internal MIPI D-PHY TXRX data - X_MIPI_TXRX_DP XC MIPI_I/O RK internal MIPI D-PHY TXRX data + X_MIPI_TXRX_DN XD MIPI_I/O RK internal MIPI D-PHY TXRX data - X_MIPI_TXRX_DP XD MIPI_I/O RK internal MIPI D-PHY TXRX data + X_MIPI_TXRX_DN XD MIPI_I/O RK internal MIPI D-PHY TXRX data - X_MIPI_TXRX_DP XD MIPI_I/O RK internal MIPI D-PHY TXRX data + X_MIPI_RX_CLKN XC CSI-_I RK internal MIPI D-PHY RX0 receive clock- X_MIPI_RX_CLKP XC CSI-_I RK internal MIPI D-PHY RX0 receive clock+ X_MIPI_RX_D0N XD CSI-_I RK internal MIPI D-PHY RX0 receive data 0- X_MIPI_RX_D0P XD CSI-_I RK internal MIPI D-PHY RX0 receive data 0+ X_MIPI_RX_DN XC CSI-_I RK internal MIPI D-PHY RX0 receive data - X_MIPI_RX_DP XC CSI-_I RK internal MIPI D-PHY RX0 receive data + X_MIPI_RX_DN XC CSI-_I RK internal MIPI D-PHY RX0 receive data - X_MIPI_RX_DP XC CSI-_I RK internal MIPI D-PHY RX0 receive data + X_MIPI_RX_DN XD CSI-_I RK internal MIPI D-PHY RX0 receive data - X_MIPI_RX_DP XD CSI-_I RK internal MIPI D-PHY RX0 receive data + Table : MIPI DSI/CSI Signal Location Please refer to section. for additional information about using the MIPI interface as camera interface. PHYTEC Messtechnik GmbH 0 L-e_

75 Camera Interface Camera Interfaces The phycore-rk SOM offers one parallel camera port (CIF PP) and two MIPI CSI- interfaces to connect digital cameras. All signals (including control signals and an I C interface) to use the camera interfaces according to Phytec's phycam-s+ (requires an external deserializer), or phycam-p standard are available at the phycore-connector. The RK's -bit wide parallel camera port and the MIPI CSI- interfaces are connected to the Image Signal Processing (ISP) unit and the Video Input Processor (VIP) to process the camera signals (Figure 0). Figure 0: Camera Connectivity of the RK On the phycore-rk SOM camera port CIF PP is brought out as parallel interfaces with data bits, HREF (horitontal sync), VSYNC (vertical sync), CLKOUT and CLKIN (pixel clock). The MIPI CSI- interfaces connect to the phycore-connector with five data lanes and one clock lane (Figure ). The camera interfaces of the phycore-rk include all signals and are prepared to be used as phycam-s(+), phycam-p, or MIPI CSI- interface on an appropriate carrier board. Please refer to section..0 for more information on how to use the camera interfaces on a carrier board with different interface options. PHYTEC Messtechnik GmbH 0 L-e_

76 phycore -RK [PCM-0] Figure : Camera Interfaces at the phycore-connector Parallel bit and MIPI CSI-. Parallel Camera Interface (CIF PP) The parallel camera interface (CIF PP) is available at the phycore-connector with data bits, HSYNC, VSYNC and PIXCLK as shown in the following table. Signal Pin # ST SL Description X_CIF_D0 XB0 I. V Camera interface input pixel data 0 X_CIF_D XA I. V Camera interface input pixel data X_CIF_D XB I. V Camera interface input pixel data X_CIF_D XA I. V Camera interface input pixel data X_CIF_D XB I. V Camera interface input pixel data X_CIF_D XA I. V Camera interface input pixel data X_CIF_D XA I. V Camera interface input pixel data X_CIF_D XB I. V Camera interface input pixel data X_CIF_D XB I. V Camera interface input pixel data X_CIF_D XA I. V Camera interface input pixel data X_CIF_D0 XB I. V Camera interface input pixel data 0 X_CIF_D XA I. V Camera interface input pixel data X_CIF_CLKIN XA I. V Camera interface input pixel clock X_CIF_VSYNC XA I. V Camera interface vertical synchronization X_CIF_HREF XB I. V Camera interface horizontal synchronization X_CIF_CLOCKOUT XB O. V Camera interface output work clock Table : Parallel Camera Interface (CIF PP) Signal Location PHYTEC Messtechnik GmbH 0 L-e_

77 Camera Interface Signal Pin # ST SL Description X_IC_SCL XA OD_BI. V IC_SENSOR clock X_IC_SDA XB OD_BI. V IC_SENSOR data X_PMUGPIO0_A/MAC_RXD0 XB O. V phycam-s+ data enable X_PMUGPIO0_A/MAC_RXD XB I. V phycam-s+ power down, Figure : Signals optionally usable with the Camera Interface Using the phycore's parallel camera interface CIF PP, together with an I²C bus facilitates easy implementation of a CMOS camera interface, e.g. a phycam-p or a phycam-s+ interface on a custom carrier board (section..0).. MIPI CSI- Camera Interfaces The RK includes three D-PHYs which are compliant with the MIPI D-PHY interface specification, revision.. One is for DSI (D-PHY TX0), one is for CSI (D-PHY RX0) and the third one can be configure d to DSI or CSI (D-PHY TXRX). On the phycore_rk only D-PHY RX0 and D-PHY TXRX are available at phycore Connector X with four data lanes and one clock lane each (Table ). Both can be used to connect camera modules to the phycore-rk. Please refer to section for additional information about the location of the MIPI signals on the phycore Connector. Use of an I²C bus, a camera clock signal and three GPIOs as control signals allows connecting a MIPI CSI- camera module directly. Note: It is not possible to use the MIPI CSI- interface and the CIF PP interface together at the Image Signal Processing (ISP) unit or the Video Input Processor (VIP) simultaneously. Connecting two camera modules is only possible if one connects to the ISP unit and the second one to the VIP. More information on the Phytec camera interface standards phycam-p and phycam-s+ and how to implement them on a custom carrier board can be found in the corresponding manual L-. The schematic of the phyboard-rk carrier board, which shows the parallel camera interface brought out as phycam-s+ interface (LVDS), can also serve as reference design. : Or any other GPIO available - recommended to implement special control features for the camera interface circuitry on the carrier board (e.g. enabling/disabling of the interface, switching between phycam-p and phycam-s, etc.). Please refer to L- or appropriate Phytec CB designs as reference. PHYTEC Messtechnik GmbH 0 L-e_

78 phycore -RK [PCM-0] Technical Specifications The physical dimensions of the phycore-rk are represented in Figure. The module s profile is max.. mm thick, with a maximum component height of. mm on the bottom (connector) side of the PCB and approximately. mm on the top (microcontroller) side. The board itself is approximately. mm thick. D. mm phycore-rk mm mm. mm. mm. mm mm Figure : Physical Dimensions (top view) 0 PHYTEC Messtechnik GmbH 0 L-e_

79 Technical Specifications Note: To facilitate the integration of the phycore-rk into your design, the footprint of the phycore-rk is available for download (section 0.). Additional specifications: Dimensions: mm x mm Weight: approx.. g Storage temperature: -0 C to + C Operating temperature: refer to section. Humidity: % r.f. not condensed Operating voltage: VDD_IN_OTG_OUT: V +/- % Linux idle, no Ethernet connected: typical. W Linux idle, Ethernet connected, no traffic: typical. W Power consumption: cores full load, Ethernet connected, no traffic: typical. W Conditions: GB DDR, GB emmc, MB SPI NOR Flash, KB EEPROM, G-bit Ethernet PHY, PCMIC on board, 0 C, V Table : Technical Specifications The above-mentioned specifications describe the standard configuration of the phycore-rk as of the printing of this manual. : depending on the configuration of the module PHYTEC Messtechnik GmbH 0 L-e_

80 phycore -RK [PCM-0]. Product Temperature Grades Caution! The right temperature grade of the Module depends very much on the use case. It is mandatory to determine if the use case suites the temperature range of the chosen module (see below). If necessary a heat spreader can be used for temperature compensation The feasible operating temperature of the SOM highly depends on the use case of your software application. Modern high performance microcontrollers and other active parts as the ones described within this manual are usually rated by qualifications based on tolerable junction or case temperatures. Therefore, making a general statement about maximum or minimum ambient temperature ratings for the described SOM is not possible. However, the above mentioned parts are available still in different temperature qualification levels by the producers. We offer our SOMs in different configurations making use of those temperature qualifications. To indicate which level of temperature qualification is used for active and passive parts of a SOM configuration we have categorized our SOMs in three temperature grades. The table below describes these grades in detail. These grades describe a set of components which in combination add up to a useful set of product options with different temperature grades. This enables Phytec to make use of cost optimizations depending on the required temperature range. In order to determine the right temperature grade and whether the maximum or minimum qualification levels are met within an application the following conditions must be defined by considering the use case: Determined processing load for the given software use case Maximum temperature ranges of components (see table below) Power consumption resulting from a base load and the calculating power required (in consideration of peak loads as well as time periods for system cool-down) Surrounding temperatures and existing airflow in case the system is mounted into a housing Heat resistance of the heat dissipation paths within the system along with the considered usage of a heat spreader or a heat sink to optimize heat dissipation Product Temp. Grade I X Controller Temp Range (Junction Temp) Industrial -0 C to +0 C / Automotive -0 C to+ C Extended Commercial -0 C to +0 C C Commercial 0 C to + C RAM (Case Temp) Industrial -0 C to + C Industrial -0 C to + C Consumer 0 C to + C Others (Ambient) Industrial -0 C to + C Industrial -0 C to + C Consumer 0 C to +0 C Table : Product Temperature Grades PHYTEC Messtechnik GmbH 0 L-e_

81 Technical Specifications. Connectors on the phycore-rk Manufacturer Number of pins per connector Samtec part number (lead free) Height Samtec phycore-connector X: 0 pins ( rows of 0 pins each) REF--0 mm Information on the receptacle sockets that correspond to the connectors populating the underside of the phycore RK is provided below. The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board. In order to get the exact spacing, the maximum component height ( mm) on the bottom side of the phycore must be subtracted. Mating Connector Connector height mm Manufacturer Number of pins per connector Samtec part number (lead free) Phytec part number (lead free) Height Samtec 0 pins ( rows of 0 pins each) REF--0 VM0 mm Please refer to the corresponding datasheets and mechanical specifications provided within the category Module Connector in the download section of the phycore-rk web page. PHYTEC Messtechnik GmbH 0 L-e_

82 phycore -RK [PCM-0] 0 Hints for Integrating and Handling the phycore-rk 0. Integrating the phycore-rk Design Rules Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phycore module. For maximum EMI performance we recommend as a general design rule to connect all GND pins to a solid ground plane. But at least all GND pins neighboring signals which are being used in the application circuitry should be connected to GND. Additional Information and Reference Design Besides this hardware manual much information is available to facilitate the integration of the phycore-rk into customer applications.. the design of the phycore-rk Carrier Board (PCM-) can be used as a reference for any customer application. many answers to common questions can be found at or the link RK Carrier Board within the category Dimensioned Drawing in the download section of the phycore-rk web page leads to the layout data as shown in Figure. It is available in different file formats. Use of this data allows integrating the phycore-rk SOM as a single component into your design.. different support packages are available to support you in all stages of your embedded development. Please visit or or contact our sales team for more details. PHYTEC Messtechnik GmbH 0 L-e_

83 Handling the phycore-rk. mm. mm.0 mm. mm. mm. mm. mm. mm. mm mm. mm. mm 0. mm mm DDDDDDDDDD0DDDDDDDDDD0DDDDDDDDDD0DDDDDDDDDD0DDDDDDDDDD0DDDDDDDDDD0 mm 0.0 mm. mm. mm.0 mm mm mm CCCCCCCCCC0CCCCCCCCCC0CCCCCCCCCC0CCCCCCCCCC0CCCCCCCCCC0CCCCCCCCCC0 0. mm D. mm PAD mm D.mm D. mm BBBBBBBBBB0BBBBBBBBBB0BBBBBBBBBB0BBBBBBBBBB0BBBBBBBBBB0BBBBBBBBBB0 mm. mm mm Ref Des AAAAAAAAAA0AAAAAAAAAA0AAAAAAAAAA0AAAAAAAAAA0AAAAAAAAAA0AAAAAAAAAA0. mm. mm.mm 0. mm. mm. mm mm. mm A tolerance of +/- 0. mm applies to all indicated measures, except for the measures of the outer edges which have a tolerance of +/- 0. mm Figure : Footprint of the phycore-rk PHYTEC Messtechnik GmbH 0 L-e_

84 phycore -RK [PCM-0] 0. Handling the phycore-rk Modifications on the phycore Module Removal of various components, such as the microcontroller and the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board as well as surrounding components and sockets remain undamaged while de-soldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. To remove the component, carefully heat up both terminals with the solder-iron tip and pick up the part from the board. Alternatively, a hot air gun can be used to heat and loosen the bonds. Caution! If any modifications to the module are performed, regardless of their nature, the manufacturer warranty is voided. PHYTEC Messtechnik GmbH 0 L-e_

85 The phycore -RK on the phycore Carrier Board The phycore-rk on the phycore Carrier Board This chapter provides detailed information on the phycore-rk Carrier Board and its usage with the phycore-rk SOM. The information and all board images in the following sections are applicable to the. PCB revision of the phycore-rk Carrier Board.. Concept of the phycore Carrier Board Phytec phycore Carrier Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start-up and subsequent communication to and programming of applicable Phytec System on Module (SOM) modules. phycore Carrier Boards are designed for evaluation, testing and prototyping of Phytec System on Module in laboratory environments prior to their use in customer designed applications. The phycore Carrier Board provides a flexible development platform enabling quick and easy start-up and subsequent programming of the phycore System on Module. The carrier board design allows easy connection of additional extension boards featuring various functions that support fast, convenient prototyping and software evaluation. This modular development platform concept includes the following components: the phycore-rk Module populated with the RK microcontroller and all applicable SOM circuitry such as DDR SDRAM, Flash, PHY, and PMIC to name a few. the phycore Carrier Board, which offers all essential components and connectors for start-up including: a power socket which enables connection to an external power adapter, interface connectors such as DB-, USB and Ethernet allowing for use of the SOM s interfaces with a standard cable. The carrier board can also serve as a reference design for development of custom target hardware in which the phycore SOM is deployed. Carrier board schematics are available under a Non Disclosure Agreement (NDA). Re-use of carrier board circuitry likewise enables users of Phytec SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. PHYTEC Messtechnik GmbH 0 L-e_

86 phycore -RK [PCM-0]. Features The phycore Carrier Board has the following features for supporting the phycore-rk modules: Power supply circuits to supply the phycore-rk and the peripheral devices of the carrier board V power supply through wall adapter jack, -pole MINI COMBICON base strip, or Micro-USB connector. V lithium-ion battery as alternative power supply Monitoring of the lithium-ion battery charging/discharging current Various LEDs to indicate the status of the different supply voltages Support of different power modes of the appropriate phycore Supervision of the six main supply voltage domains DIP switches to configure the boot options for the phycore-rk module mounted Support of all interfaces available at the phycore-connector Full featured four line RS- transceiver supporting data rates of up to Mbps, hardware handshake and RS- connector Second two line RS- transceiver supporting data rates of up to Mbps and RS- connector One USB OTG interface brought out to a USB Micro-AB connector Two USB host interfaces (one USB.0/USB. compliant, one only USB.0 compliant) USB HSIC hub controller providing two USB.0 downstream ports Gbit Ethernet interface Support of four I C buses from the SOM, available at different connectors on the carrier board Connectivity to two SPI interfaces from the SOM Complete audio interface available at four. mm audio jacks HDMI interface PHYTEC Display Interface (PDI) (LVDS display with separate connectors for data lines and display/backlight supply voltage) including a circuitry to allow dimming of a backlight Data Display Group (DDG) LVDS display interface including a touch screen interface for use of wire resistive touch panels and several supply voltages Audio/Video (A/V) connector for use with phyboard Expansion Boards, and to add specific audio/video connectivity with custom expansion boards Serial LVDS camera interface compatible to Phytec phycam-s+ camera standard with I C bus for camera control MIPI interface connectors supporting two MIPI interfaces with four data lanes each (one as camera interface and one as camera, or display interface) One Secure Digital Card / Multi Media Card Interface (SD/MMC) Phytec Wi-Fi/Bluetooth connector : Please get additional information on phyboard Expansion Boards from our sales team. PHYTEC Messtechnik GmbH 0 L-e_

87 The phycore -RK on the phycore Carrier Board RTC with battery supply/backup Two user-programmable LEDS (one RGB multicolor LED and one red LED) Two user-programmable buttons plus reset button, PMIC sleep button and PMIC wakeup button kb I C EEPROM NTC temperature measurement Expansion connector with signals not used for features and interfaces on the carrier board, and all carrier board supply voltages JTAG interface for programming and debugging The following sections contain specific information relevant to the operation of the phycore-rk mounted on the phycore Carrier Board. PHYTEC Messtechnik GmbH 0 L-e_

88 phycore -RK [PCM-0]. Overview of the phycore Carrier Board Peripherals The phycore Carrier Board is depicted in Figure. It is equipped with the components and peripherals listed in Table, Table 0, Table and Table. For a more detailed description of each peripheral refer to the appropriate chapter listed in the applicable table. The following figures highlight the location of each peripheral for easy identification. D JP 0 JP JP 0 X X 0 J0 X JP JP JP JP JP JP JP0JP 0 0 X0 J X X S B JP J J J 0 X B0 B B B B B0 B B B B B0 B B B B B0 B B B B B B B B B B B B B B B B B B B B B B B B X A A A A A A A A A A A0 A J X B X X JP D0 JP X 0 D BAT D D J J 0 X J 0 D S S S S S D0 S D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D0 D D D D D0 D D D D D0 D D D D D0 D D D D D0 B B B0 B B B B X D D0 D D D X C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C0 C C C C C0 C C C C C0 C C C C C0 C C C C C0 C C C C C0 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B0 B B B B B0 B B B0 B B B B B0 B B B B B0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A0 A A A A A0 A A A A A0 A A A A A0 A A A A A0 A A A A A J J X J0 J D D D D J 0 0 X 0 0 X X X X X X D J X0 + TS - D X + - X X X X X0 0 X X J D D Figure : phycore Carrier Board Overview of Connectors,Buttons and Switches 0 PHYTEC Messtechnik GmbH 0 L-e_

89 The phycore -RK on the phycore Carrier Board.. Connectors and Pin Header Table lists all available connectors on the phycore Carrier Board. Figure highlights the location of each connector for easy identification. Reference Designator Description Section X Gbit Ethernet connector (RJ with speed and link LED).. X X Serial interface UART without handshake signals (DB-F) Serial interface UART0 with handshake signals (DB-M).. X Expansion connector (x0 socket connector; mm pitch).. X X X X X X X X X X X Table : Audio/Video (A/V) connector # providing resistive touch interface; I S and I C interface signals (x dual entry socket connector; mm pitch) Audio/Video (A/V) connector # providing parallel LCD interface signals (x0 dual entry socket connector; mm pitch) USB OTG connector (USB Micro-AB, can also be used as V power input) Secure Digital Memory/MultiMedia Card slot SDMMC0 (microsd slot Yamaichi) Stereo line in connector (MP/FM,. mm stereo jack) Microphone in connector (. mm stereo jack) Stereo line out connector (Speaker / docking station / FMTX,. mm stereo jack) Headset out connector (. mm stereo jack) USB HSIC hub downstream USBDN and USBDN connector (USB.0, type A, dual port, angled standing) USB host and USB host connector (USB.0, type A, dual port, angled standing) Data Display Group display interface connector for LVDS data (Hirose -pin DF series wire-to-board connector;. mm pitch) phycore Carrier Board Connectors and Pin Headers....., PHYTEC Messtechnik GmbH 0 L-e_

90 phycore -RK [PCM-0] Reference Designator Description Section X Data Display Group display interface connector for display/ backlight supply and control (Hirose 0-pin DF series wireto-board... connector;. mm pitch) X0 Data Display Group display interface connector for resistive touch (Hirose x0-pin header connector;. mm pitch)... X Data Display Group display interface connector for optional supply voltages (Hirose -pin DF series wire-to-board... connector;. mm pitch) X Data Display Group display interface connector for additional LVDS data lanes (Hirose -pin DF series wire-to-board... connector;. mm pitch) X Wi-Fi/Bluetooth connector (x-pin header connector;. mm pitch).. X0 Lithium-ion battery connector (. V to. V, max. A) (-pole TE Connectivity MTA-00 Friction Lock Header) X Wall adapter input power jack to supply main board power ( V, max. A)... X Alternative power connector ( V, max. A) (-pole MINI COMBICON base strip;. mm pitch) X Ground terminal (solder lug, mm) for measuring purposes - X HDMI connector.. X Camera0, phycam-s+ Connector (Hirose -pin DF series wire-to-board connector;. mm pitch)..0. X MIPI connector (Molex 0-pin SlimStack board-to-board connector; 0. mm pitch).. X0 JTAG (x0-pin header connector;. mm pitch).. X phycore-connector, ( x Samtec x 0 pins; 0. mm pitch).. X PHYTEC Display Interface (PDI) data connector (Molex 0-pin FFC/FPC; 0. mm pitch) Phytec Display Interface (PDI) power connector... (-position TE Connectivity Micro-MaTch SMD FTE) BAT Holder for coin cell CR0 to buffer RTC at U.. Table : phycore Carrier Board Connectors and Pin Headers (continued) PHYTEC Messtechnik GmbH 0 L-e_

91 The phycore -RK on the phycore Carrier Board Note: Ensure that all module connections do not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller User's Manual/Data Sheets. As damage from improper connections varies according to use and application, it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals... Switches The phycore Carrier Board is populated with several switches which are essential for the operation of the phycore-rk module on the carrier board. Figure shows the location of the switches and push buttons. Button Description Section S User button - Toggles RK's GPIO_A signal S User button - Toggles RK's GPIO_A0 signal.. S Button to toggle the PWRON signal of the PMIC on the SOM.. S PMIC sleep button phycore SOM PMIC control.. S System Reset button system reset signal generation.. S DIP switch phycore SOM emmc boot enable/disable S DIP switch phycore SOM SPI NOR Flash boot enable/disable..0 Table 0: phycore Carrier Board Push Buttons Descriptions S, S User buttons connecting to GPIO_A (S) and GPIO_A0 (S) of the RK. S Can be used to switch to phycore-rk into different power states. It toggles signal X_PMIC_nPWRON (XB) at the PMIC on the SOM. S S S S Issues a system sleep event. Currently not supported by software. Issues a system reset signal. Pressing this button will toggle the X_nRESET pin (XC) of the phycore module LOW, causing the controller to reset. DIP-switch S enables/disables booting the phycore-rk from emmc. DIP-switch S enables/disables booting the phycore-rk from SPI NOR Flash. : All special functions of the PMIC on the SOM such as RTC interrupts, use of power groups, etc. require the PMIC to be programmed via I C interface. At the time of delivery only the generation of the required voltages is implemented. Please refer to the Power Management IC's datasheet for more information on how to program the PMIC. PHYTEC Messtechnik GmbH 0 L-e_

92 phycore -RK [PCM-0].. LEDs The phycore Carrier Board is populated with numerous LEDs which are used to indicate the status of the USB interfaces, as well as the different supply voltages, and as userprogrammable LED.Figure shows the location of the LEDs. Their function is listed in the table below: LED Color Description Section D green Indicates presence of external V input voltage VCC_EXT_V from X or X D green Indicates presence of lithium-ion battery input voltage VCC_LiIon_BATT+ at X0 D0 green PMIC system voltage VDD_SYS generated on the phycore-rk D green Indicates buffering of the Real-Time Clock at U by the coin cell installed at BAT Indicates presence of. V supply voltage VCCV from voltage D green regulator U for various peripherals on the phycore Carrier Board Indicates presence of. V supply voltage VCCV from voltage D green regulator U for various peripherals on the phycore Carrier Board Indicates presence of. V supply voltage VCCV from voltage D green regulator U for various peripherals on the phycore Carrier Board Indicates presence of V supply voltage VCCV from voltage D green regulator U for various peripherals on the phycore Carrier Board D RGB User programmable RGB-LED (ports LED0, LED and LED of - bit I C LED dimmer at U) D red User LED connected to port LED of -bit I C LED dimmer at U D0 D D D D Table : yellow Indicates presence of the USBOTG VBUS voltage yellow Indicates presence of the USB host VBUS voltage yellow Indicates presence of the USB host VBUS voltage Indicates presence of the VBUS voltage of USB hub downstream yellow port USB_DN Indicates presence of the VBUS voltage of USB hub downstream yellow port USB_DN phycore Carrier Board LEDs Descriptions , PHYTEC Messtechnik GmbH 0 L-e_

93 B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B The phycore -RK on the phycore Carrier Board JP D 0 JP JP 0 X X 0 0 J0 0 JP JP JP JP JP JP JP0JP X0 X J X X S JP J B J J X 0 X A A A A A A X A A A A A0 A J B X 0 X 0 JP D0 JP 0 X D BAT D D J J D S J S X S S S S D0 D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D X D D D D D0 D D D D D0 D D D D D0 D D D D D0 D D D D D0 D D D D D0 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C0 C C C C C0 C C C C C0 C C C C C0 C C C C C0 C C C C C0 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B0 B B B B B0 B B B B B0 B B B B B0 B B B B B0 B B B B B0 X A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A0 A A A A A0 A A A A A0 A A A A A0 A A A A A0 A A A A A0 X 0 0 J 0 J J0 J D D D D 0 J X X X X X X D J D X0 X X 0 X 0 X X X0 0 X X D J D Figure : phycore Carrier Board Overview of the LEDs PHYTEC Messtechnik GmbH 0 L-e_

94 phycore -RK [PCM-0].. Jumpers The phycore Carrier Board comes pre-configured with removable jumpers (JP) and solder jumpers (J). The jumpers allow the user the flexibility of configuring a limited number of features for development purposes. Table below lists the jumpers, their default positions, and their functions in each position. Figure depicts the jumper pad numbering scheme for reference when altering jumper settings on the development board. Figure provides a detailed view of the phycore Carrier Board jumpers and their default settings. In these diagrams a beveled edge indicates the location of pin. Before making connections to peripheral connectors it is advisable to consult the applicable section in this manual for setting the associated jumpers. removable jumper solder jumper e.g.: JP e.g.: JP Figure : Typical Jumper Numbering Scheme e.g.: JP e.g.: J Table provides a comprehensive list of all carrier board jumpers. The table only provides a concise summary of jumper descriptions. For a detailed description of each jumper, see the applicable chapter listed in the right hand column of the table. If manual modification of the solder jumpers is required, please ensure that the board, as well as surrounding components and sockets, remain undamaged while de-soldering. Overheating the board can cause the solder pads to loosen, rendering the board inoperable. Carefully heat neighboring connections in pairs. After a few alternations, components can be removed with the solder-iron tip. Alternatively, a hot air gun can be used to heat and loosen the bonds. PHYTEC Messtechnik GmbH 0 L-e_

95 B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B The phycore -RK on the phycore Carrier Board 0 X 0 X JP JP X JP JP B X B X 0 0 D D BAT D D X 0 JP JP JP J D J 0 J0 S JP JP 0 X0 J S X 0 0 J S S JP X S B A B A D0 B A B A B A B A JP B A S B A A0 A S A D C A A A0 A A A A A0 A X 0 A A A A0 A A A A A A A A A A A A A0 A B B B B B B B B B B B B B B B B B B B B B B B B B B B0 B B B B B0 B B B B B0 B B B B B0 B B B B B0 B B B B B0 X A A A A A A A A A A A A A A A A A A A A A A A A A A J JP C D C C D C C J J J D C C D C C0 D C C D C C D C C D C C D C C0 D C C D C C D C C D C C D C C0 D D D D D D0 D D D D D0 D D D D D0 D D D D D0 D D D D D0 D D D D D0 C C A D C C A D X C C A0 X D C J C A D C C0 A D C C A D C C A D C X C A0 D C C D C C0 D C C D C C D C C D C C D C C0 X J J J0 J JP D D D D D0 0 0 J 0 JP 0 0 X X X X X X X PCB Edge D J X0 D X X 0 X D D D D D D 0 X 0 X0 0 0 X 0 X X J D D M Figure : phycore Carrier Board Jumper Locations PHYTEC Messtechnik GmbH 0 L-e_

96 phycore -RK [PCM-0] The following conventions are used in the Jumper column of jumper Table J = solder jumper JP = removable jumper Jumper/ Setting JP Description JP connects the write control input of the EEPROMat U with GND. If this jumper is not populated, the EEPROM is write protected. closed EEPROM is not write protected Section... open EEPROM is write protected JP Jumper JP forces the USB OTG interface of the phycore-rk to function either as host (master), or device (slave) open USBOTG_ID floating, phycore-rk in slave mode, or according to the mode configured by software closed USBOTG_ ID connected to GND, phycore-rk in host mode JP, JP, JP, JP0, JP JP, JP + Jumpers JP JP connect either VDD_LVD_DDG (configured with JP) or GND to pin (JP), pin (JP), pin (JP), pin (JP0) and pin (JP) of the Data Display Group optional connector X. Ensure to select the voltage level at each pin according to the connected display. VDD_LVD_DDG (configured with JP) connected to the corresponding pin of X + GND connected to the corresponding pin of X Jumpers JP and JP connect either VCCV or GND to pin (JP) and pin (JP) of the Data Display Group extra LVDS connector X. Ensure to select the voltage level for at each pin individually according to the connected display. + V CCV connected to the corresponding pin of X + GND connected to the corresponding pin of X Table : phycore Carrier Board Jumper Descriptions : Default settings are in bold blue text PHYTEC Messtechnik GmbH 0 L-e_

97 The phycore -RK on the phycore Carrier Board Jumper/ Description Setting JP Jumper JP allows selecting the voltage source for the supply voltage (VDD_LVD_DDG) at pins and of Data Display Group LVDS interface connector X. Ensure to select the voltage level according to the connected display. + VDD_IN_OTG_OUT ( V) connected to pins and of X + VCCV (. V) connected to pins and of X + VCCV ( V) connected to pins and of X JP, JP Jumpers JP and JP select the voltage source for the supply voltage at pins,, (JP) and pins and (JP) of Data Display Group display backlight connector X. Ensure to select the voltage level according to the connected display. JP + VDD_IN_OTG_OUT ( V) connected to pins and of X + VCCV (. V) connected to pins and of X + VCCV ( V) connected to pins and of X JP + VDD_IN_OTG_OUT ( V) connected to pins and of X + VCCV (. V) connected to pins and of X + VCCV ( V) connected to pins and of X JP Jumper JP selects the voltage level at pin of Data Display Group extra LVDS connector X. Ensure to select the voltage level according to the connected display. + VDD_IN_OTG_OUT ( V) connected to pin of X + VCCV (. V) connected to pin of X + GND connected to pin of X JP JP connects the coin cell installed at BAT to the Real-Time Clock at U. Closing JP allows buffering the Real-Time Clock. Opening JP stops buffering the Real-Time Clock by the coin cell, thus allowing the coin cell to be left in its holder when the board is not in use. closed Coin cell buffers the RTC, LED D ON open Coin cell disconnected from RTC, LED D OFF Section Table : phycore Carrier Board Jumper Descriptions 0 (continued) PHYTEC Messtechnik GmbH 0 L-e_

98 phycore -RK [PCM-0] Jumper/ Description Setting J Jumper J connects pins 0 to of HDMI connector X either directly to the common ground plane, or to the shield contact which connects to the ground plane via a resistor and a capacitor and which is also used at other shielded connectors. It should be adapted according to the HDMI device attached to the carrier board to reduce electrical noise from other electrical sources. + All four shield pins are connected to GND + All four shield pins connect to the carrier boards' shield contact J J selects rising, or falling edge strobe for the LVDS Deserializer at U used for the camera connectivity of the phycore-rk (CIF PP) + rising edge strobe used for the LVDS camera signals + falling edge strobe used for the LVDS camera signals J Jumper J allows selecting X_nRESET or GPIO PMUGPIO0_B as reset signal used at DDG resistive touch connector X0 (pin ) and Phytec A/V connector X (pin ) System reset signal X_nRESET used as display reset signal + X_DISPLAY_RESET at X0- and X- GPIO X_PMUGPIO0_B used as display reset signal + X_DISPLAY_RESET at X0- and X- J0 Jumper J0 configures the I²C address of the touch screen controller at U + Touch controller (U) address: 0x + Touch controller (U) address: 0x J, J, J J: + J: + J: + other settings J, J and J define the slave addresses (E0, E and E) of the serial memory at U on the IC_CAM bus. In the highnibble of the address I C memory devices have the slave ID 0x. The low-nibble is build from E, E, E0 and the R/W bit. E0 =, E = 0, E= 0, => 0x / 0x (W/R) are selected as the low-nibble of the EEPROM's address I C address 0x (memory array), 0x (ID page) please refer to Table to find alternative addresses resulting from other combinations of jumpers J, J and J Section and Table : phycore Carrier Board Jumper Descriptions 0 (continued) 0 PHYTEC Messtechnik GmbH 0 L-e_

99 The phycore -RK on the phycore Carrier Board Jumper/ Setting J, J, J, J, J0, J, J, J Description Select device power supply input either from VDD_IN_OTG_OUT or from VDD_SYS. The corresponding devices are: J Voltage regulator U VCC (pin and 0) J Voltage regulator U VCC (pin and 0) J Voltage regulator U VCC (pin and 0) J USB hub port current regulator U0 IN (pin) J0 USB host port current regulator U IN (pin) J USB OTG and host port current regulator U IN (pin) J Phytec Display Interface connector X (pin A, A, A) J Voltage regulator U VCC (pin and 0) + The corresponding device is supplied by VDD_SYS + The corresponding device is supplied by VDD_IN_OTG_OUT J Jumper J selects either VCCV ( output of voltage regulator U on the carrier board) or VDD_SD (output of PMIC on module) as supply voltage for the micro SD/MMC card + Micro SD/MMC card is powered by VDD_SD + Micro SD/MMC card is powered by VCCV J Jumper J allows selecting either VDD_IN_OTG_OUT or VDD_HDMIV as supply voltage for the HDMI ESD protection device at U, and as pull-up voltage for HDMI_SCL and HDMI_SDA. VDD_HDMIV is the PMIC's V supply output (0 ma) for HDMI. It can be enabled/disabled by software. + VDD_IN_OTG_OUT used as supply and pull-up voltage + VDD_HDMIV used as supply and pull-up voltage Table : phycore Carrier Board Jumper Descriptions 0 (continued) Section.... Note: Detailed descriptions of the assembled connectors, jumpers and switches can be found in the following chapters. PHYTEC Messtechnik GmbH 0 L-e_

100 D D D 0 0 D D D B A B B A A A B B D C B A C A A D B C0 B D C B A C D C D B D0 C0 B A B C B C A0 B0 D A D C B A A A D C A C B A0 C A C B C C C D C D D phycore -RK [PCM-0]. Functional Components on the phycore Carrier Board This section describes the functional components of the phycore-rk Carrier Board supporting the phycore-rk module. Each subsection details a particular connector/interface and associated jumpers for configuring that interface... phycore-rk SOM Connectivity (X) M X0 X X X X 0 0 D D X X J 0 D D X0 0 J X X 0 0 X J D X A A0 X A A A A A A A A0 A A A A0 A A0 A A A A A A A A A A0 A A A A A A A A A A A A A A A A A A A D D J X X D 0 0 B B B B B B B0 B B B B B0 B B B B B0 B B B B B B B0 B B B B B B B0 B B B B B B B B B B B B B B0 B B0 X J 0 D J S J0 D D 0 C C0 C C C C0 C C C C0 C C C0 C C C0 C C X 0 C C C C C C C C C C C C C C C C C C C C C C C C C C X 0 D D D D D D D D D D D D D D D D D D D D D D D D D D D0 D D D D D D D0 D D D D D0 D D D D D0 D D D D D0 D0 D D0 J X BAT S S S S S J J J J J0 D J S PCB Edge JP 0 X X JP JP JP J X X X X J JP JP0JP A A A A A0 A JP JP X JP D0 A A A A A A JP JP JP JP B0 BB B B B BB BB BB B B B B BB B B0 B B B B B B B B B0 B B B B B B B B B B B X X X X X Figure : phycore- RK SOM Connectivity to the Carrier Board Connector X on the carrier board provides the phycore System on Module connectivity. The connector is keyed for proper insertion of the SOM. Figure above shows the location of connector X, along with the pin numbering as described in section. The beveled edge of the module shape indicates the location of pin A. Please refer to section. for information on manufacturer, part number and ordering. PHYTEC Messtechnik GmbH 0 L-e_

101 The phycore -RK on the phycore Carrier Board Caution! Samtec connectors guarantee optimal connection and proper insertion of the phycore-rk. Please make sure that the phycore-rk is fully plugged into the matting connectors of the carrier board. Otherwise individual signals may have a bad, or no contact. To support all features of the phycore-rk Carrier Board the BSP provided assigns functions different from what is described in Table to Table to some pins of the phycore-rk. Table lists all pins with functions different from what is described in section. Use of these pins in their original function described in section of this manual requires changing the BSP. Note: The information given in the TYPE column is from the SOM's perspective. Pin# Signal Type SL GPIO Designated Function XA X_PMUGPIO0_B O. V PMUGPIO0_B XA X_CIF_D O. V GPIO_B XA X_CIF_D O. V GPIO_A HUB_CONNECT input of USB hub U (controls hub communication stage transition) USB host VBUS enable (active low) ADC multiplexer U Select (S) input XA X_SPI_CSN I. V GPIO_A User button (S) XA X_IS_SDO O. V GPIO_A XA X_IS_SDO O. V GPIO_A EEPROM enable (PHYWIRE) at PDI data connector X-B Display enable at X-, X-, X- and X-B, XA X_IS_SDO O. V GPIO_A MIPI Power on signal at X- XA X_GPIO_B O. V GPIO_B MIPI CSI/DSI enable at X- XA X_GPIO_B0 I. V GPIO_B0 PMIC sleep control button (S) XA XA X_GPIO_A0 /MAC_CRS X_PMUGPIO0_B0/ MAC_RXCLK I. V GPIO_A0 User button (S) I. V PMUGPIO0_B0 USB OTG over-current detection (active low) XB0 X_CIF_D0 O. V GPIO_B USB OTG VBUS enable (active low) XB X_CIF_D O. V GPIO_A0 Table : Specifically used Pins on the phycore-connector USB host VBUS enable (active low) PHYTEC Messtechnik GmbH 0 L-e_

102 phycore -RK [PCM-0] Pin# Signal Type SL GPIO Designated Function XB X_SDIO0_WRPT I. V GPIO_D XB X_SDIO0_PWREN O. V GPIO_D XB X_SDIO0_BKPWR O. V GPIO_D XB X_SDIO0_INTN O. V GPIO_D XB X_SDIO0_DET I. V GPIO_D XB X_SPI0_CSN0 I. V GPIO_B XB X_SPI0_CLK I. V GPIO_B XB0 X_SPI0_TXD I/O. V GPIO_B XB X_SPI0_RXD I. V GPIO_B XB X_SPI0_CSN I. V GPIO_C0 XB XB XB XB XB X_GPIO_B /MAC_COL X_PMUGPIO0_A /MAC_RXD0 X_PMUGPIO0_A /MAC_RXD X_GPIO_B /MAC_RXER X_GPIO_A /PMIC_EXT_TS O. V GPIO_B O. V PMUGPIO0_A O. V PMUGPIO0_A I. V GPIO_B WLAN interrupt request at WIFI connector X- Bluetooth enable at WIFI connector X- WLAN enable at WIFI connector X- Bluetooth wake-up at WIFI connector X- USB host over-current detection (active low) USB host over-current detection (active low) Interrupt request from resistive touch control U User-programmable GPIO at X- AV interrupt request at X-, X0- and X-B USB hub U interrupt request (active low) Reset at USB hub U and Ethernet PHY U (active low) Camera interface deserializer U output enable (REN) Camera interface deserializer U power down input (npwrdn) (active low) Interrupt request from RTC U and Ethernet PHY U (nm) O. V GPIO_A/ Control of system supply via USB OTG and/or battery pack XC0 X_PMUGPIO0_B O. V PMUGPIO0_B Display reset (J +)at X-, X0- Table : Specifically used Pins on the phycore-connector (continued) : If no Wi-Fi module is installed at X this GPIO can be used unrestrictedly at expansion connector X. : J selects the signal which is connected to pin XB. GPIO_A is brought out in the default configuration (section ). PHYTEC Messtechnik GmbH 0 L-e_

103 The phycore -RK on the phycore Carrier Board.. Power (X, X, X0, X) M R0 R X0 X X R R R0 R X X D F D X F X J 0 D D X0 0 J X X 0 0 X J X D X J X D D X 0 0 X D J J D S J0 D D 0 X 0 X D D0 J X BAT S S S S S J J J J D J0 J S X JP 0 X JP JP JP J X X X X J JP D0 JP JP JP0JP X JP JP JP JP JP X X X X X Figure 0: Powering Scheme The primary input power of the phycore-rk Carrier Board comes from either the wall adapter jack X (+ V), connector X (input current A), the lithium-ion battery connector X0 (input current. A), or Micro-USB connector X (input current A). Switching regulators on the carrier board generate five different voltages. These, together with the possible external power sources, supply the phycore-rk and the different components of the carrier board supported by the SOM. The following table lists the voltage domains and their main use. PHYTEC Messtechnik GmbH 0 L-e_

104 phycore -RK [PCM-0] Voltage domain VCC_EXT_V VCC_LiIon_BATT+ VCC_LiIon_BATT- VDD_BATT+ VDD_IN_OTG_OUT VCCV VCC Table : Description Main V supply voltage from wall adapter input at X or -pole connector X. Can be measured at ADC_IN0 (section...). Lithium-Ion battery supply voltage connected to the battery anode. The battery voltage level can be between. V and. V with a maximum current flow of A. Lithium-Ion battery supply voltage connected with battery cathode. A 0 mω current sense resistor connects VCC_LiIon_BATT- to GND for measuring purposes (section...). Lithium-Ion battery supply voltage. It is connected to the BAT input pins of the PMIC on the module. If the PMIC is in battery charging mode, current will flow in the opposite direction on the carrier board to charge the battery. V power supply for carrier board and SOM (voltage regulators, voltage measurement, USB current regulators, Phytec Display Interface connectors, Data Display Group connectors, alternative video connector, HDMI, expansion connector, RGB dimming LED). Can be measured at ADC_IN (section...) It comes from two different sources: VCC_EXT_V X_USBOTG_VBUSOUT from the Micro-USB port It is connected to the PMIC USB/OTG pins. Current can flow in both directions on the carrier board depending on how the phycore module is powered (by the battery, USB OTG port, or an external V supply) and how the PMIC boost converter is configured. PMIC can switch off current flowing from PMIC to VDD_IN_OTG_OUT domain through its OTG switch.. V supply voltage from carrier board's voltage regulator U. Ranges from V to. V with maximum A DC output current (NTC reference voltage regulator U, voltage measurement, ADC multiplexer, RS- transceivers, Ethernet PHY, Ethernet connector LEDs, USB hub, micro SD card, JTAG connector, Phytec Display Interface connectors, light sensing ADC, Data Display Group connectors, alternative audio connector, HDMI CEC, camera interface, audio codec, MIPI connector, Wi-Fi/Bluetooth connector, expansion connector, resistive touch controller, RTC, EEPROM, LED, and pull-ups),. Can be measured at ADC_IN (section...). V supply voltage from carrier board's voltage regulator U. Ranges from V to V with maximum 00 ma DC output current (available for display backlight). Voltage Domains on the Carrier Board PHYTEC Messtechnik GmbH 0 L-e_

105 Voltage domain VCCV VCCV VCC_NTCREF_V VDD_SYS VDD_V_IO VDD_HDMIV VDD_SD VDD_ETH_DVDDH VDD_BYP Table : Description The phycore -RK on the phycore Carrier Board. V supply voltage from carrier board's voltage regulator U. Ranges from. V to V with maximum A DC output current (available for USB hub, Wi-Fi/Bluetooth connector, expansion connector).. V supply voltage from carrier board's voltage regulator U. Ranges from. V to V with maximum A DC output current (available for audio codec, Ethernet PHY, expansion connector).. V NTC reference voltage from carrier board's voltage regulator U. Ranges from. V to. V. Supply voltage from module. Ranges from. V to. V (on carrier board available for voltage regulators, voltage measurement, USB current regulators, Phytec Display Interface connectors, expansion connector). Can be measured at ADC_IN0 (section...).. V supply voltage from module (available at expansion connector). Can be measured at ADC_IN (section...). V supply voltage from module (available at HDMI and expansion connector). Can be measured at ADC_IN (section...).. V supply voltage from module (available at micro SD card slot and expansion connector). V supply voltage (available for Ethernet PHY pin DVDDH and pull-ups) USB hub internal regulator output. V (available for hub reference clock configuration and pin VDD_CORE_REG) Voltage Domains on the Carrier Board PHYTEC Messtechnik GmbH 0 L-e_

106 phycore -RK [PCM-0] Seven LEDs on the phycore Carrier Board show the status of the different voltage domains. The assignment of the LEDs to the voltage domains is shown in the following table: LEDs Color Description D0 yellow X_USBOTG_VBUS: V USBOTG VBUS attached to connector X D green VCC_EXT_V: V input voltage attached to connector X or X D green VCC_LiIon_BATT+: Lithium-ion battery input voltage VCC_LiIon_BATT+ at X0 D0 green VDD_SYS: PMIC system voltage generated on the phycore- RK D green VCCV:. V supply voltage from voltage regulator U for various peripherals on the phycore Carrier Board D green VCCV:. V supply voltage from voltage regulator U for various peripherals on the phycore Carrier Board D green VCCV:. V supply voltage from voltage regulator U for various peripherals on the phycore Carrier Board D green VCCV: V supply voltage from voltage regulator U for various peripherals on the phycore Carrier Board Table : Power LEDs on the phycore-tk Carrier Board... Power Supply Options The phycore Carrier Board is designed to be powered from three different power sources which can be connected at the same time. The following table shows the different options: Single Power Supply Double Power Supplies Triple Power Supplies Table : Only external V (from X or X) Only lithium-ion battery (at X0) Only USB OTG VBUS port (from X) External V (from X or X) together with lithium-ion battery (at X0) External V (from X or X) together with USB OTG VBUS (from X) Lithium-ion battery (at X0) together with USB OTG VBUS (from X) External V (from X or X), lithium-ion battery (at X0) and USB OTG VBUS (from X) all at the same time Power Supply Conditions of the Carrier Board PHYTEC Messtechnik GmbH 0 L-e_

107 The phycore -RK on the phycore Carrier Board Note: When the carrier board is powered by USB OTG VBUS, the switch status of MOSFET Q must be carefully controlled. Please see section "Power Supply via Micro-USB Connector (X)".... Power Supply via Wall Adapter Input (X) Power jack X is designed for powering the board with an AC wall adapter. The output voltage from the AC wall adapter feeds voltage domain VCC_EXT_V. LED D indicates the availability of the external V supply voltage. Caution! Ensure to use only an AC wall adapter with good power quality! Power spikes during poweron could destroy the phycore module mounted on the carrier board! Do not change modules or jumper settings while the carrier board is supplied with power! Permissible input at X: + V DC regulated (< A). The required current load capacity of the power supply depends on the specific configuration of the phycore mounted on the carrier board, the particular interfaces enabled while executing software as well as whether an optional expansion board, or any other external devices (e.g. USB devices) are connected to the carrier board. An adapter with a minimum supply of.0 A is recommended. Caution! The power supply circuitry on the carrier board is not designed to support all connectable devices at the same time! Note: If many functions and peripherals of the phycore-rk kit are used at the same time the power consumption might exceed W ( V / A). Wall Adapter Input X is not capable of supporting this. In this case connector X must be used. This connector supports a current of up to A. Polarity: -- + Figure : GND + VDC 000 ma Center Hole. mm. mm Power Connector corresponding to Wall Adapter Input (X) PHYTEC Messtechnik GmbH 0 L-e_

108 phycore -RK [PCM-0]... Power Supply via Pin Connector X An alternative -pol pin connector (X) provides the convenience of powering the board with a laboratory power device and a higher supply current. The voltage from this connector feeds the same voltage domain (VCC_EXT_V ) as the power jack X. LED D indicates the availability of the external V supply voltage. Caution! Ensure to use only an power supplys with good power quality! Power spikes during poweron could destroy the phycore module mounted on the carrier board! Do not change modules or jumper settings while the carrier board is supplied with power! Permissible input at X: V DC regulated (< A). The required current load capacity of the power supply depends on the specific configuration of the phycore mounted on the carrier board, the particular interfaces enabled while executing software as well as whether an optional expansion board, or any other external devices (e.g. USB devices) are connected to the carrier board. An adapter with a minimum supply of.0 A is recommended. Caution! The power supply circuitry on the carrier board is not designed to support all connectable devices at the same time! Even if a power device with higher power output is used to feed the board at X, the highest permissible current is still limited by PCB trace width and output capabilities of on-board voltage regulators. It is recommended not to use all functional interfaces supported by the phycore-rk at the same time. Ensure that the power consumption does not to exceed W ( V / A).... Power Supply via Battery Connector (X0) The phycore-rk offers the smart battery management functionalities which enables supplying the module with some lithium-based batteries. Connector X0 (-pole TE Connectivity MTA-00 Friction Lock Header ) provides the connectivity to a lithium-ion or a lithium polymer battery cell (or pack). The voltage from this connector feeds the voltage domain VCC_LiIon_BATT+. LED D indicates the availability of the battery supply voltage. Pin # Signal name Description VCC_LiIon_BATT+ Battery positive terminal X_PMIC_BAT_TS Battery thermistor VCC_LiIon_BATT- Battery negative terminal Table : Battery Connector X0 Signal Description Permissible input at X0: standard battery cell voltage. V -. V DC (< A). : Mating connectors: e.g. TE Connectivity MTA-00 series -00-, --, or PHYTEC Messtechnik GmbH 0 L-e_

109 The phycore -RK on the phycore Carrier Board Note: Although no battery is connected to the carrier board, LED D might still light up (showing minor blinking). This is because the battery supplying current and battery charging current share the same pins. If the PMIC on the module is in battery charging mode, the PMIC might generate an output voltage (might be square-wave shape) at voltage domain VDD_BATT+. Caution! Powering the module with lithium-based batteries requires the control over battery charging/discharging, temperature, current and capacity, and importantly, power balancing between the battery and other power supplies. All the control functions must be programmed to the PMIC via I C interface and monitored using the PMIC battery fuel gauge. The current software version does NOT support battery management feature! The battery input current and maximal charge current is suggested to be A, representing the maximum power that the battery can provide is less than W. If many functions and peripherals of the phycore-rk kit are used at the same time the power consumption might exceed this power range. Do not change modules or jumper settings while the carrier board is supplied with power!... Power Supply via Micro-USB Connector (X) Micro-USB X provides an USB OTG interface which can deliver a V supply voltage (up to 00 ma at pin VBUS) to any device connected to the carrier board. Reversely, the carrier board can also act as device to receive supply voltage via pin VBUS of Micro-USB connector X. LED D0 indicates the presence of the V supply voltage at Micro-USB port pin VBUS. Caution! The V supply voltage from Micro-USB port VBUS pin is connected with power domain VDD_IN_OTG_OUT through the MOSFET switch Q or the ideal diode switch D. In default settings, switch Q is in OFF state. When the carrier board is only powered by Micro-USB port, D switches on automatically and Q is allowed to switch on by setting GPIO_A high. When the carrier board is powered by lithium-ion battery (section...) and Micro-USB port at the same time, D switches off automatically (if the PMIC OTG switch is on) and Q is allowed to switch on by setting GPIO_A high. Q must stay in OFF state (by setting GPIO_A low) as long as VCC_EXT_V is present! Note: The carrier board can be powered up only by Micro-USB port, when the consuming current of the whole board does not exceed the standard Micro-USB port current limit. Some of the USB AC/DC wall adapters support up to A output current. When the carrier board is connected with no load, such as display or USB devices, as well as no lithium-ion battery to charge, the highest booting current of the system will be less than A, but higher than 00 ma. When the board is connected with load, booting/operating current will exceed Micro-USB power source limit, leading to unsuccessful booting. PHYTEC Messtechnik GmbH 0 L-e_

110 phycore -RK [PCM-0]... Current, Temperature and Voltage Supervision... Battery Charging / Discharging Current Sensing Pins SNSP (battery charging/discharging sensing current positive pin) and SNSN (battery charging/discharging sensing current negative pin) of the PMIC on the module are used to receive the voltage across the 0 mω current sensing resistor R to detect current flow from VCC_LiIon_BATT- to GND, or from GND to VCC_LiIon_BATT-. SNSP and SNSN accept input voltage in the range of - mv to mv. Current sensing can be disabled by removing jumper R0 and R0, or mounting a 0 Ω resistor at R.... Battery Pack Temperature Monitoring Thermistor input (TS) of the PMIC on the phycore-rk is brought out at pin of battery connector X0. It allows connecting an NTC thermistor inside a battery-pack in order to monitor the battery-pack's temperature. When the TS (thermistor input) is active, it will sink a constant current (0. ma) into the thermistor inside the battery-pack. It will then measure the voltage across the thermistor through an internal ADC. The ADC input voltage must be in the range of 0 V to. V. It may be necessary to match the serial/parallel resistor (R or R) for the thermistor, to guarantee the input voltage at TS is in the allowed range. The input voltage at TS varies along with the temperature change inside the battery pack. Make sure the measured voltage covers a wide enough temperature range in which the battery works safely. Battery charge activities on/off are controlled by the PMIC on the phycore-rk by comparing the measured temperature with the upper/lower temperature limit preset in the corresponding PMIC register. The temperature limits should be mentioned in the battery-pack's documentation. Note: To measure the battery pack's temperature at least a 0 Ω resistor must be installed at R on the carrier board. : All special functions of the PMIC such as battery management, etc. require the PMIC to be programmed via I C interface. At the time of delivery only the generation of the required voltages is implemented. Please refer to the Power Management IC's datasheet for more information on how to program the PMIC. PHYTEC Messtechnik GmbH 0 L-e_

111 ... Supply Voltage Monitoring The phycore -RK on the phycore Carrier Board The carrier board supports measuring of six supply voltages. The ADC multiplexer at U connects always three supply voltages to the RK's Successive Approximation Register (SAR) analog digital converter. Signal X_CIF_D (GPIO_A) selects the voltages to be measured. The following table shows which voltages are selected depending on GPIO_A. SAR-ADC input ADC_IN0 ADC_IN ADC_IN Table : Signal level GPIO_A Low VCC_EXT_V: External supply voltage from X or X the SOM VDD_V_IO: Supply voltage from the PMIC on the SOM VDD_IN_OTG_OUT: Main supply voltage for the SOM and CB, or USB OTG VBUS voltage Voltages Selection at U for Monitoring High VDD_SYS: Supply voltage from the PMIC on VCCV: Supply voltage from U on the CB VDD_HDMIV: HDMI supply voltage from the PMIC on the SOM PHYTEC Messtechnik GmbH 0 L-e_

112 B A B A B A B A B A B A B A B A B D C B A C C C A C C A D C C B C0 B D C B A C D C D B D0 C0 B A B C B C A0 B0 D A D C B A A A D C A C B A0 C A C B C C C D C D D phycore -RK [PCM-0].. RS- Connectivity (X, X) D JP JP JP JP S B B0 B B B B BBB B B BB B BB B B B B B0B B B B B B B B B0 B B B B B B B B B 0 A A A A A A A A A A A0 A B D D D D S S S S S D0 S 0 0 D D 0 M D D JP JP JP X X X J0 JP X X0 JP J JP0JP X JP J J J X X X J X X JP D0 JP X BAT J J J X B B B0 B B A A A A0 A A D D D D D D D D D D D D D D D D D D D D D D D D D D0 D D D D D D D0 D D D D D0 D D D D D0 D D D D D0 B B A A B B0 B B A A B B C C C C C C B B B0 B B X A A A A A A0 A A X C C B B B A A A A X C C C C C C0 C C C C0 C C C0 C C C0 B B0 B B B B0 B A A A A A A A A A A A0 A A0 C C B B B B A A B B B B B B B A A C C C C B B0 C C C C C C J J J0 J D D D D J X X X X X X J X0 X X X U X U F X X0 X X J Figure : RS- Interface Connectors X and X The phycore Carrier Board supports UART interfaces UART0, UART and UART provided by the phycore module. Connectors X (DB- male connector) and X (DB- female connector) provide connection interfaces to UART0 (X) and UART (X) of the phycore-rk. Two RS- transceivers (U, U) on the carrier board convert the TTL level signals from the phycore-rk to RS- level signals. The serial interface UART0 allows for a -wire connection including the signals RTS and CTS for hardware flow control. UART provides only signals TX and RX v. Figure and Figure below show the signal mapping of the RS- level signals at connectors X and X. PHYTEC Messtechnik GmbH 0 L-e_

113 The phycore -RK on the phycore Carrier Board The TTL signals of UART are routed to the Wi-Fi/Bluetooth connector X. Please refer to section.. for more information on how to use the signals of serial interface UART on the Wi-Fi/Bluetooth connector X at TTL level. The RS- interfaces at connector X (UART0) and X (UART) are hard-wired and no jumpers must be configured for proper operation. Pin : Pin : Pin : Pin : Pin : RxD RS- RTS RS- TxD RS- CTS RS- GND Figure : RS- Connector X (DB-M) Signal Mapping (UART0) Figure : Pin : TxD-RS Pin : RxD-RS Pin : GND RS- Connector X (DB-F) Signal Mapping (UART) PHYTEC Messtechnik GmbH 0 L-e_

114 B A B A B A B A B A B A B A B A B D C B A C C C A C C A D C C B C0 B D C B A C D C D B D0 C0 B A B C B C A0 B0 D A D C B A A A D C A C B A0 C A C B C C C D C D D phycore -RK [PCM-0].. Ethernet Connectivity (X) M X0 X X 0 0 D D X X X X J 0 D D X0 0 J U X X 0 0 X J D X X A A A A0 A A A A0 A A0 A A A A A A A A A A0 A A A A A A A A A A A A A A A A A A A D D J X X D 0 0 B B B0 B B B B B0 B B B B B0 B B B B B B B0 B B B B B B B0 B B B B B B B B B B B B B B0 X J 0 D J S J0 D D 0 C C C C0 C C C C0 C C C0 C C C0 X 0 C C C C C C C C C C C C C C C C C C C C C C X 0 D D D D D D D D D D D D D D D D D D D D D D D D D D D0 D D D D D D D0 D D D D D0 D D D D D0 D D D D D0 D0 J X BAT S S S S S J J J J J0 D J S X JP 0 X JP JP JP J X X X X J JP JP0JP A A A A A0 A JP JP X JP D0 A A A A A A JP JP JP JP B0 BB B B B BB BB BB B B B B BB B B0 B B B B B B B B B0 B B B B B B B B B B B X X X X X Figure : Ethernet Interfaces at Connectors X The phycore's Ethernet interface ETH0 (0/00/000 Mbit/s) is accessible at the RJ- connector (X) on the carrier board. The LEDs for LINK (green) and SPEED (yellow) indication, and the magnetics are integrated in the connector. The Ethernet transceiver on the SOM supports the HP Auto-MDIX function, eliminating the need for considerations of a direct connect LAN cable or a cross-over patch cable. The transceiver detects the TX and RX signals of the connected device and automatically configures its TX and RX pins accordingly. PHYTEC Messtechnik GmbH 0 L-e_

115 D D D 0 0 D D D B B B B A D C B D D B C B C0 B B B B C B0 D D C B A C B C D C D D The phycore -RK on the phycore Carrier Board.. USB OTG Connectivity (X) M X0 X X X X 0 0 D D X X J 0 D D X0 0 J X X 0 0 X J X D X A A A A A A A A A0AAAAA A A A AAAAAAA A0 AA AA0 A AAA A A AA A0 A AA A AA A AA0 AA A A AA AA A0 AA X D D J 0 0 B B B B B B0BB B BB B B BB0BB B B B B B0B B B BB BB B0 B BB BBB0 B B B B B B BBB B B B0 X X D J 0 D J S J0 D D 0 C C C C C C0 CC CC0 C CCC C0 C C C C C C C C0 CC CCCC C C C C C C0 CCCC C CC C C C C C C CCC C X 0 X 0 D D D D D D D D0 D D0 D DD0DD DD D D D0 D D DDD DD D D DD D D D D D0 D D D DD DDDDD0DD D DDD D D0 J X BAT S S S S S J J J J J0 D J S X JP 0 X JP JP JP J X X X X J A A A A A0 A D0 JP JP JP0JP X JP A A A A A A JP JP JP JP JP B0 BB B B B BB BB BB B B B B BB B B0B B B B B B B B B0 B B B B B B B B B B B X X X X X Figure : USB OTG Interface at Connector X The USB OTG interface of the phycore is accessible at connector X (USB Micro-AB) on the carrier board. The phycore-rk supports the On-The-Go feature. USB OTG (On-The-Go) devices are capable of initiating the session, controlling the connection and exchanging host and peripheral roles between each other. This interface is compliant with USB revision.0. Jumper JP configures the OTG operating mode with the X_USBOTG_ID signal. By default this jumper is open, which leaves the ID pin floating, and thus configuring the interface mode as USB OTG. Alternatively this jumper can be closed, connecting the ID signal to GND, and configuring the interface mode as host. Typically the configuration of a connecting device as host or slave is done automatically via the USB cable. However, given the limited number of OTG enabled devices in the embedded PHYTEC Messtechnik GmbH 0 L-e_

116 B A B A B A B A B A B A B A B A B D C B A C C C A C C A D C C B C0 B D C B A C D C D B D0 C0 B A B C B C A0 B0 D A D C B A A A D C A C B A0 C A C B C C C D C D D B phycore -RK [PCM-0] market this jumper is provided to either simulate an OTG cable, or force the OTG interface into host mode when OTG operation is not required. LED D0 (yellow) signals USBOTG_VBUS power input/output. USBOTG_VBUS power presence is detected by the phycore-rk through the OTG_VBUS pin (XD)... USB Host Connectivity (X, X) M X0 X X X X 0 0 D D X X J 0 D D X0 0 J X X 0 0 X J X D X A A A A0 A A A A0 A A0 A A A A A A A A A A0 A A A A A A A A A A A A A A A A A A A J X U D D X 0 0 B B B0 B B B B B0 B B B B B0 B B B B B B B0 B B B B B B B0 B B B B B B B B B B B B B B0 X D J 0 D D D J S J0 0 C C C C0 C C C C0 C C C0 C C C0 X 0 C C C C C C C C C C C C C C C C C C C C C C X 0 D D D D D D D D D D D D D D D D D D D D D D D D D D D0 D D D D D D D0 D D D D D0 D D D D D0 D D D D D0 D0 J X BAT S S S S S J J J J J0 D J S X JP 0 X JP JP JP J X X X X J JP JP0JP A A A A A0 A JP JP X JP D0 A A A A A A JP JP JP JP B0 BB B B BBB BB BB B BB B BB B B0B B B B B B B B B0 B B B B B B B B B B X X X X X Figure : Components supporting the USB Host Interfaces The USB host interfaces (USB host and USB host) of the phycore are accessible at connector X (USB.0, type A, dual port, angled standing) on the carrier board. These interfaces support control of input USB devices such as keyboard, mouse or USB key. The USB host interface (EHCI controller) is compliant only with USB revision.0, whereas the USB host interface (DW controller) is compliant with USB revision.0 and.. These two interfaces provide the data lines D+ and D-, as well as the supply line Vbus. USB host is brought out at the lower socket of X and USB host at the upper socket. The USB host interface is also accessible at display data connector X (only data lines D+ and D-). PHYTEC Messtechnik GmbH 0 L-e_

117 The phycore -RK on the phycore Carrier Board LEDs D (yellow) and D (yellow) indicate the presence of the VBUS supply voltages X_USBHOST_VBUSOUT (D) and X_USBHOST_VBUSOUT (D).... USB HSIC Connectivity (X) The phycore-rk provides an USB.0 High-Speed Inter-Chip interface (HSIC) which operates in host mode. It is compliant with USB revision.0 and Enhanced Host Controller Interface Specification.0. HSIC interfaces are optimized for portable electronic devices and poit-to-point applications. On the phycore-rk Carrier Board the HSIC interface connects to the upstream port of the High-Speed hub controller at U which provides two downstream facing ports. These ports extend to connector X (USB.0, type A, dual port, angled standing). These two interfaces provide the data lines D+ and D-, as well as the supply line Vbus. USB downstream port (USB_DN) is brought out at the lower socket of X and USB downstream port (USB_DN) at the upper socket. LEDs D (yellow) and D (yellow) indicate the presence of the VBUS supply voltages X_USBDN_VBUSOUT (D) and X_USBDN_VBUSOUT (D) (Figure ). Various resistors allow configuring the High-Speed hub controller at U as described in the following table. Resistor Value (Size) Populated Description R 0 Ω (00) no VCCV connected to VDD_CORE_REG input (. V R 0 Ω (00) yes regulator for digital logic core) R 0 Ω 00) yes VCCV connected to configuration resistors at R 0 Ω (00) no REF_SEL0 and REF_SEL (reference clock select) R 0 kω (00) yes Set REF_SEL to (if REF_SEL = and R 0 kω (00) no REF_SEL = 0, the primary R 0 kω (00) no reference clock is set to Set REF_SEL0 to 0 R0 0 kω (00) yes. MHz.) R 0 kω (00) no R 0 kω (00) yes Set HUB_CONNECT to 0 R 0 Ω (00) no R0 0 Ω (00) no I C interface IC disconnected from U R0 0 Ω (00) no Downstream ports are not disabled by hardware R0 0 Ω (00) no pull-up (R0 and R0 USBDN; R0 and R0 R0 0 Ω (00) no USBDN) R0 0 Ω (00) no Table : Hardware Default Configuration of HSIC Hub Controller U. : Due to the small size of the components' footprint it is generally not recommended to change the configuration. If necessary please contact our sales team to get to know how to order the configuration required. PHYTEC Messtechnik GmbH 0 L-e_

118 B A B A B A B A B A B A B A B A B D C B A C C C A C C A D C C B C0 B D C B A C B D C D B D0 C0 B A B C B C A0 B0 D A D C B A A A D C A C B A0 C B A B C B C C B B C B B D C D D B phycore -RK [PCM-0].. Display / Touch Connectivity M X0 X X X X D D 0 0 X 0 X0 0 J D J X 0 0 A A A A0 A A A A0 A A0 A A A A A A A A A A0 A A A A A A A A A A A A A A A A A A A J X X D D 0 0 B B B0 B B B B B0 B B B B B0 B B B B B B B0 B B B B B B B0 B B B B B B B B B B B B B B0 J J S J0 0 C C C C0 C C C C0 C C C0 C C C0 D 0 C C C C C C C C C C C C C C C C C C C C C C X D0 D D D D D D D D D D D D D D D D D D D D D D D D D D0 D D D D D D D0 D D D D D0 D D D D D0 D D D D D0 J BAT S S S S S D J0 J J J X JP S 0 JP JP JP J X X X J JP JP JP0 JP A A A A A0 A X A A A A A A B0 B B B B B B B B B B B B B B0 B B B B B B B B0 B B B B B B B B B JP JP JP JP X X X X X X J X X X X D D X 0 D D X 0 X J J X 0 X D0 JP JP D D Figure : Phytec Display Interface (PDI) at Connector X The phycore-rk Carrier Board provides four different ways to connect displays to the phycore-rk. The Phytec Display Interface (PDI) is intended to be used with a display specific display adapter at connector X, while the Phytec Audio/Video (A/V) connector (X, X) can be used with phyboard Expansion Boards (section...). Various connectors allow connecting displays from the Digital Display Group (section 0) and MIPI connector X is the fourth possibility to connect a display to the phycore-rk (section..).... Phytec Display Interface (PDI) (X) The various performance classes of the phycore family allow attaching a large number of different displays varying in resolution, signal level, type of the backlight, pinout, etc. In order not to limit the range of displays connectable to the phycore, the phycore carrier board provides, besides the special display connectors suitable only for a small number of displays, the Phytec Display Interface (PDI) at connector X. The new concept intends the : Please find additional information on phyboard Expansion Boards in the corresponding application guide (L-e). 00 PHYTEC Messtechnik GmbH 0 L-e_

119 The phycore -RK on the phycore Carrier Board use of an adapter board (e.g. Phytec s LCD display adapters LCD-0, LCD-0 and LCD-0) to attach a special display, or display family to the phycore. The Phytec Display- Interface (PDI) was defined to connect the adapter board to the phycore Carrier Board. It consists of two universal connectors which provide the connectivity for the display adapter. They allow also easy adaption to any customer display. One connector (0 pin FCC connector 0. mm pitch) at X is intended to connect all data signals to the display adapter. It combines various interface signals like LVDS, USB, I C, etc. required to hook up a display. The second connector of the PDI (TE Connectivity Micro-MaTch -0-) at X provides all supply voltages needed to supply the display and a backlight, and the brightness control. The following sections contain specific information on each connector.... Phytec Display Interface (PDI) Data Connector (X) PDI data connector X (Molex 0-pin FFC/FPC connector; 0. mm pitch; -0) provides display data from the serial LVDS display interface of the phycore-rk (section ). In addition other useful interfaces such as USB, I C, etc. are available at PDI data connector X. Table lists all miscellaneous signals and gives detailed explanations. The following table shows the pin-out of the PDI s display data connectors at X. The display data connector at X is 0 pin FCC connector with 0. mm pitch. Pin # Signal name ST SL Description B X_SPI_CLK O. V SPI clock B X_SPI_RXD I/O. V SPI master data in; slave data out B X_SPI_TXD O/I. V SPI master data out; slave data in B X_SPI_CSN0 O. V SPI chip select display B X_SPI0_RXD I/O. V Display interrupt input (connects to GPIO_B of the RK) B VCCV O. V Power supply display B X_IC_SCL OD_BI. V IC_AUDIO clock signal B X_IC_SDA OD_BI. V IC_AUDIO data signal B GND - - Ground B0 X_ PWM0 O. V PWM 0 brightness output B VCCV O. V Logic supply voltage B NC - - not connected B X_DISPLAY_ENABLE O. V Display enable signal (connects to GPIO_A of the RK) Table 0: PDI Data Connector X Signal Description : Provided to supply any logic on the display adapter. Max. draw 00 ma PHYTEC Messtechnik GmbH 0 L-e_ 0

120 phycore -RK [PCM-0] Pin # Signal name ST SL Description B X_IS_SDO I/O. V Hardware Introspection Interface for internal use only B GND - - Ground B X_USBHOST_DP I/O. V USB host data + B X_USBHOST_DM I/O. V USB host data - B GND - - Ground B X_LDCD0_D/LVDS_D0N LVDS_O RK internal LVDS transmit data 0- B0 X_LDCD0_D0/LVDS_D0P LVDS_O RK internal LVDS transmit data 0+ B GND - - Ground B X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - B X_LDCD0_D/LVDS_DP LVDS_O RK internal LVDS transmit data + B GND - - Ground B X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - B X_LDCD0_D/LVDS_DP LVDS_O RK internal LVDS transmit data + B GND - - Ground B X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - B X_LDCD0_D/LVDS_DP LVDS_O RK internal LVDS transmit data + B0 GND - - Ground B X_LDCD0_D/LVDS_CLK0N LVDS_O RK internal LVDS transmit clock0- B X_LDCD0_D0/LVDS_CLK0P LVDS_O RK internal LVDS transmit clock0+ B GND - - Ground B X_TS_X+ I/O. V Touch X+ (from touch panel controller at U) B X_TS_X- I/O. V Touch X- (from touch panel controller at U) B X_TS_Y+ I/O. V Touch Y+ (from touch panel controller at U) B X_TS_Y- I/O. V Touch Y- (from touch panel controller at U) B NC - - not connected B GND - - Ground B0 X_LS_ANA I. V Light sensor analog input (from ADC at U) Table 0: PDI Data Connector X Signal Description (continued) The following table shows the auxiliary interfaces at display data connector X. 0 PHYTEC Messtechnik GmbH 0 L-e_

121 The phycore -RK on the phycore Carrier Board Signal Description USBHOST USB host interface for optional features e.g. front USB. IC_AUDIO I C interface for optional EEPROM, or other I C devices SPI SPI interface to connect optional SPI slave PHYWIRE Hardware Introspection Interface For internal use only X_DISPLAY_ENABLE Can be used to enable, or disable the display, or to shutdown the backlight. It is connected to GPIO_A of phycore-rk. In default setup, GPIO_A is inverted by Q X_ PWM0 PWM output to control the brightness of a display's backlight (0%=dark, 00%=bright). LS_ANA Analog light sensor input. The analog light sensor input at pin 0 extends to an -bit A/D converter (U) which is connected to the IC bus at address 0x. To get the maximum adjustment range the output voltage of an applicable light sensor should range from 0 V to VREF (U internal.0 V). Table : Auxiliary Interfaces at PDI Data Connector X... Phytec Display Interface (PDI) Power Connector (X) The display power connector X (-position TE Connectivity Micro-MaTch SMD FTE connector;. mm pitch; -- ) provides all supply voltages needed to supply the display and a backlight. Pin # Signal name ST SL Description A GND - Ground A VCCV O. V. V power supply display A GND - Ground A VDD_IN_OTG_OUT O V V power supply display A GND - Ground A VDD_IN_OTG_OUT O V V power supply display A GND - Ground A VDD_IN_OTG_OUT O V V power supply display A GND - Ground A0 X_ PWM0 O. V PWM0 brightness output A VCCV O + V Backlight power supply A VCCV O + V Backlight power supply Table : PDI Power Connector X Signal Description : Mating connectors: Male-on-Wire connector (-0-), or Crimp-on-Snap-in housing (-0-) and crimp contact (e.g. 0-) : Jumper J allows to change the supply voltage for this pin from VDD_IN_OTG (default) to VDD_SYS (Table ). PHYTEC Messtechnik GmbH 0 L-e_ 0

122 phycore -RK [PCM-0]... DDG Display and Touch Connectivity (X, X, X0, X, X) Caution! Every time before powering up the device with a new display, check jumper and resistor settings and verify that the pin assignment is adapted correctly for the display to be connected. The phycore Carrier Board offers standard connectivity suitable for a number of LVDS displays from the Data Display Group (DDG). DDG display / touch modules contain onboard LVDS interface controllers and LED backlight units. To connect to a DDG display the carrier board provides five connectors to deliver the supply voltage with selectable voltage levels, LVDS data and clock signals, display backlight control, resistive touch signals and an I C bus to/from the display. The following sections contain specific information on each connector.... DDG LVDS Data Connector (X) The DDG LVDS data connector X (Hirose DF-P-.H 0 ) provides display data from the serial LVDS display interface of the phycore-rk (section.). Four data lanes and one clock lane from each of the two RK's LVDS transmitter are brought out at X. In addition to the LVDS data lanes, a supply voltage and a backlight enable signal are available at data connector X. The following table shows the pinout of the DDG LVDS data connector at X. Pin # Signal name ST SL Description, VDD_LVD_DDG 0. V, V, or Display supply voltage V (selectable with JP), GND - Ground X_LDCD0_D/LVDS_DP LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - X_LDCD0_D0/LVDS_CLK0P LVDS_O RK internal LVDS transmit clock0+ X_LDCD0_D/LVDS_CLK0N LVDS_O RK internal LVDS transmit clock0- X_LDCD0_D/LVDS_DP LVDS_O RK internal LVDS transmit data + 0 X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_DP LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - X_LDCD0_D0/LVDS_D0P LVDS_O RK internal LVDS transmit data 0+ Table : DDG LVDS Data Connector X Signal Description 0: Mating connector: Hirose DF-S-.C (housing), and DF-SCFA or DF-0SCFA (crimp contact) 0 PHYTEC Messtechnik GmbH 0 L-e_

123 The phycore -RK on the phycore Carrier Board Pin # Signal name ST SL Description X_LDCD0_D/LVDS_D0N LVDS_O RK internal LVDS transmit data 0- X_LDCD0_D/LVDS_DP LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_CLKP LVDS_O RK internal LVDS transmit clock + X_LDCD0_D/LVDS_CLKN LVDS_O RK internal LVDS transmit clock - X_LDCD0_D/LVDS_DP LVDS_O RK internal LVDS transmit data + 0 X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_DP LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - X_LDCD0_D/LVDS_DP LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - X_DISPLAY_ENABLE LVDS_O RK internal Display enable signal (GPIO_A) Table : DDG LVDS Data Connector X Signal Description (continued) Jumper JP allows selecting the voltage source for the supply voltage at pins and of connector X. JP Supply voltage at pins and of X + VDD_IN_OTG_OUT ( V) + VCCV (. V) + VCCV ( V) Table : JP Selecting the Supply Voltage at DDG LVDS Data Connector X : Default settings are in bold blue text PHYTEC Messtechnik GmbH 0 L-e_ 0

124 phycore -RK [PCM-0]... DDG Display Backlight Connector (X) The DDG display backlight connector X (Hirose DF-0P-.V ) provides all supply voltages needed to supply a display and a backlight. Display enable control and backlight PWM signal are also available at connector X. Pin # Signal name ST SL Description,, - O. V, V, Backlight supply voltage or V (selectable with JP),, 0 GND - Ground X_DISPLAY_ENABLE O. V Display enable signal (GPIO_A) X_DISPLAY_BACKLIGHT_PWM O. V Brightness control signal (PWM of the RK), - O Table :. V, V, or V DDG Display Backlight Connector X Signal Description Display supply voltage (selectable with JP) Jumpers JP and JP allow selecting the voltage source for the supply voltage at pins, and (JP), and pins and (JP) of connector X. JP Supply voltage at pins, and JP Supply voltage at pins and Supply voltage + + VDD_IN_OTG_OUT ( V) + + VCCV (. V) + + VCCV ( V) Table : JP and JP Selecting the Supply Voltage at DDG Display Backlight Connector X : Mating connector: Hirose DF-0S-.C (housing), and DF-0SCFA or DF-0SCFA (crimp contact) : Default settings are in bold blue text 0 PHYTEC Messtechnik GmbH 0 L-e_

125 ... DDG Resistive Touch Connector (X0) The phycore -RK on the phycore Carrier Board The DDG resistive touch connector X0 (Hirose DFA-0DP-.V ) provides signals X+, X-, Y+, Y- signals from a -wire resistive touch screen controller at U. A Display Reset, AV interrupt and an I C bus are also available at connector X0. Pin # Signal name ST SL Description VCCV PWR_O. V. V display supply voltage,,,,,,, NC - - not connected,, 0 X_SPI0_RXD I. V AV interrupt request (GPIO_B of the RK) X_DISPLAY_RESET O. V Display reset output (connected to X_nRESET via J ) X_TS_X+ I/O. V Touch X+ (from touch panel controller at U) X_TS_X- I/O. V Touch X- (from touch panel controller at U) X_TS_Y+ I/O. V Touch Y+ (from touch panel controller at U) 0 X_TS_Y- I/O. V Touch Y- (from touch panel controller at U) X_IC_SDA OD_BI. V IC_AUDIO data signal X_IC_SCL OD_BI. V IC_AUDIO clock signal,, GND - Ground Table : DDG Resistive Touch Connector X0 Signal Description... DDG Display Optional Connector (X) The DDG display optional connector X (Hirose DF-P-.H ) provides additional supply voltages for a display. Pin # Signal name ST SL Description,,,, - PWR_O, GND V, V,. V, or GND, GND - Ground Table : DDG Display Optional Connector X Signal Description The output at each pin can be individually configured with jumpers JP JP and JP (Table ) : Mating connector: Hirose DF-0DS-.C (housing), and DF-0SCFA or DF-0SCF (crimp contact) : Closing jumper J at + allows using GPIO PMUGPIO0_B as display reset signal (Table ). : Mating connector: Hirose DF-S-.C (housing), and DF-SCFA or DF-0SCFA (crimp contact) PHYTEC Messtechnik GmbH 0 L-e_ 0

126 phycore -RK [PCM-0]... DDG Display Extra LVDS Connector (X) DDG display extra LVDS connector X (Hirose DFA-P-.H ) provides the remaining LVDS signals of RK for 0-bit display and several supply voltages. Pin # Signal name ST SL Description NC,, NC GND - Ground X_LDCD0_D/LVDS_DP LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - X_LDCD0_D0/LVDS_DP LVDS_O RK internal LVDS transmit data + X_LDCD0_D/LVDS_DN LVDS_O RK internal LVDS transmit data - - PWR_O, Configurable with. V, or GND GND jumper JP (Table ) - PWR_O, Configurable with. V, or GND GND jumper JP (Table ) - PWR_O, GND V,. V, or GND Table : DDG Display Extra LVDS Connector X Signal Description... Phytec Audio/Video (A/V) Connectors (X, X) Configurable with jumper JP (Table ) Caution! Every time before powering up the device with a new display, check jumper and resistor settings and verify that the pin assignment is adapted correctly for the display to be connected. Audio/Video (A/V) connectors X and X provide an easy way to add typical A/V functions and features to the phycore-rk. Standard interfaces such as parallel LCD interface, I S and I C as well as different supply voltages are available at the two A/V female dual entry connectors. One special feature of these connectors is their connectivity from the bottom or the top. The A/V connector is intended for use with phyboard Expansion Boards, and to add specific audio/video connectivity with custom expansion boards. The pinout of the A/V connectors is shown in the following tables. : Mating connector: Hirose DF-S-.C (housing), and DF-0SCFA or DF-0SCFA (crimp contact) : Default settings are in bold blue text : Please get additional information on phyboard Expansion Boards from our sales team. 0 PHYTEC Messtechnik GmbH 0 L-e_

127 ... Audio/Video (A/V) Connector # (X) The phycore -RK on the phycore Carrier Board Audio/Video (A/V) connector # (X) (x dual entry socket connector mm pitch) provides signals for audio and touch screen connectivity, as well as an I C bus and additional control signals. Pin # Signal name ST SL Description X_IS_AV_SCLK I/O. V I S/PCM bit clock X_IS_AV_LRCK_TX I/O. V I S/PCM frame clock for transmitting serial data 0 X_IS_AV_SDI I. V I S/PCM serial data input X_IS_AV_SDO0 O. V I S/PCM serial data output 0 X_SPI0_RXD I. V AV interrupt request (GPIO_B of the RK) X_DISPLAY_ENABLE O. V Display enable signal (GPIO_A of the RK), GND - GND X_DISPLAY_RESET O. V Display reset output (connected to X_nRESET via J ) X_TS_X+ I/O. V Touch X+ (from touch panel controller at U) 0 X_TS_X- I/O. V Touch X- (from touch panel controller at U) X_TS_Y+ I/O. V Touch Y+ (from touch panel controller at U) X_TS_Y- I/O. V Touch Y- (from touch panel controller at U) VCCV PWR_O.V. V display supply voltage X_IC_SCL OD_BI. V IC_AUDIO clock signal X_IC_SDA OD_BI. V IC_AUDIO data signal Table 0: Phytec A/V Connector # (X) Signal Location 0: Removing R and mounting R connects signal X_IS_AV_LRCK_RX to pin of X. : Closing jumper J at + allows using GPIO PMUGPIO0_B as display reset signal (Table ). PHYTEC Messtechnik GmbH 0 L-e_ 0

128 phycore -RK [PCM-0]... Audio/Video (A/V) Connector # (X) Audio/Video (A/V) connector # (X) (x0 dual entry socket connector mm pitch) makes all parallel LCD signals for display connectivity available. Pin # Signal name ST SL Description GND - - Ground X_LDCD0_D/LVDS_DP O. V LCDC0 data red 0 X_LDCD0_D/LVDS_DN O. V LCDC0 data red X_LDCD0_D/LVDS_DP O. V LCDC0 data red X_LDCD0_D/LVDS_DN O. V LCDC0 data red GND - - Ground X_LDCD0_D0/LVDS_DP O. V LCDC0 data 0 red X_LDCD0_D/LVDS_DN O. V LCDC0 data red X_LDCD0_D/LVDS_CLKP O. V LCDC0 data red 0 X_LDCD0_D/LVDS_CLKN O. V LCDC0 data red GND - - Ground X_LDCD0_D/LVDS_DP O. V LCDC0 data green 0 X_LDCD0_D/LVDS_DN O. V LCDC0 data green X_LDCD0_D0/LVDS_CLK0P O. V LCDC0 data 0 green X_LDCD0_D/LVDS_CLK0N O. V LCDC0 data green GND - - Ground X_LDCD0_D/LVDS_DP O. V LCDC0 data green X_LDCD0_D/LVDS_DN O. V LCDC0 data green X_LDCD0_D/LVDS_DP O. V LCDC0 data green 0 X_LDCD0_D/LVDS_DN O. V LCDC0 data green GND - - Ground X_LDCD0_D0/LVDS_D0P O. V LCDC0 data 00 blue 0 X_LDCD0_D/LVDS_D0N O. V LCDC0 data 0 blue X_LDCD0_D/LVDS_DP O. V LCDC0 data 0 blue X_LDCD0_D/LVDS_DN O. V LCDC0 data 0 blue GND - - Ground X_LDCD0_D/LVDS_DP O. V LCDC0 data 0 blue X_LDCD0_D/LVDS_DN O. V LCDC0 data0 blue X_LDCD0_D/LVDS_DP O. V LCDC0 data 0 blue 0 X_LDCD0_D/LVDS_DN O. V LCDC0 data 0 blue Table : Phytec A/V Connector # (X) Signal Location 0 PHYTEC Messtechnik GmbH 0 L-e_

129 The phycore -RK on the phycore Carrier Board Pin # Signal name ST SL Description GND - - Ground X_LCDC0_DCLK O. V LCDC0 clock X_LCDC0_DEN O. V LCDC0 data enable X_LCDC0_HSYNC O. V LCDC0 horizontal sync pulse X_LCDC0_VSYNC O. V LCDC0 vertical sync pulse GND - - Ground GND - - Ground X_PWM O. V Brightness control PWM signal VCCV PWR_O V Backlight power supply 0 VDD_IN_OTG_OUT PWR_O V.0 V power supply display Table : Phytec A/V Connector # (X) Signal Location (continued)... Resistive Touch Control at U As many smaller applications need a touch screen as user interface, provisions are made to connect - wire resistive touch screens to the PDI data connector X (pins B - B, Table 0), Phytec A/V Connector X (pins, Table 0) and DDG Resistive Touch Connector X0 (pins 0, Table ). The signals from the touch screen panel are processed by a touch panel controller at U. The touch panel controller is connected to I C bus IC_SENSOR at address 0x. Jumper J0 allows changing the device address as shown in the table below. U I²C Addresses J0 0x + 0x + Table : Resistive Touch Controller U I²C Address Configuration (J0) An additional interrupt output is connected to X_SPI0_CLK (GPIO_B) of the phycore-rk : Defaults are in bold blue text PHYTEC Messtechnik GmbH 0 L-e_

130 B A B A B A B A B A B A B A B A B D C B A C C C A C C A D C C B C0 B D C B A C D C D B D0 C0 B A B C B C A0 B0 D A D C B A A A D C A C B A0 C B A B C B C C B B C B B D C D D phycore -RK [PCM-0].. High-Definition Multimedia Interface (HDMI) (X) M X0 X X X X 0 0 D D X X J 0 D D X0 0 J X X 0 0 X J D X X A A A A0 A A A A0 A A0 A A A A A A A A A A0 A A A A A A A A A A A A A A A A A A A X D D J X D 0 0 B B B0 B B B B B0 B B B B B0 B B B B B B B0 B B B B B B B0 B B B B B B B B B B B B B B0 X J 0 D J S J0 D D 0 C C C C0 C C C C0 C C C0 C C C0 X 0 C C C C C C C C C C C C C C C C C C C C C C X 0 D D D D D D D D D D D D D D D D D D D D D D D D D D D0 D D D D D D D0 D D D D D0 D D D D D0 D D D D D0 D0 J U X BAT S S S S S J J J J J0 D J S X JP 0 X JP JP JP J X X X X J JP A A A A A0 A JP JP JP0JP X JP D0 A A A A A A JP JP JP JP B0 B B B B B B B B B B B B B B0 B B B B B B B B0 B B B B B B B B B B B X X X X X Figure : HDMI Interface at Connector X The High-Definition Multimedia Interface (HDMI) of the phycore-rk module is compliant with HDMI.a and.0a specification, and implements HDCP.. It supports up to 00p at 0 Hz and k x k at 0 Hz HDTV display resolutions and up to QXGA graphic display resolutions. Please refer to the RK Technical Reference Manual for more information. The HDMI interface brought out at the shielded female connector X on the phycore Carrier Board is comprised of the following signal groups: three pairs of data signals, one pair of clock signals, an I²C bus which is exclusively for the HDMI interface, Consumer Electronics Control (CEC) and the hot plug detect (HPD) signal. Level shifters shift the I²C interface signals from I/O voltage (VCCV) to V. All HDMI signals available at connector X extend from the phycore-connector to the HDMI receptacle via an HDMI transmitter port protection device at U. PHYTEC Messtechnik GmbH 0 L-e_

131 The phycore -RK on the phycore Carrier Board Pin # Signal name ST SL Description HDMI_TXP TMDS_O HDMI HDMI data channel positive output GND - - Ground HDMI_TXN TMDS_O HDMI HDMI data channel negative output HDMI_TXP TMDS_O HDMI HDMI data channel positive output GND - - Ground HDMI_TXN TMDS_O HDMI HDMI data channel negative output HDMI_TX0P TMDS_O HDMI HDMI data channel 0 positive output GND - - Ground HDMI_TX0N TMDS_O HDMI HDMI data channel 0 negative output 0 HDMI_TCP TMDS_O HDMI HDMI clock positive output GND - - Ground HDMI_TCN TMDS_O HDMI HDMI clock negative output HDMI_CEC I/O. V HDMI Consumer Electronics Control (CEC) NC - - not connected HDMI_SCL OD_BI V HDMI I C clock (IC_SCL) HDMI_SDA OD_BI V HDMI I C data (IC_SDA) GND - - Ground V_OUT PWR_O V HDMI V power supply (either VDD_IN_OTG_OUT or VDD_HDMIV (default) selectable with J) HDMI_HPD I/O - HDMI hot plug detect signal 0 GND - - Shield connects to GND or Shield (via J) GND - - Shield connects to GND or Shield (via J) GND - - Shield connects to GND or Shield (via J) GND - - Shield connects to GND or Shield (via J) Table : HDMI Connector X Jumper J connects pins 0 to of HDMI connector X either directly to the common ground plane GND, or to the shield contact which connects to the ground plane via a resistor and a capacitor and which is also used at other shielded connectors (Ethernet, UART, USB, etc.). It should be adapted according to the HDMI device attached to the carrier board to reduce electrical noise from other electrical sources. J Description + All four shield pins are connected to GND + All four shield pins connect to the carrier boards' shield contact Table : J Selecting the Shield at Connector X : Default settings are in bold blue text PHYTEC Messtechnik GmbH 0 L-e_

132 phycore -RK [PCM-0].. Mobile Industry Processor Interface (MIPI) (X, X) On the phycore-rk carrier board the two MIPI interfaces D-PHY TXRX and D-PHY RX0 are provided at MIPI connector X (Molex SlimStack board-to-board connector; 0. mm pitch; -00 ) and expansion connector X (Figure ). Two MIPI data lanes from D-PHYs RX0 and TXRX are available on each connector. The MIPI clock lanes from D-PHYs RX0 and TXRX are brought out only on MIPI connector X. An I C (IC_CAM) bus and GPIO control signals are available in addition on X to allow connecting MIPI camera modules (section..0.). However, MIPI D-PHY TXRX can also be used to connect a MIPI display. The table below shows the pinout of connector X. Pin # Signal name ST SL Description GND - - Ground GND - - Ground X_MIPI_RX_D0P CSI-_I RK internal MIPI D-PHY RX0 receive data 0+ X_MIPI_TXRX_D0P MIPI_I/O RK internal MIPI D-PHY TXRX data 0+ X_MIPI_RX_D0N CSI-_I RK internal MIPI D-PHY RX0 receive data 0- X_MIPI_TXRX_D0N MIPI_I/O RK internal MIPI D-PHY TXRX data 0- GND - - Ground GND - - Ground X_MIPI_RX_DP CSI-_I RK internal MIPI D-PHY RX0 receive data + 0 X_MIPI_TXRX_DP MIPI_I/O RK internal MIPI D-PHY TXRX data + X_MIPI_RX_DN CSI-_I RK internal MIPI D-PHY RX0 receive data - X_MIPI_TXRX_DN MIPI_I/O RK internal MIPI D-PHY TXRX data - GND - - Ground GND - - Ground X_MIPI_RX_CLKP CSI-_I RK internal MIPI D-PHY RX0 receive clock+ X_MIPI_TXRX_CLKP MIPI_I/O RK internal MIPI D-PHY TXRX clock+ X_MIPI_RX_CLKN CSI-_I RK internal MIPI D-PHY RX0 receive clock- X_MIPI_TXRX_CLKN MIPI_I/O RK internal MIPI D-PHY TXRX clock- GND - - Ground 0 GND - - Ground X_IS_SDO O. V MIPI power on control (GPIO_A) X_SPI0_TXD I/O. V GPIO_B Table : MIPI Connector X : Mating Molex SlimStack board-to-board plug: -00, -00, PHYTEC Messtechnik GmbH 0 L-e_

133 The phycore -RK on the phycore Carrier Board Pin # Signal name ST SL Description X_IC_SCL OD_BI. V IC_CAM clock signal X_GPIO_B O. V MIPI CSI/DSI Enable (GPIO_B) X_IC_SDA OD_BI. V IC_CAM data signal TP - - Test point GND - - Ground GND - - Ground VCCV O.V.V camera supply voltage 0 VCCV O.V.V camera supply voltage Table : MIPI Connector X (continued) The locations of the MIPI signals at expansion connector X are shown in Table. PHYTEC Messtechnik GmbH 0 L-e_

134 B A B A B A B A B A B A B A B A B D C B A C C C A C C A D C C B C0 B D C B A C D C D B D0 C0 B A B C B C A0 B0 D A D C B A A A D C A C B A0 C A C B C C C D C D D phycore -RK [PCM-0]..0 Camera Interface (X, X) M X0 X X D D X X X 0 0 X J 0 D D X0 0 J U X X U J D 0 0 X J X X A A A A0 A A A A0 A A0 A A A A A A A A A A0 A A A A A A A A A A A A A A A A A A A D D J X X D J D 0 0 B B B0 B B B B B0 B B B B B0 B B B B B B B0 B B B B B B B0 B B B B B B B B B B B B B B0 X 0 J S J0 D D 0 C C C C0 C C C C0 C C C0 C C C0 X D 0 C C C C C C C C C C C C C C C C C C C C C C X 0 D D D D D D D D D D D D D D D D D D D D D D D D D D0 D D D D D D D0 D D D D D0 D D D D D0 D D D D D0 D0 J X BAT S S S S S J J J J J0 D J S X JP 0 X JP JP JP J X X X X J JP JP JP JP0JP A A A A A0 A JP D0 X A A A A A A JP JP JP JP B0 BB B B B BB BB BB B B B B BB B B0 B B B B B B B B B0 B B B B B B B B B B B X X X X X Figure 0: Camera Interface at Connector X and X The phycore-rk provides two types of camera interfaces (parallel and MIPI CSI-). On the target application the camera interfaces can thus be used to connect: camera modules with phycam-s(+) interface (Figure ) (requires an external deserializer) camera modules with phycam-p interface (section..0.) camera modules with MIPI CSI- interface (circuitry "MIPI" on the Phytec Carrier Board PCM- schematic) (section..0.) Based on the Phytec Carrier Board (PCM-) the following sections give a basic overview on how to connect a camera using the different interface options. Details on the position of the signals on the phycore Connector and further technical details can be found in section. ff. PHYTEC Messtechnik GmbH 0 L-e_

135 ..0. phycam-s(+) (LVDS) Camera Interfaces (X) The phycore -RK on the phycore Carrier Board The -channel 0-Bit LVDS random lock deserializer (U) on the phycore-rk Carrier Board is connected to the RK's camera sensor interfaces CIF PP. The LVDS deserializer at U converts the LVDS Signals received at connector X (Hirose DFA-P-.H ) on the carrier board to a 0-bit wide parallel data signal and separate clock. The 0-bit wide data bus consists of data bits and sync bits (HREF/VSYNC). The camera interface is compatible with the Phytec phycam-s+ camera interface standard. Figure depicts the signal path and Table the pinout of X. Information on the phycam-s+ standard can be found in the phycam-manual (L-). Pin # Signal name ST SL Description X_Camera0_L0P I ±0 mv Serial data LVDS input + X_Camera0_L0N I ±0 mv Serial data LVDS input - X_Camera0_RXCLK- O. V Reference clock LVDS input - X_IC_SDA_CAMERA OD_BI. V Camera I C data (IC_SDA) X_IC_SCL_CAMERA OD_BI. V Camera I C clock (IC_SCL) X_Camera0_RXCLK+ O. V Reference clock LVDS input + VCCV O. V. V supply voltage camera GND - - Ground GND - - Ground 0 GND - - Ground Table : Phytec phycam-s+ Camera Connector X Figure : Implementation of a phycam-s+ and two MIPI Interfaces on the phycore Carrier Board Note: It is not possible to use the MIPI CSI- interface and the CIF PP interface together at the Image Signal Processing (ISP) unit or the Video Input Processor (VIP) simultaneously. Connecting two camera modules is only possible if one connects to the ISP unit and the second one to the VIP. : Mating connector: Hirose DF-S-.C (housing), and DF-0SCFA or DF-0SCFA (crimp contact) PHYTEC Messtechnik GmbH 0 L-e_

136 phycore -RK [PCM-0]..0. MIPI CSI- Camera Interface (X) MIPI connector X (Molex SlimStack board-to-board connector; 0. mm pitch; - 00 ) provides two MIPI data lanes and one MIPI clock lane from each D-PHY (D-PHY RX0 and D-PHY TXRX) together with an I C (IC_CAM) bus and GPIO control signals. Use of the I²C bus, the camera clock signal and the control signals allows connecting a MIPI CSI- camera module directly. Table in section.. shows the pinout of MIPI connector X. Figure and Figure show the connection of the MIPI signals to the Image Signal Processing (ISP) unit and the Video Input Processor (VIP) of the RK. Note: It is not possible to use two MIPI CSI- interfaces together at the Image Signal Processing (ISP) unit or the Video Input Processor (VIP) simultaneously. Connecting two MIPI camera modules is only possible if one connects to the ISP unit and the second one to the VIP...0. phycam-p or Parallel Camera Interface On the phycore-rk Carrier Board the parallel camera interface of the phycore-rk is not available at a separate connector. However Figure depicts how to use the parallel camera interface on a custom application. Figure : Implementation of a phycam-p or parallel Camera Interface together with two MIPI Interfaces on a Custom Carrier Board As can be seen in Figure combining the phycore's parallel camera interface CIF PP, with an I²C bus and up to four GPIOs, used for optional control signals, facilitates easy implementation of a CMOS camera interface according to the phycam-p standard. Information on the phycam-p standard can be found in the phycam-manual (L-). : Mating Molex SlimStack board-to-board plug: -00, -00, PHYTEC Messtechnik GmbH 0 L-e_