3.3V CMOS Static RAM for Automotive Applications 4 Meg (256K x 16-Bit)

Transcription

1 .V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) IDTVYS IDTVYL Features 25K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. Equal access and cycle times Automotive: 2//2 One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power coumption via chip deselect Upper and Lower Enable Pi Single.V power supply Available in -pin, mil plastic SOJ package and a - pin, mil TSOP Type II package and a ball grid array, 9mm x 9mm package. Description The IDTV is a,9,-bit high-speed Static RAM organized as 25K x. It is fabricated using IDT s high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs and automotive applicatio. The IDTV has an output enable pin which operates as fast as 5, with address access times as fast as. All bidirectional inputs and outputs of the IDTV are LVTTL-compatible and operation is from a single.v supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDTV is packaged in a -pin, mil Plastic SOJ and a -pin, mil TSOP Type II package and a ball grid array, 9mm x 9mm package. Functional Block Diagram OE Output Enable A -A Address s Row / Column Decoders Chip Select Write Enable,9,-bit Memory Array See Amps and Write Drivers High Output High Write Low Output I/O I/O I/O Low Write I/O BHE BLE Enable s drw 2 Integrated Device Technology, Inc. DECEMBER 2 DSC-/

2 IDTVYS, IDTVYL.V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) Pin Configuratio - SOJ/TSOP Pin Configuratio - BGA A A A2 A A I/O I/O I/O 2 I/O VDD SO- SO-2 VSS 2 I/O I/O 5 I/O I/O A5 A A A A A A A OE BHE BLE I/O I/O I/O I/O 2 VSS VDD I/O I/O I/O 9 I/O NC* A A A2 A A 2 5 A BLE OE A A A2 NC B I/O BHE A A I/O C I/O I/O2 A5 A I/O I/O9 D VSS I/O A A I/O VDD E VDD I/O NC A I/O2 VSS F I/O I/O5 A A I/O I/O G I/O NC A2 A I/O H NC A A9 A A NC tbl Pin Descriptio A - A Address Inputs Input Chip Select Input *Pin 2 can either be a NC or connected to Vss Top View drw 2 Write Enable Input OE Output Enable Input BHE High Enable Input BLE Low Enable Input I/O - I/O Data Input/Output I/O VDD.V Power Pwr VSS Ground Gnd tbl Truth Table () OE BLE BHE I/O-I/O I/O-I/O Function H X X X X High-Z High-Z Deselected - Standby L L H L H DATAOUT High-Z Low Read L L H H L High-Z DATAOUT High Read L L H L L DATAOUT DATAOUT Word Read L X L L L DATAIN DATAIN Word Write L X L L H DATAIN High-Z Low Write L X L H L High-Z DATAIN High Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled NOTE:. H = VIH, L = VIL, X = Don't care. tbl.2 2

3 IDTVYS, IDTVYL.V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) Absolute Maximum Ratings () Symbol Rating Value Unit VDD Supply Voltage Relative to -.5 to +. V VIN, VOUT VSS Terminal Voltage Relative to VSS -.5 to VDD+.5 V TBIAS Temperature Under Bias -55 to +25 o C TJ Junction Temperature Range - to + o C TSTG Storage Temperature -5 to + o C PT Power Dissipation W IOUT DC Output Current 5 ma NOTE: tbl. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. SOJ/TSOP Capacitance (TA = +25 C, f =.MHz) Symbol Parameter () Conditio Max. Unit CIN Input Capacitance VIN = dv pf CI/O I/O Capacitance VOUT = dv pf tbl 2 Recommended Operating Temperature and Supply Voltage Grade Temperature VSS VDD Automotive Grade - C to +25 C V See Below Automotive Grade 2 - C to + C V See Below Automotive Grade - C to +5 C V See Below Automotive Grade C to + C V See Below Recommended DC Operating Conditio tbl 5 Symbol Parameter Min. Typ. Max. Unit VDD Supply Voltage... V VSS Ground V VIH Input High Voltage 2. VDD+. () V VIL Input Low Voltage -. (). V tbl NOTE:. Refer to maximum overshoot/undershoot diagram below. The measured voltage at device pin must not exceed half sinusoidal wave with 2V peak and half period of 2. Maximum Overshoot/Undershoot BGA Capacitance (TA = +25 C, f =.MHz) VIH +2V 2 Symbol Parameter () Conditio Max. Unit CIN Input Capacitance VIN = dv pf CI/O I/O Capacitance VOUT = dv pf VIL 2-2V drw 2 NOTE: tbl 2b. This parameter is guaranteed by device characterization, but not production tested..2

4 IDTVYS, IDTVYL.V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) DC Electrical Characteristics (VDD = Min. to Max., ) Symbol Parameter Test Conditio Automotive Temperature Grade Min. IDTV Max. Unit ILI Input Leakage Current VDD = Max., VIN = VSS to VDD ILO Output Leakage Current VDD = Max., = VIH, VOUT = VSS to VDD and 2 5 and and 2 5 and µa µa VOL Output Low Voltage IOL = ma, VDD = Min.. V VOH Output High Voltage IOH = -ma, VDD = Min. 2. V (, 2, ) DC Electrical Characteristics (VDD = Min. to Max., VLC =.2V, VHC = VDD.2V, ) Symbol ICC ISB ISB Parameter Dynamic Operating Current < VLC, Outputs Open, VDD = Max., f = fmax IDTVS/VL VS/L2 VS/L VS/L2 Automotive Grade Automotive Grade Automotive Grade 2 and 2 and 2 and S Max L Max Typ. () Dynamic Standby Power Supply Current > VHC, Outputs Open, VDD = Max., f = fmax S L Max. Max Full Standby Power Supply Current (static) S Max > VHC, Outputs Open, VDD = Max., f = L Max. tbl tbl. All values are maximum guaranteed values. 2. All inputs switch between.2v (Low) and VDD -.2V (High).. fmax = /trc (all address inputs are cycling at fmax); f = mea no address input lines are changing.. Typical values are measured at.v, 25 o C and with equal read and write cycles. This parameter is guaranteed by device characterization but is not production tested. Unit ma ma ma AC Test Loads.V +.5V 5Ω DATA OUT 2Ω I/O Z =5Ω pf 5pF* 5Ω taa, ta (Typical, ) 5 2 Figure. AC Test Load CAPACITANCE (pf) drw 5 Figure. Output Capacitive Derating drw *Including jig and scope capacitance. Figure 2. AC Test Load (for tclz, tolz, tchz, tohz, tow, and twhz) AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load drw GND to.v.5.5v.5v Figures,2 and tbl 9.2

5 IDTVYS, IDTVYL.V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) AC Electrical Characteristics (VDD = Min. to Max., ) VS/L2 VS/L VS/L2 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCLE trc Read Cycle Time 2 2 taa Address Access Time 2 2 ta Chip Select Access Time 2 2 tclz (,2) Chip Select Low to Output in Low-Z tchz (,2) Chip Select High to Output in High-Z toe Output Enable Low to Output Valid tolz (,2) Output Enable Low to Output in Low-Z tohz (,2) Output Enable High to Output in High-Z toh Output Hold from Address Change tbe Enable Low to Output Valid tblz (,2) Enable Low to Output in Low-Z tbhz (,2) Enable High to Output in High-Z tpu Chip Select Low to Power Up tpd Chip Select High to Power Down 2 2 WRITE CYCLE twc Write Cycle Time 2 2 taw Address Valid to End of Write tcw Chip Select Low to End of Write tbw Enable Low to End of Write tas Address Set-up Time twr Address Hold from End of Write twp Write Pulse Width tdw Data Valid to End of Write tdh Data Hold Time tow (,2) Write Enable High to Output in Low-Z twhz (,2) Write Enable Low to Output in High-Z. At any given temperature and voltage condition, tchz is less than tclz, tohz is less than tolz, and twhz is less than tow for any given device. 2. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.. This parameter is guaranteed by design and not production tested. Timing Waveform of Read Cycle No. (,2,) tbl trc toh taa toh DATAOUT PREVIOUS DATAOUT VALID. is HIGH for Read Cycle. 2. Device is continuously selected, is LOW.. OE, BHE, and BLE are LOW..2 5 DATAOUT VALID d

6 IDTVYS, IDTVYL.V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) Timing Waveform of Read Cycle No. 2 () trc taa toh OE BHE, BLE DATAOUT (2) ta tclz (2) tbe tblz toe tolz tohz tchz tbhz DATA OUT VALID VDD Supply Current ICC ISB tpu tpd drw. is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of, BHE, or BLE traition LOW; otherwise taa is the limiting parameter.. Traition is measured ±2mV from steady state. Timing Waveform of Write Cycle No. ( Controlled Timing) (,2,) twc taw BHE, BLE (2) tcw tbw twp twr (5) tchz (5) tbhz DATAOUT DATAIN tas PREVIOUS DATA VALID (5) twhz. A write occurs during the overlap of a LOW, LOW BHE or BLE, and a LOW. 2. OE is continuously HIGH. If during a controlled write cycle OE is LOW, twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during a controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified twp.. During this period, I/O pi are in the output state, and input signals must not be applied.. If the LOW or BHE and BLE LOW traition occurs simultaneously with or after the LOW traition, the outputs remain in a high-impedance state. 5. Traition is measured ±2mV from steady state..2 tdw DATAIN VALID (5) tow tdh DATA VALID drw

7 IDTVYS, IDTVYL.V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) Timing Waveform of Write Cycle No. 2 ( Controlled Timing) (,) twc taw tas (2) tcw BHE, BLE tbw twp twr DATAOUT tdw tdh DATAIN DATAIN VALID d9 Timing Waveform of Write Cycle No. (BHE, BLE Controlled Timing) (,) twc taw tas (2) tcw tbw BHE, BLE twp twr DATAOUT tdw tdh DATAIN DATAIN VALID. A write occurs during the overlap of a LOW, LOW BHE or BLE, and a LOW. 2. During this period, I/O pi are in the output state, and input signals must not be applied.. If the LOW or BHE and BLE LOW traition occurs simultaneously with or after the LOW traition, the outputs remain in a high-impedance state. d.2

8 IDTVYS, IDTVYL.V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) Ordering Information IDT V X X XX XXX X X Device Type Power Speed Package Process/ Temperature Range 2 Automotive Grade (- C to +25 C) Automotive Grade 2 (- C to + C) Automotive Grade (- C to +5 C) Automotive Grade ( C to + C) G Restricted hazardous substance device Y PH BE -pin, -mil SOJ (SO-) -pin TSOP Type II (SO-2) Ball Grid Array 2 2 Speed in nanoseconds S L Standard Power Low Power Y Y die stepping drw a.2

9 IDTVYS, IDTVYL.V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) Datasheet Document History Rev Date Page Description 2// p. - Released Automotive datasheet CORPORATE HEADQUARTERS for SALES: for Tech Support: 2 Silver Creek Valley Road -5- or ipchelp@idt.com San Jose, CA fax: The IDT logo is a registered trademark of Integrated Device Technology, Inc..2 9