AN2663 Application note

Transcription

1 Application note How to migrate from M29W128FH/L to M29W128GH/L Flash memories Introduction The objective of this application note is to explain how to migrate an application based on the M29W128FH/L Flash memory to an M29W128GH/L Flash memory. The purpose of this document is not to provide detailed information on the devices, but to highlight the similarities and differences between them. The comparison takes into consideration the signal descriptions, packages, architecture, software command set, performance, and block protections. The M29W128FH/L and M29W128GH/L are 128 Mbit (8 Mb x 16 or 16 Mb x 8) Flash memories that can be read, erased and reprogrammed using a single low supply voltage. Both memories are divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. and Erase commands are written to the command interface of the memory. An onchip /Erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. Group of blocks can be protected to prevent accidental or Erase commands from modifying the memory. On both devices, the highest or lowest memory block can also be protected by using a hardware method. All devices have an extra block, the extended block, of 128 words (256 bytes). It can be accessed using a dedicated command. The extended block can be protected and so is useful for storing security information. However the protection is not reversible, once protected the protection cannot be undone. In this document, the M29W128FH (highest block protected) and M29W128FL (lowest block protected) will be referred to as M29W128F, and the M29W128GH (highest block protected) and the M29W128GL (lowest block protected) will be referred to as M29W128G unless otherwise specified. Please refer to the M29W128F and M29W128G datasheets for additional information on devices. January 2008 Rev 2 1/25

2 Contents AN2663 Contents 1 Memory architecture and protection groups Hardware migration Signal description Packages Software command set Fast commands operation fails detection Device codes and auto select codes Performance and characteristics Access time Page Read mode and Erase times Block protection Temporary block unprotect Extended memory block Conclusion Revision history /25

3 List of tables List of tables Table 1. Signal description for the M29W128F devices Table 2. Signal description for the M29W128G devices Table 3. M29W128G, Enhanced Buffered commands (16-bit mode) Table 4. M29W128G, Fast commands (16-bit mode) Table 5. M29W128G, Fast commands (8-bit mode) Table 6. M29W128F, Fast commands, 16-bit mode Table 7. M29W128F, Fast commands, 8-bit mode Table 8. Root part number and device code Table 9. M29W128F, extended memory block protection - 8-bit mode Table 10. M29W128F, extended memory block protection - 16-bit mode Table 11. M29W128G, extended memory block protection - 8-bit mode Table 12. M29W128G, extended memory block protection - 16-bit mode Table 13. M29W128G, and Erase times Table 14. M29W128F, and Erase times Table 15. Document revision history /25

4 List of figures AN2663 List of figures Figure 1. M29W128F TSOP56 connections Figure 2. M29W128G TSOP56 connections Figure 3. M29W128F TBGA64 connections Figure 4. M29W128G TBGA64 connections /25

5 Memory architecture and protection groups 1 Memory architecture and protection groups The M29W128F and the M29W128G memory arrays are divided into uniform blocks. The M29W128F features 256 blocks of 32 Kwords (64 Kbytes) each, while the M29W128G has 128 blocks of 64 Kwords (128 Kbytes) each. Both devices have an extended memory block of 128 words in x 16 mode or x 256 bytes in x 8 mode. See Section 3: Software command set for a description of the extended memory block commands. Another difference between the M29W128F and the M29W128G is protection groups: On the M29W128F, the 8 outermost blocks (first 4 blocks and last 4 blocks) are protected individually. All the other blocks are grouped by four. On the M29W128G, all blocks are protected individually. The protection granularity is always 64 Kwords or 128 Kbytes on the M29W128G. 5/25

6 Hardware migration AN Hardware migration This section provides a detailed comparison between M29W128F and M29W128G signals and package pin-out. 2.1 Signal description Table 1 and Table 2 give a comparison between the M29W128F and M29W128G signals. The devices are compatible except for the V CCQ signal and a few slight differences in the V PP /WP signal. On both devices, the V PP function allows the memory to use an external high voltage power supply to reduce the time required for Fast operations. The Write Protect (WP) function provides a hardware method of protecting the outermost memory block: When (V PP /WP) is Low, V IL, the highest or lowest block is protected on both the M29W128G and M29W128F devices. In M29W128F, program and erase operations in this block are ignored while V PP /WP is Low, even when RESET (RP) is at V ID (temporary unprotection). When V PP /WP is High, V IH, the memory reverts to the previous protection status of the outermost block. On the M29W128F devices, applying 12 V to the V PP /WP pin will temporarily unprotect any block previously protected (including the two outermost blocks). On the M29W128G devices this functionality is available upon customer request. In addition, the V PP /WP pin must not be left floating or unconnected on the M29W128F, whereas M29W128G V PP /WP is High, V IH, when unconnected, due to an internal pull-up. In the M29W128G devices, V CCQ provides the power supply to the I/O pins and enable all outputs to be powered independently from V CC. This is an added feature which is not present in the M29W128F devices. However, the M29W128G devices are compatible with all the applications using the M29W128F devices even if they feature the V CC supply voltage only. 6/25

7 Hardware migration Table 1. Signal description for the M29W128F devices Name Description Direction A0-A22 Address inputs Inputs DQ0-DQ7 Data inputs/outputs I/O DQ8-DQ14 Data inputs/outputs I/O DQ15A 1 Data input/output or address input I/O E Chip Enable Input G Output Enable Input W Write Enable Input RP Reset/Block temporary unprotect Input RB Ready/Busy output Output BYTE Byte/word organization select Input V CC Supply voltage Supply V PP /WP V PP /Write Protect Input V SS Ground - Not connected internally - Table 2. Signal description for the M29W128G devices Name Description Direction A0-A22 Address inputs Inputs DQ0-DQ7 Data inputs/outputs I/O DQ8-DQ14 Data inputs/outputs I/O DQ15A 1 Data input/output or address input I/O E Chip Enable Input G Output Enable Input W Write Enable Input RP Reset Input RB Ready/Busy output Output BYTE Byte/word organization select Input V CCQ Input/output buffer supply voltage Supply V CC Supply voltage Supply V PP /WP (1) V PP /Write Protect Input V SS Ground - Not connected - 1. VPP/WP may be left floating as it is internally connected to a pull-up resistor which enables program/erase operations. 7/25

8 Hardware migration AN Packages The M29W128F and M29W128G are delivered in TSOP56-14 x 20 mm, and TBGA64-10 x 13 mm, 1 mm pitch packages. The M29W128G is fully pin-to-pin compatible with the M29W128F (the vice versa is not true due to the V CCQ pin). See Figure 1 and Figure 2, in conjunction with Table 1 and Table 2. Refer to the M29W128F and M29W128G datasheets for details on the packages. Figure 1. M29W128F TSOP56 connections Figure 2. M29W128G TSOP56 connections A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP A21 VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A M29W128FH M29W128FL A16 BYTE V SS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 V CC A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP A21 VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A M29W128GH M29W128GL A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 VCCQ AI11526 AI13331b 8/25

9 Hardware migration Figure 3. M29W128F TBGA64 connections A A3 A7 RB W A9 A13 B A4 A17 V PP /WP RP A8 A12 A22 C A2 A6 A18 A21 A10 A14 D A1 A5 A20 A19 A11 A15 V CC E A0 DQ0 DQ2 DQ5 DQ7 A16 V SS F V CC E DQ8 DQ10 DQ12 DQ14 BYTE G G DQ9 DQ11 V CC DQ13 DQ15 A-1 H V SS DQ1 DQ3 DQ4 DQ6 V SS AI /25

10 Hardware migration AN2663 Figure 4. M29W128G TBGA64 connections A A3 A7 RB W A9 A13 B A4 A17 V PP /WP RP A8 A12 A22 C A2 A6 A18 A21 A10 A14 D A1 A5 A20 A19 A11 A15 V CCQ E A0 DQ0 DQ2 DQ5 DQ7 A16 V SS F V CCQ E DQ8 DQ10 DQ12 DQ14 BYTE G G DQ9 DQ11 V CC DQ13 DQ15 A-1 H V SS DQ1 DQ3 DQ4 DQ6 V SS AI11527c 10/25

11 Software command set 3 Software command set The M29W128F and M29W128G feature an identical set of standard commands. The commands are compliant with the JEDEC standard. 3.1 Fast commands The M29W128F and the M29W128G devices both feature Fast commands. The Enhanced Buffered command is only available on M29W128G devices. It is valid in x 16 mode only and makes use of the device s 256-word write buffer to speed up programming. To use the Enhanced Buffered command, all the 256 words must be loaded into the write buffer in an increasing address order. Each write buffer has the same A22-A8 addresses. The Enhanced Buffered command dramatically reduces system programming time. Double, Quadruple, and Octuple Byte, Double and Quadruple Word commands are only available on M29W128F devices. In M29W128G devices it is recommended to use Enhanced Buffered and Write to Buffer commands to reach the best programming speed. In addition, the M29W128G devices feature a full set of Unlock Bypass commands (see Table 3, Table 4, Table 5, Table 6, and Table 7). Table 3. M29W128G, Enhanced Buffered commands (16-bit mode) Command Length Bus Write operations 1st 2nd 3rd 4th th 258th 259th 260th Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Enhanced Buffered AA 2AA 55 BAd 33 BAd (00) Data BAd (FF) Data Enhanced Buffered Confirm 1 BAd (00) 29 Unlock Bypass Enhanced Buffered 257 BAd 33 BAd (00) Data BAd (FF) Data 11/25

12 Software command set AN2663 Table 4. M29W128G, Fast commands (16-bit mode) Bus Write operations (1) Command Length 1st 2nd 3rd 4th 5th 6th Add Data Add Data Add Data Add Data Add Data Add Data Write to Buffer N AA 2AA 55 BAd 25 BAd N (2) PA (3) PD WBL (4) PD Write to Buffer Confirm 1 BAd (5) 29 Buffered Abort and Reset AA 2AA F0 Unlock Bypass AA 2AA Unlock Bypass Unlock Bypass Block Erase Unlock Bypass Chip Erase Unlock Bypass Write to Buffer Unlock Bypass Reset 2 X A0 PA PD 2+ X 80 BAd 30 2 X 80 X 10 N+3 BAd 25 BAd N (2) PA (3) PD 2 X 90 X 00 WBL (6) PD 1. X Don t care, PA Address, PD Data, BAd Any address in the Block, WBL Write Buffer Location. All values in the table are in hexadecimal. 2. The maximum number of cycles in the command sequence is 36. N+1 is the number of words to be programmed during the Write to Buffer operation. 3. Each buffer has the same A22-A5 addresses. A0-A4 are used to select a word within the N+1 word page. 4. The 6th cycle has to be issued N time. WBL scans the word inside the page. 5. BAd must be identical to the address loaded during the Write to Buffer 3rd and 4th cycles. 12/25

13 Software command set Table 5. Command M29W128G, Fast commands (8-bit mode) Length Bus Write operations (1) 1st 2nd 3rd 4th 5th 6th 7th 8th 9th Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Write to Buffer N+5 AAA AA BAd 25 BAd N (2) PA (3) PD WBL (4) PD Write to Buffer Confirm 1 BAd (5) 29 Buffered Abort and Reset Unlock Bypass Unlock Bypass Unlock Bypass Block Erase Unlock Bypass Chip Erase Unlock Bypass Write to Buffer Unlock Bypass Reset 3 AAA AA AAA F0 3 AAA AA AAA 20 2 X A0 PA PD 2+ X 80 BAd 30 2 X 80 X 10 N+3 BAd 25 BAd N (2) PA (3) PD WBL (6) PD 2 X 90 X X Don t care, PA Address, PD Data, BAd Any address in the Block, WBL Write Buffer Location. All values in the table are in hexadecimal. 2. The maximum number of cycles in the command sequence is 68. N+1 is the number of bytes to be programmed during the Write to Buffer operation. 3. Each buffer has the same A22-A5 addresses. A0-A4 and A-1 are used to select a byte within the N+1 byte page. 4. The 6th cycle has to be issued N time. WBL scans the word inside the page. 5. BAd must be identical to the address loaded during the Write to Buffer 3rd and 4th cycles. 6. The 4th cycle has to be issued N time. WBL scans the word inside the page. 13/25

14 Software command set AN2663 Table 6. M29W128F, Fast commands, 16-bit mode Bus Write operations (1) Command Length 1st 2nd 3rd 4th 5th 6th Add Data Add Data Add Data Add Data Add Data Add Data Write to Buffer and Write to Buffer and Abort and Reset Write to Buffer and Confirm N AA 2AA 55 BA 25 BA N (2) PA (3) PD AA 2AA F0 1 BA (5) 29 WBL (4) PD Double Word PA0 PD0 PA1 PD1 Quadruple Word PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 Unlock Bypass AA 2AA Unlock Bypass 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X X Don t care, PA Address, PD Data, BA Any address in the Block, WBL Write Buffer Location. All values in the table are in hexadecimal. 2. The maximum number of cycles in the command sequence is 36. N+1 is the number of words to be programmed during the Write to Buffer and operation. 3. Each buffer has the same A22-A5 addresses. A0-A4 are used to select a word within the N+1 word page. 4. The 6th cycle has to be issued N time. WBL scans the word inside the page. 5. BA must be identical to the address loaded during the Write to buffer and 3rd and 4th cycles. 14/25

15 Software command set Table 7. Command Length M29W128F, Fast commands, 8-bit mode Bus Write operations (1) 1st 2nd 3rd 4th 5th 6th 7th 8th 9th Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Write to Buffer and N+ 5 AAA AA BA 25 BA N (2) PA (3) PD WBL (4) PD Write to Buffer and Abort and Reset Write to Buffer and Confirm Double Byte Quadruple Byte Octuple Byte Unlock Bypass Unlock Bypass Unlock Bypass Reset 3 AAA AA AAA F0 1 BA (5) 29 3 AAA 50 PA0 PD0 PA1 PD1 5 AAA 56 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 9 AAA 8B PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7 3 AAA AA AAA 20 2 X A0 PA PD 2 X 90 X X Don t care, PA Address, PD Data, BA Any address in the Block, WBL Write Buffer Location. All values in the table are in hexadecimal. 2. The maximum number of cycles in the command sequence is 68. N+1 is the number of bytes to be programmed during the Write to Buffer and operation. 3. Each buffer has the same A22-A5 addresses. A0-A4 and A-1 are used to select a byte within the N+1 byte page. 4. The 6th cycle has to be issued N time. WBL scans the word inside the page. 5. BA must be identical to the address loaded during the Write to buffer and 3rd and 4th cycles. 15/25

16 Software command set AN operation fails detection In M29W128G devices, it is possible to detect operation fails, even during a Write to Buffer or Enhanced Buffered, when changing programmed data from 0 to 1, that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous value and the current value. In M29W128F devices, this functionality is not available for the Write to Buffer command. 3.3 Device codes and auto select codes The auto select codes are composed of the manufacturer code, the device code, the block protection status, and the extended memory block verify code. The M29W128F and M29W128G devices have the same manufacturer code but different device code and extended memory block verify code (please refer totable 8, Table 9, Table 10, Table 11, and Table 12). The M29W128F and M29W128G devices use identical commands and address inputs to read the auto select codes. Table 8. Root part number and device code Root part number M29W128FH M29W128FL M29W128GH M29W128GL Device code 227Eh h + 228Ah 227Eh h + 228Bh 227Eh h h 227Eh h h 16/25

17 Software command set Table 9. M29W128F, extended memory block protection - 8-bit mode Operation (1) E G W RP V PP/ WP A22 - A12 A11- A10 A9 A8- A7 Address inputs A6 A5 - A4 DQ A3- A2 A1 A0 15A -1 Data inputs/outputs DQ14 -DQ8 DQ7-DQ0 Verify extended memory block protection indicator (bit DQ7) Verify block protection status Temporary block unprotect (2) V IL V IL V IH V IH V IH BA X V ID X V IL X V IL V IH V IH V IL X Hi-Z M29W128F 88h (factory locked) 08h (customer lockable) M29W128G 98h (factory locked) 18h (customer lockable) 01h (protected) 00h (unprotected) X X X V ID X Valid Data input 1. X = V IL or V IH. BA any Address in the block. 2. The RP pin unprotects all the blocks that have been previously protected using a high voltage protection technique. 17/25

18 Software command set AN2663 Table 10. Operation (1) M29W128F, extended memory block protection - 16-bit mode E G W RP V PP /WP A22 - A12 A11 - A10 A9 Address inputs A8- A7 A6 A5- A4 A3-A2 A1 A0 Data inputs/outputs DQ15A-1, DQ14-DQ0 Verify extended memory block indicator (bit DQ7) V IL V IL V IH V IH V IH BA X V ID X V IL X V IL V IH Verify block protection status Temporary block unprotect (2) 1. X = V IL or V IH. BA Any Address in the block. 2. The RP pin unprotects all the blocks that have been previously protected using a high voltage protection technique. V IH V IL M29W128F 0088h (factory locked) 0008h (customer lockable) M29W128G 0098h (factory locked) 0018h (customer lockable) 0001h (protected) 0000h (unprotected) X X X V ID X Valid Data input Table 11. M29W128G, extended memory block protection - 8-bit mode Address inputs Data inputs/outputs Operation (1) E G W A22- A16 A14- A10 A9 A8- A7 A6 A5- A4 A3- A2 A1 A0 DQ15 A-1 DQ14 -DQ8 DQ7-DQ0 Verify extended memory block protection indicator (bit DQ7) M29W128GL M29W128GH V IL V IL V IH X X V ID (2) X V IL X V IL V IH V IH X X 89h (factory locked) 09h (customer lockable) 99h (factory locked) 19h (customer lockable) Verify block protection status BAd V IL (protected) 00h 01h (unprotected) 1. X = V IL or V IH. BAd any address in the block. 2. When using the in-system method, applying V ID to A9 is not required. A9 can be either V IL or V IH. 18/25

19 Software command set Table 12. M29W128G, extended memory block protection - 16-bit mode Address inputs Data inputs/outputs Operation (1) E G W A22- A16 A14- A10 A9 A8- A7 A6 A5- A4 A3- A2 A1 A0 DQ15A-1, DQ14-DQ0 Verify extended memory block indicator (bit DQ7) M29W128GL M29W128GH V IL V IL V IH X X V ID (2) X V IL X V IL V IH V IH 0089h (factory locked) 0009h (customer lockable) 0099h (factory locked) 0019h (customer lockable) Verify block protection status BAd V IL 0001h (protected) 0000h (unprotected) 1. X = V IL or V IH. BAd any address in the block. 2. When using the in-system method, applying V ID to A9 is not required. A9 can be either V IL or V IH. 19/25

20 Performance and characteristics AN Performance and characteristics The M29W128F and the M29W128G have almost compatible DC and AC characteristics (see the respective datasheets for details). The differences lie in access times, fast programming times, and supply voltages. 4.1 Access time The M29W128G has a random access time of 70 ns or 90 ns, depending on the V CCQ supply voltage, whereas the M29W128F has an access time of 60 or 70 ns. 4.2 Page Read mode The Page mode is available on the M29W128F and M29W128G to speed up read operations. The data is internally read and stored in a 8-word (or 16-byte) page buffer. Using Page read, the access time for subsequent read operations is reduced to 25 ns for both devices with V CCQ =V CC, while it is reduced to 30 ns for the M29W128G with V CCQ =1.65V. 20/25

21 Performance and characteristics 4.3 and Erase times The time required to program or erase the whole memory is lower on the M29W128G compared to the M29W128F. The memory can be either programmed using a Fast or an Enhanced Buffered command (see Section 3.1), or using the word by word program command. Refer to Section 3.1 for details on Fast commands. Table 13. M29W128G, and Erase times Parameter Min Typ (1)(2) Max (2) Unit Chip Erase (3) s Block Erase (64 Kbytes) (4) 0.5 s Erase Suspend latency time 5 50 µs Block Erase time-out 50 µs Byte Word Single Byte 16 Write to Buffer (64 bytes at-a-time) V PP /WP =V PPH 51 V PP /WP =V IH 78 Single Word 16 Write to Buffer (32 words at-a-time) V PP /WP =V PPH 51 V PP /WP =V IH (3) µs µs 200 (3) µs Chip (byte by byte) (3) s Chip (word by word) (3) s Chip (Write to Buffer ) (5) (3) s Chip (Write to Buffer with V PP /WP =V PPH ) (5) (3) s Chip (Enhanced Buffered ) (5) 8 40 s Chip (Enhanced Buffered with V PP /WP =V PP ) (5) 5 25 s Suspend latency time 5 15 µs /Erase cycles (per block) 100,000 cycles Data retention 20 years 1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested. 3. Maximum value measured at worst case conditions for both temperature and V CC after 100,000 program/erase cycles. 4. Block Erase Polling cycle time (see Figure 23: Data polling AC waveforms in the M29W128G datasheet). 5. Intrinsic program timing, that means without the time required to execute the bus cycles to load the program commands. µs 21/25

22 Performance and characteristics AN2663 Table 14. M29W128F, and Erase times Parameter Min Typ (1)(2) Max (2) Unit Chip Erase (3) s Block Erase (64 Kbytes) (4) s Erase Suspend latency time 50 (4) µs Single or Multiple Byte (1, 2, 4 or 8 bytes at-a-time) 10 µs Byte Word Write to Buffer and (64 bytes at-atime) V PP /WP =V PPH 90 V PP /WP =V IH 280 Single or Multiple Word (1, 2 or 4 words at-a-time) 10 Write to Buffer V PP /WP =V PPH 90 and (32 words at-atime) V PP /WP =V IH (3) 200 (3) Chip (byte by byte) (3) s Chip (word by word) (3) s Chip (Quadruple Byte or Double Word) (3) s Chip (Octuple Byte or Quadruple Word) (3) s Suspend latency time 5 15 µs /Erase cycles (per block) 100,000 cycles Data retention 20 years 1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested. 3. Maximum value measured at worst case conditions for both temperature and V CC after 100,000 program/erase cycles. 4. Maximum value measured at worst case conditions for both temperature and V CC. µs µs µs 22/25

23 Block protection 5 Block protection In M29W128F, there are three techniques that can be used to control block protection, these are the programmer technique, the in-system technique and temporary unprotection. In M29W128G, there are three more sophisticated software protections, such as volatile protection, non-volatile protection, and password protection (please refer to the M29W128G datasheet for details). The M29W128F and M29W128G both feature hardware protection. In particular, the V PP /WP pin protects the highest block of the M29W128FH and M29W128GH (01 model), and the lowest block of the M29W128FL and M29W128GL (02 model). 5.1 Temporary block unprotect In the M29W128F, when held at V ID, the Reset/Block Temporary Unprotect pin, RP, will temporarily unprotect all the blocks previously protected using a high voltage block protection technique. In the M29W128G, this functionality is available upon customer request. 6 Extended memory block The M29W128F and M29W128G devices both have a 128-word / 256-byte extended memory block. In the M29W128F this block can be either completely factory locked or completely customer lockable. In the M29W128G, a half block (64 words) is factory locked and the other half (64 words) is customer lockable. 7 Conclusion Applications can be easily migrated from an M29W128F to an M29W128G Flash memory. Despite not being a full replacement of the M29W128F, the M29W128G features better performance in terms of programming / erasing time and block protection. The main differences lie in block size, protection granularity and protection features. 23/25

24 Revision history AN Revision history Table 15. Document revision history Date Version Changes 26-Nov Initial release. 03-Jan Applied Numonyx branding. 24/25

25 Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS ILUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved. 25/25