LY62L205016A 32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM

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Randall Thompson
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1 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Sep Rev. 1.1 Add 25 & 40 spec for ISB1 & IDR on page 4 & page 9 Delete grade for ordering information on page 11 Correct typo error on the column UB#, B# of truth table for row Byte Read Byte Write and Output Disable at page 4: revised to be Nov July yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

2 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM FEATURES GENERA DESCRIPTION Fast access time : 55/70ns ow power consumption: Operating current : 45/30mA (TYP.) Standby current : 10μA (TYP.) S-version Single 2.7V ~ 3.6V power supply All inputs and outputs TT compatible Fully static operation Tri-state output Data byte control : (i) BYTE# fixed to V CC B# controlled DQ0 ~ DQ7 UB# controlled DQ8 ~ DQ15 (ii) BYTE# fixed to V SS DQ15 used as address pin, while DQ8~DQ14 pins not used Data retention voltage : 1.2V (MIN.) Green package available Package : 48-pin 12mm x 20mm TSOP-I The Y A is a 33,554,432-bit low power CMOS static random access memory organized as 2,097,152 words by 16 bits or 4,194,304 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The Y A is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The Y A operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TT compatible PRODUCT FAMIY Product Operating Power Dissipation Vcc Range Speed Family Temperature Standby(ISB1,TYP.) Operating(Icc,TYP.) Y A 0 ~ ~ 3.6V 55/70ns 10µA(S) 45/30mA Y A(I) -40 ~ ~ 3.6V 55/70ns 10µA(S) 45/30mA yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

3 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM FUNCTIONA BOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0~A20 /A-1~A20 DQ0-DQ7 ower Byte DQ8-DQ15 Upper Byte DECODER I/O DATA CIRCUIT 2048Kx16/4096Kx8 MEMORY ARRAY COUMN I/O SYMBO DESCRIPTION A0 A20 Address Inputs(word mode) A-1 A20 Address Inputs(byte mode) DQ0 DQ15 Data Inputs/Outputs, Chip Enable Input WE# Write Enable Input OE# Output Enable Input B# ower Byte Control UB# Upper Byte Control BYTE# Byte Enable VCC VSS Power Supply Ground WE# OE# B# UB# BYTE# CONTRO CIRCUIT yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

4 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM PIN CONFIGURATION A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# NC UB# B# A18 A17 A7 A6 A5 A4 A3 A2 A Y A A16 BYTE# Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss A0 TSOP-I ABSOUTE MAIMUN RATINGS* PARAMETER SYMBO RATING UNIT Voltage on VCC relative to VSS VT1-0.5 to 4.6 V Voltage on any other pin relative to VSS VT2-0.5 to VCC+0.5 V Operating Temperature TA 0 to 70(C grade) -40 to 85(I grade) Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W DC Output Current IOUT 50 ma *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

5 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM TRUT TABE MODE BYTE# OE# WE# B# UB# Standby Output Disable Read Write I/O OPERATION DQ0-DQ7 DQ8-DQ14 DQ15 igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z D OUT igh Z D OUT D IN igh Z D IN yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA: igh Z igh Z igh Z igh Z D OUT D OUT igh Z D IN D IN igh Z igh Z A-1 igh Z D OUT D OUT igh Z D IN D IN SUPPY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 Byte# Read Dout igh Z A-1 ICC,ICC1 Byte # Write Din igh Z A-1 ICC,ICC1 Note: = VI, = VI, = Don't care. DC EECTRICA CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. *4 MA. UNIT Supply Voltage VCC V Input igh Voltage VI * VCC+0.3 V Input ow Voltage VI * V Input eakage Current II VCC VIN VSS µa Output eakage VCC VOUT VSS Current IO Output Disabled µa Output igh Voltage VO IO = -1mA V Output ow Voltage VO IO = 2mA V ICC Cycle time = Min. = VI and = VI ma II/O = 0mA Other pins at VI or VI ma Average Operating Power supply Current Standby Power Supply Current ICC1 ISB ISB1 Cycle time = 1µs 0.2V and VCC-0.2V II/O = 0mA Other pins at 0.2V or VCC-0.2V = VI or = VI Other pins at VI or VI VCC-0.2V or 0.2V Other pins at 0.2V or VCC-0.2V - S - SI ma ma µa µa -S µa -SI µa Notes: 1. VI(max) = VCC + 2.0V for pulse width less than 6ns. 2. VI(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25

6 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM CAPACITANCE (TA = 25, f = 1.0Mz) PARAMETER SYMBO MIN. MA UNIT Input Capacitance CIN - 6 pf Input/Output Capacitance CI/O - 8 pf Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse evels 0.2V to VCC -0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference evels 1.5V Output oad C = 30pF + 1TT, IO/IO = -1mA/2mA AC EECTRICA CARACTERISTICS (1) READ CYCE PARAMETER SYM. Y A-55 Y A-70 UNIT MIN. MA. MIN. MA. Read Cycle Time trc ns Address Access Time taa ns Chip Enable Access Time tace ns Output Enable Access Time toe ns Chip Enable to Output in ow-z tcz* ns Output Enable to Output in ow-z toz* ns Chip Disable to Output in igh-z tcz* ns Output Disable to Output in igh-z toz* ns Output old from Address Change to ns B#, UB# Access Time tba ns B#, UB# to igh-z Output tbz* ns B#, UB# to ow-z Output tbz* ns (2) WRITE CYCE PARAMETER SYM. Y A-55 Y A-70 UNIT MIN. MA. MIN. MA. Write Cycle Time twc ns Address Valid to End of Write taw ns Chip Enable to End of Write tcw ns Address Set-up Time tas ns Write Pulse Width twp ns Write Recovery Time twr ns Data to Write Time Overlap tdw ns Data old from End of Write Time td ns Output Active from End of Write tow* ns Write to Output in igh-z twz* ns B#, UB# Valid to End of Write tbw ns *These parameters are guaranteed by device characterization, but not production tested. yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

7 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM TIMING WAVEFORMS READ CYCE 1 (Address Controlled) (1,2) Address trc taa to Dout Previous Data Valid Data Valid READ CYCE 2 ( and and OE# Controlled) (1,3,4,5) Address trc taa tace B#,UB# tba OE# tbz tcz toz toe to toz tbz tcz Dout igh-z Data Valid igh-z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, = low, = high, B# or UB# = low. 3.Address must be valid prior to or coincident with = low, = high, B# or UB# = low transition; otherwise taa is the limiting parameter. 4.tCZ, tbz, toz, tcz, tbz and toz are specified with C = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tcz is less than tcz, tbz is less than tbz, toz is less than toz. yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

8 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM WRITE CYCE 1 (WE# Controlled) (1,2,3,5,6) twc Address taw tcw tbw B#,UB# tas twp twr WE# twz TOW Dout (4) igh-z (4) tdw td Din Data Valid WRITE CYCE 2 ( and Controlled) (1,2,5,6) Address twc taw tas twr tcw tbw B#,UB# twp WE# Dout twz (4) igh-z tdw td Din Data Valid yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

9 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM WRITE CYCE 3 (B#,UB# Controlled) (1,2,5,6) twc Address taw twr tas tcw tbw B#,UB# twp WE# Dout (4) twz igh-z tdw td Din Data Valid Notes : 1.WE#,, B#, UB# must be high or must be low during all address transitions. 2.A write occurs during the overlap of a low, high, low WE#, B# or UB# = low. 3.During a WE# controlled write cycle with OE# low, twp must be greater than twz + tdw to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the, B#, UB# low transition and high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and twz are specified with C = 5pF. Transition is measured ±500mV from steady state. yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

10 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM DATA RETENTION CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. MA. UNIT VCC for Data Retention VDR VCC - 0.2V or 0.2V V Data Retention Current IDR -S µa VCC = 1.2V -SI µa VCC-0.2V or 0.2V -S other pins at 0.2V or VCC-0.2V µa -SI µa Chip Disable to Data See Data Retention tcdr Retention Time Waveforms (below) ns Recovery Time tr trc * - - ns trc * = Read Cycle Time DATA RETENTION WAVEFORM ow Vcc Data Retention Waveform (1) ( controlled) VDR 1.2V Vcc Vcc(min.) Vcc(min.) tcdr tr VI Vcc-0.2V VI ow Vcc Data Retention Waveform (2) ( controlled) VDR 1.2V Vcc Vcc(min.) Vcc(min.) tcdr tr VI 0.2V VI ow Vcc Data Retention Waveform (3) (B#, UB# controlled) VDR 1.2V Vcc Vcc(min.) Vcc(min.) tcdr tr B#,UB# VI B#,UB# Vcc-0.2V VI yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

Y62205016A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM PACKAGE OUTINE DIMENSION 48-pin 12mm x 20mm TSOP-I Package Outline Dimension yontek Inc.

11 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM PACKAGE OUTINE DIMENSION 48-pin 12mm x 20mm TSOP-I Package Outline Dimension yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

12 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM ORDERING INFORMATION Package Type 48-pin 12mm x 20mm TSOP-I Access Time (Speed)(ns) Power Type 55 Special Ultra ow Power 70 Special Ultra ow Power Temperature Range( ) Packing Type yontek Item No. 0 ~70 Tray Y A-55S Tape Reel Y A-55ST -40 ~85 Tray Y A-55SI Tape Reel Y A-55SIT 0 ~70 Tray Y A-70S Tape Reel Y A-70ST -40 ~85 Tray Y A-70SI Tape Reel Y A-70SIT yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

13 Y A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM TIS PAGE IS EFT BANK INTENTIONAY. yontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. I, Science-Based Industrial Park, sinchu 300, Taiwan. TE: FA:

LY62L102516A 1024K x 16 BIT LOW POWER CMOS SRAM

LY62L102516A 1024K x 16 BIT LOW POWER CMOS SRAM Y62102516A 1024K x 16 BIT OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jan. 09. 2012 Rev. 1.1 Deleted WRITE CYCE Notes : 1.WE#,, B#, UB# must be high or must