4Mb Async. FAST SRAM Specification

Size: px
Start display at page:

Download "4Mb Async. FAST SRAM Specification"

Transcription

1 S6R4008V1M, S6R4016V1M, S6R4008C1M S6R4016C1M 4Mb Async. FAST SRAM Specification INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO NETSOL PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN NETSOL PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Netsol products, contact your nearest Netsol office. 2. Netsol products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Netsol reserves the right to change products or specification without notice

2 Document Title 256Kx16 & 512Kx8 Bit Asynchronous FAST SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial Draft Oct Advanced 0.1 Revise ICC, ISB, ISB1 and IDR value Mar Preliminary 1.0 Final spec release Jul Final Revise ICC, ISB, ISB1 and IDR value - 2 -

3 256Kx16 & 512Kx8 Bit Asynchronous FAST SRAM Features Fast Access Time 10ns CMOS Low Power Dissipation Standby (TTL) : 35mA (Max.) (CMOS) : 28mA (Max.) Operating : 80mA (Max.) Single 3.3 ±0.3V or 5.0 ±0.5V Power Supply - S6R40xxV1M : 3.3 ±0.3V Power Supply - S6R40xxC1M : 5.0 ±0.5V Power Supply TTL Compatible Inputs and Outputs Fully Static Operation, No Clock or Refresh required Three State Outputs Data Byte Control(x16 Mode) LB : I/O0~ I/O7, UB : I/O8~ I/O15 Standard 44 TSOP2 Package Pin Configuration Operating in Commercial and Industrial Temperature range. General Description The S6R4016V(C)1M and S6R4008V(C)1M are a 4,194,304- bit high-speed Static Random Access Memory organized as 256K (512K) words by 16(8) bits. The S6R4016V(C)1M (S6R40 08V(C)1M) uses 16(8) common input and output lines and have an output enable pin which operates faster than address access time at read cycle. And S6R4016V(C)1M allows that lower and upper byte access by data byte control(ub, LB). The device is fabricated using advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The S6R4016V1M and S6R4008V1M are packaged in a 400mil 44-pin TSOP(II). Both S6R4016V(C)1M and S6R4008V(C)1M products use common input and output lines, and have output enable pin which operates faster than address access time at read cycle. Also S6R4016V1M allows the byte access for the products having 16 bits. These are particularly well suited for designs needed high flexibility of wide density, organization and power supply. The devices are fabricated using advanced CMOS process, 6-TR based cell technology, and those are particularly well suited for use in extended temperature applications. 4Mb Asynchronous FAST SRAM Ordering Information Density Org. VDD (V) taa(ns) Speed t(ns) Part Number Package TEMP 4Mb 256Kx16 512Kx S6R4016V1M-UC(I)10 44 TSOP2 C : Commercial Temperature S6R4016C1M-UC(I)10 44 TSOP2 I : Industrial Temperature S6R4008V1M-UC(I)10 44 TSOP S6R4008C1M-UC(I)10 44 TSOP2-3 -

4 Logic Block Diagram - S6R4016V(C)1M (256K x 16) CLK Gen. Pre-Charge Circuit A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Row Decoder 256K X 16 Memory Array I/O0~I/O7 I/O8~I/O15 Data Cont. Data Cont. Gen. CLK I/O Circuit & Column Decoder A10 A11 A12 A13 A14 A15 A16 A17 UB LB 44 TSOP2 Package Pin Configurations(Top View) - S6R4016V(C)1M (256K x 16) A0 A1 A2 A3 A4 I/O0 I/O1 I/O2 I/O3 Vcc Vss I/O4 I/O5 I/O6 I/O7 A5 A6 A7 A8 A TSOP A17 A16 A15 UB LB I/O15 I/O14 I/O13 I/O12 Vss Vcc I/O11 I/O10 I/O9 I/O8 N.C A14 A13 A12 A11 A10 Pin Function Pin Name A0 - A17 LB UB I/O0 ~ I/O15 VCC VSS N.C Pin Function Address Inputs Write Enable Chip Select Output Enable Lower-byte Control(I/O0~I/O7) Upper-byte Control(I/O8~I/O15) Data Inputs/Outputs Power(+3.3V or +5.0V) Ground No Connection - 4 -

5 Logic Block Diagram - S6R4008V(C)1M (512K x 8) CLK Gen. Pre-Charge Circuit A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Row Decoder 512K X 8 Memory Array I/O0~I/O7 Data Cont. I/O Circuit & Column Decoder CLK Gen. A10 A11 A12 A13 A14 A15 A16 A17 A18 44 TSOP2 Package Pin Configurations(Top View) - S6R4008V(C)1M (512K x 8) A0 A1 A2 A3 A4 I/O0 I/O1 Vcc Vss I/O2 I/O3 A5 A6 A7 A8 A A18 A17 A16 A15 I/O7 44 TSOP2 35 I/O6 34 Vss Pin Function 33 Vcc Pin Name 32 I/O5 31 I/O4 A0 - A A14 A13 A12 27 A11 26 A10 I/O0 ~ I/O VCC VSS N.C Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+3.3V or +5.0V) Ground No Connection - 5 -

6 Absolute Maximum Ratings* Voltage on Any Pin Relative to VSS Voltage on Vcc Supply Relative to VSS Parameter Symbol Rating Unit 3.3V Product VIN, VOUT -0.5 to Vcc+0.5V 5.0V Product -0.5 to Vcc+0.5V 3.3V Product VIN, VOUT -0.5 to V Product -0.5 to 7.0 Power Dissipation PD 1.0 W Storage Temperature TSTG -65 to 150 C Operating Temperature Commercial TA 0 to 70 C Industrial TA -40 to 85 C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. V V Recommended DC Operating Conditions*(TA=0 to 70 C) Parameter Symbol Min Typ Max Unit Supply Voltage 3.3V Product VCC V 5.0V Product VCC Ground VSS V Input High Voltage 3.3V Product VIH VCC+0.3 V 5.0V Product VIH VCC+0.5 Input Low Voltage VIL -0.3** V * The above parameters are also guaranteed for industrial temperature range. DC and Operating Characteristics*(TA=0 to 70 C, Vcc=3.3±0.3V or 5.0±0.5V, unless otherwise specified) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current ILI VIN=VSS to VCC -2 2 µa Output Leakage Current ILO =VIH or =VIH or =VIL VOUT=VSS to VCC Operating Current** ICC Min. Cycle, 100% Duty =VIL, VIN=VIH or VIL, IOUT=0mA * The above parameters are also guaranteed for industrial temperature range. ** The operating current parameters can be changed in the final spec µa Com. 10ns - 80 ma Ind. 10ns - 80 Standby Current ISB Min. Cycle, =VIH - 35 ma ISB1 f=0mhz, VCC-0.2V, VIN VCC-0.2V or VIN 0.2V - 28 Output Low Voltage Level VOL IOL=8mA V Output High Voltage Level VOH IOH=-4mA V Capacitance*(TA=25 C, f=1.0mhz) Item Symbol Test Conditions TYP Max Unit Input/Output Capacitance CI/O VI/O=0V - 8 pf Input Capacitance CIN VIN=0V - 6 pf * Capacitance is sampled and not 100% tested

7 Test Conditions* Parameter Value Input Pulse Level 0 to 3.0V Input Rise and Fall Time 3ns Input and Output Timing Reference Levels 1.5V Output Load See Fig. 1 * The above parameters are also guaranteed at industrial temperature range. Output Load(A) Output Load(B) (for thz, tlz, twhz, tolz & tohz) Dout Zo=50Ω RL=50Ω 30pF* VL=1.5V Dout +3.3V for 3.3V I/O +5.0V for 5.0V I/O 319/480Ω 353/255Ω 5pF* * Including Scope and Jig Capacitance Fig. 1 Overshoot Timing Undershoot Timing VDD+1.0V VDD+0.5V VDD 20% trc,twc(min) VIH VSS VSS-0.5V VIL VSS-1.0V 20% trc,twc(min) Fig. 2 Functional Description (x8 Mode) Mode I/O Pin Supply Current H X X* Not Select ISB, ISB1 L H H Output Disable ICC L H L Read DOUT ICC L L X Write DIN ICC * X means Don t Care

8 Functional Description (x16 Mode) LB** UB** Mode I/O0~I/O7 I/O Pin I/O8~I/O15 Supply Current H X X* X X Not Select ISB, ISB1 L H H X X Output Disable ICC L X X H H L H DOUT L H L H L Read DOUT ICC L L X * X means Don t Care. L L DOUT DOUT L H DIN H L Write DIN L L DIN DIN ICC Data Retention Characteristics*(TA=0 to 70 C) Parameter Symbol Test Condition Min. Typ. Max. Unit VCC for Data Retention VDR VCC - 0.2V /5.5 V Data Retention Current IDR VCC=2.0V, VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V * The above parameters are also guaranteed at industrial temperature range ma Data Retention Set-Up Time tsdr See Data Retention ns Recovery Time trdr Wave form(below) ms Data Retention Wave Form controlled VCC tsdr Data Retention Mode trdr 3.0V VIH VDR GND VCC - 0.2V - 8 -

9 Read Cycle* Parameter Symbol Min Max Unit Read Cycle Time trc 10 - ns Address Access Time taa - 10 ns Chip Select to Output tco - 10 ns Output Enable to Valid Output t - 5 ns UB, LB Access Time ** tba - 5 ns Chip Enable to Low-Z Output tlz 3 - ns Output Enable to Low-Z Output tolz 0 - ns UB, LB Enable to Low-Z Output ** tblz 0 - ns Chip Disable to Output thz 0 5 ns Output Disable to Output tohz 0 5 ns UB, LB Disable to Output ** tbhz 0 5 ns Output Hold from Address Change toh 3 - ns Chip Selection to Power Up Time tpu 0 - ns Chip Selection to Power DownTime tpd - 10 ns * The above parameters are also guaranteed for industrial temperature range. Write Cycle* Parameter Symbol Min Max Unit Write Cycle Time twc 10 - ns Chip Select to End of Write tcw 7 - ns Address Set-up Time tas 0 - ns Address Valid to End of Write taw 7 - ns Write Pulse Width( High) twp 7 - ns Write Pulse Width( Low) twp ns UB, LB Valid to End of Write ** tbw 7 - ns Write Recovery Time twr 0 - ns Write to Output twhz 0 5 ns Data to Write Time Overlap tdw 5 - ns Data Hold from Write Time tdh 0 - ns End of Write to Output Low-Z tow 3 - ns * The above parameters are also guaranteed for industrial temperature range

10 Timing Diagrams Timing Waveform Of Read Cycle(1) (Address Controlled, ==VIL, =VIH, UB, LB=VIL **) Address trc toh Data Out Previous Valid Data Valid Data taa Timing Waveform Of Read Cycle(2) (=VIH) Address trc UB, LB** taa tco tba thz(3,4,5) tbhz(3,4,5) tblz(4,5) t tohz Data out tolz tlz(4,5) Valid Data toh VCC Current ICC ISB tpu 50% tpd 50% NOTES(Read Cycle) 1. is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. thz and tohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with =VIL. 7. Address valid prior to coincident with transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle

11 Timing Waveform Of Write Cycle(1) ( Clock) Address twc taw twr(5) tcw(3) tbw UB, LB** tas(4) twp(2) tdw tdh Data in Valid Data tohz(6) Data out Timing Waveform Of Write Cycle(2) (=Low fixed) Address twc taw tcw(3) tbw twr(5) UB, LB** tas(4) twp1(2) Data in Data out tdw Valid Data tdh twhz(6) tow (10) (9)

12 Timing Waveform Of Write Cycle(3) (=Controlled) twc Address taw twr(5) tcw(3) tbw UB, LB** tas(4) twp(2) Data in tdw Valid Data tdh Data out tlz twhz(6) (8) Timing Waveform Of Write Cycle(4) (UB, LB Controlled) twc Address taw tcw(3) twr(5) tbw UB, LB** tas(4) twp(2) Data in tdw Valid Data tdh Data out tblz twhz(6) (8) NOTES(Write Cycle) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low,,lb and UB. A write begins at the latest transition going low and going low ; A write ends at the earliest transition going high or going high. twp is measured from the beginning of write to the end of write. 3. tcw is measured from the later of going low to end of write. 4. tas is measured from the address valid to the beginning of write. 5. twr is measured from the end of write to the address change. twr applied in case a write ends as or going high. 6. If, and are in the Read Mode during this period, the I/O pins are in the output low-z state. Inputs of opposite phase of the output must not. be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If goes low simultaneously with going or after going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied

13 Package Dimensions 44-TSOP2-400BF #44 # TYP Units:millimeters/Inches 0~ ~ ~ ± ± ( 0.50 ) #1 # Max ± ± ( ) ± ± Min Max Max

4Mb Async. FAST SRAM A-die Specification

4Mb Async. FAST SRAM A-die Specification S6R4008V1A, S6R4016V1A, S6R4008C1A, S6R4016C1A, S6R4008W1A S6R4016W1A 4Mb Async. FAST SRAM A-die Specification NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.

More information

16Mb(1M x 16 bit) Low Power SRAM

16Mb(1M x 16 bit) Low Power SRAM 16Mb(1M x 16 bit) Low Power SRAM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING

More information

CMOS SRAM. K6T4008C1B Family. Document Title. Revision History. 512Kx8 bit Low Power CMOS Static RAM. Revision No. History. Remark. Draft Date 0.

CMOS SRAM. K6T4008C1B Family. Document Title. Revision History. 512Kx8 bit Low Power CMOS Static RAM. Revision No. History. Remark. Draft Date 0. Document Title 512Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft December 7, 1996 Advance 0.1 Revise - Changed Operating current by reticle

More information

LP621024E-I Series 128K X 8 BIT CMOS SRAM. Document Title 128K X 8 BIT CMOS SRAM. Revision History. AMIC Technology, Corp.

LP621024E-I Series 128K X 8 BIT CMOS SRAM. Document Title 128K X 8 BIT CMOS SRAM. Revision History. AMIC Technology, Corp. 128K X 8 BIT CMOS SRAM Document Title 128K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue January 14, 2008 Preliminary 1.0 Final version release September 21, 2010

More information

AS6C K X 8 BIT LOW POWER CMOS SRAM

AS6C K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Description Issue Date Rev. 1.0 Rev. 1.1 Initial Issue Add package 48-ball 8mm 10mm TFBGA Revised ORDERING INFORMATION in page 11 Jan.09.2012 July.12.2013 0 FEATURES Fast access

More information

256K x 16 4Mb Asynchronous SRAM

256K x 16 4Mb Asynchronous SRAM FP-BGA Commercial Temp Industrial Temp 256K x 16 4Mb Asynchronous SRAM GS74117AX 8, 10, 12 ns 3.3 V V DD Center V DD and V SS Features Fast access time: 8, 10, 12 ns CMOS low power operation: 130/105/95

More information

64K x 16 1Mb Asynchronous SRAM

64K x 16 1Mb Asynchronous SRAM TSOP, FP-BGA Commercial Temp Industrial Temp 64K x 16 1Mb Asynchronous SRAM GS71116AGP/U 7, 8, 10, 12 ns 3.3 V V DD Center V DD and V SS Features Fast access time: 7, 8, 10, 12 ns CMOS low power operation:

More information

IDT71016S/NS. CMOS Static RAM 1 Meg (64K x 16-Bit)

IDT71016S/NS. CMOS Static RAM 1 Meg (64K x 16-Bit) CMOS Static RAM 1 Meg (4K x 1-Bit) IDT711S/NS Features 4K x 1 advanced high-speed CMOS Static RAM Equal access and cycle times Commercial and Industrial: //2 One Chip Select plus one Output Enable pin

More information

LP62S16256G-I Series. Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM. Revision History. Rev. No. History Issue Date Remark

LP62S16256G-I Series. Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM. Revision History. Rev. No. History Issue Date Remark Preliminary 256K X 16 BIT LOW VOLTAGE CMOS SRAM ocument Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue ate Remark 0.0 Initial issue June 2, 2006 Preliminary PRELIMINARY

More information

3.3V CMOS Static RAM for Automotive Applications 4 Meg (256K x 16-Bit)

3.3V CMOS Static RAM for Automotive Applications 4 Meg (256K x 16-Bit) .V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) IDTVYS IDTVYL Features 25K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. Equal access and cycle

More information

8K X 8 BIT LOW POWER CMOS SRAM

8K X 8 BIT LOW POWER CMOS SRAM February 2007 FEATURES Access time :55ns Low power consumption: Operation current : 15mA (TYP.), VCC = 3.0V Standby current : 1µ A (TYP.), VCC = 3.0V Wide range power supply : 2.7 ~ 5.5V Fully Compatible

More information

CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout

CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout CMOS Static RAM 1 Meg (K x -Bit) Revolutionary Pinout IDT714 Features K x advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/gnd) for reduced noise Equal access and cycle times

More information

AS6C6264 8K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY. Feb

AS6C6264 8K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY. Feb REVISION HISTORY Revision Description Issue Date 1.0 Initial issue Feb 2007 2.0 Add-in industrial temperature option for 28-pin 600 July 2017 mil PDIP. Standby current(isb1) reduced to be 20uA for I-grade

More information

IDT71V124SA/HSA. 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout

IDT71V124SA/HSA. 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout 33V CMOS Static RAM 1 Meg (K x -Bit) Center Power & Ground Pinout IDT71VSA/HSA Features K x advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/gnd) for reduced noise Equal access

More information

MOS INTEGRATED CIRCUIT

MOS INTEGRATED CIRCUIT DATA SHEET 4M-BIT CMOS STATIC RAM 256K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION MOS INTEGRATED CIRCUIT µpd444012a-x Description The µpd444012a-x is a high speed, low power, 4,194,304 bits (262,144

More information

AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM

AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.12.2012 Rev. 1.1 V CC - 0.2V revised as 0.2V for TEST CONDITION Jul.19.2012 of Average Operating Power supply Current Icc1 on

More information

512K x 8 4Mb Asynchronous SRAM

512K x 8 4Mb Asynchronous SRAM SOJ, TSOP, FP-BGA Commercial Temp Industrial Temp 512K x 8 4Mb Asynchronous SRAM GS74108ATP/J/X 8, 10, 12 ns 3.3 V V DD Center V DD and V SS Features Fast access time: 8, 10, 12 ns CMOS low power operation:

More information

LY62W K X 16 BIT LOW POWER CMOS SRAM

LY62W K X 16 BIT LOW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Initial Issue Jul.13.2011 0 FEATURES Fast access time : 55/70ns ow power consumption: Operating current : 45/30mA (TYP.) Standby current : 10A (TYP.) -version

More information

LY61L102416A 1024K X 16 BIT HIGH SPEED CMOS SRAM

LY61L102416A 1024K X 16 BIT HIGH SPEED CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issued Jan.09. 2012 Rev. 1.1 Add 48 pin BGA package type. Mar.12. 2012 Rev. 1.2 1. VCC - 0.2V revised as 0.2 for TEST July.19. 2012 CONDITION

More information

LY62L102516A 1024K x 16 BIT LOW POWER CMOS SRAM

LY62L102516A 1024K x 16 BIT LOW POWER CMOS SRAM Y62102516A 1024K x 16 BIT OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jan. 09. 2012 Rev. 1.1 Deleted WRITE CYCE Notes : 1.WE#,, B#, UB# must be high or must

More information

AS6C TINL 16M Bits LOW POWER CMOS SRAM

AS6C TINL 16M Bits LOW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Initial Issue Jan. 09. 2012 0 FEATURES Fast access time : 55ns ow power consumption: Operating current : 45mA (TYP.) Standby current : 4 A (TYP.) S-version

More information

Rev. No. History Issue Date Remark

Rev. No. History Issue Date Remark 128K X 8 BIT LOW VOLTAGE CMOS SRAM ocument Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue ate Remark 0.0 Initial issue February 19, 2002 Preliminary 0.1 Add 32L Pb-Free

More information

LY62L K X 16 BIT LOW POWER CMOS SRAM

LY62L K X 16 BIT LOW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.25.2004 Rev. 1.1 Revised Package Outline Dimension(TSOP-II) Apr.12.2007 Rev. 1.2 Added ISB1/IDR values when TA = 25 and TA = 40

More information

LY62L205016A 32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM

LY62L205016A 32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM Y62205016A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Sep.06.2012 Rev. 1.1 Add 25 & 40 spec for ISB1 & IDR on page 4 &

More information

LY62L409716A 4M X 16 BIT LOW POWER CMOS SRAM

LY62L409716A 4M X 16 BIT LOW POWER CMOS SRAM Y62409716A 4M 16 BIT OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jun.08.2017 yontek Inc. reserves the rights to change the specifications and products without

More information

LY62L K X 16 BIT LOW POWER CMOS SRAM

LY62L K X 16 BIT LOW POWER CMOS SRAM Y6225716 256K 16 BIT OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Apr.19.2006 Rev. 2.0 Revised ISB(max) : 0.5mA => 1.25mA May.11.2006 Rev. 2.1 Adding 44-pin

More information

IS62WV12816DALL/DBLL IS65WV12816DALL/DBLL

IS62WV12816DALL/DBLL IS65WV12816DALL/DBLL IS62WV12816DALL/DBLL IS65WV12816DALL/DBLL 128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JUNE 2013 FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation 36 mw (typical) operating

More information

MOS INTEGRATED CIRCUIT

MOS INTEGRATED CIRCUIT DATA SHEET 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT MOS INTEGRATED CIRCUIT µpd43256b Description The µpd43256b is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. Battery

More information

FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 1 of 13

FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 1 of 13 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM FEATURES Fast access time : 55ns ow power consumption: Operating current : 20/18mA (TYP.) Standby current : 2µA (TYP.) Single 2.7V ~ 5.5V power

More information

Rev. No. History Issue Date Remark

Rev. No. History Issue Date Remark Preliminary 512K X 8 OTP CMOS EPROM Document Title 512K X 8 OTP CMOS EPROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 17, 1998 Preliminary 1.0 Change CE from VIL to VIH

More information

AT28C16. 16K (2K x 8) CMOS E 2 PROM. Features. Description. Pin Configurations

AT28C16. 16K (2K x 8) CMOS E 2 PROM. Features. Description. Pin Configurations Features Fast Read Access Time - 150 ns Fast Byte Write - 200 µs or 1 ms Self-Timed Byte Write Cycle Internal Address and Data Latches Internal Control Timer Automatic Clear Before Write Direct Microprocessor

More information

MOS INTEGRATED CIRCUIT

MOS INTEGRATED CIRCUIT DATA SHEET 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT MOS INTEGRATED CIRCUIT μpd43256b Description The μpd43256b is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. Battery

More information

MB85R K (32 K 8) Bit. Memory FRAM DS E CMOS DESCRIPTIONS FEATURES PACKAGES FUJITSU SEMICONDUCTOR DATA SHEET

MB85R K (32 K 8) Bit. Memory FRAM DS E CMOS DESCRIPTIONS FEATURES PACKAGES FUJITSU SEMICONDUCTOR DATA SHEET FUJITSU SEMICONDUCTOR DATA SHEET DS05-13101-4E Memory FRAM CMOS 256 K (32 K 8) Bit MB85R256 DESCRIPTIONS The MB85R256 is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768 words

More information

2-Megabit (256K x 8) 5-volt Only CMOS Flash Memory AT29C020. Features. Description. Pin Configurations

2-Megabit (256K x 8) 5-volt Only CMOS Flash Memory AT29C020. Features. Description. Pin Configurations Features Fast Read Access Time - 90 ns 5-Volt-Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (256 bytes/sector) Internal Address and Data Latches for

More information

IDT7134SA/LA. HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM

IDT7134SA/LA. HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM Features High-speed access : 5/45//7 (max.) Industrial: / (max.) Commercial: 2//5/45//7 (max.) Low-power operation IDT714 Active: 7mW (typ.) Standby: 5mW (typ.) IDT714 Active: 7mW (typ.) Standby: 1mW (typ.)

More information

MB85R M Bit (128 K 8) Memory FRAM CMOS DS E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET

MB85R M Bit (128 K 8) Memory FRAM CMOS DS E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET FUJITSU SEMICONDUCTOR DATA SHEET DS05-13103-5E Memory FRAM CMOS 1 M Bit (128 K 8) MB85R1001 DESCRIPTIONS The MB85R1001 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 131,072 words x

More information

128Kx8 CMOS MONOLITHIC EEPROM SMD

128Kx8 CMOS MONOLITHIC EEPROM SMD 128Kx8 CMOS MONOLITHIC EEPROM SMD 5962-96796 WME128K8-XXX FEATURES Read Access Times of 125, 140, 150, 200, 250, 300ns JEDEC Approved Packages 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300) 32 lead,

More information

AT29C K (32K x 8) 5-volt Only CMOS Flash Memory. Features. Description. Pin Configurations

AT29C K (32K x 8) 5-volt Only CMOS Flash Memory. Features. Description. Pin Configurations Features Fast Read Access Time - 70 ns 5-Volt-Only Reprogramming Page Program Operation Single Cycle Reprogram (Erase and Program) Internal Address and Data Latches for 64-Bytes Internal Program Control

More information

A23W8308. Document Title 262,144 X 8 BIT CMOS MASK ROM. Revision History. Rev. No. History Issue Date Remark

A23W8308. Document Title 262,144 X 8 BIT CMOS MASK ROM. Revision History. Rev. No. History Issue Date Remark Preliminary 262,144 X 8 BIT CMOS MASK ROM Document Title 262,144 X 8 BIT CMOS MASK ROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 11, 1999 Preliminary PRELIMINARY (November,

More information

Low Power Pseudo SRAM

Low Power Pseudo SRAM Revision History Rev. No. History Issue Date 1.0 1. New Release. 2. Product Process change from 90nm to 65nm 3. The device build in Power Saving mode as below : 3-1. Deep Power Down (DPD) 3-2. Partial

More information

White Electronic Designs

White Electronic Designs White Electronic Desig 512Kx8 STATIC RAM CMOS, MODULE FEATURES 512Kx8 bit CMOS Static Random Access Memory Access Times 2 through 1 Data Retention Function (EDI8F8512LP) TTL Compatible Inputs and Outputs

More information

White Electronic Designs

White Electronic Designs 256Kx32 Static RM CMOS, High Speed Module FETURES 256Kx32 bit CMOS Static Random ccess Memory ccess Times: 12, 15, 20, and 25ns Individual Byte Selects Fully Static, No Clocks TTL Compatible I/O High Density

More information

AT28C K (32K x 8) Paged CMOS E 2 PROM. Features. Description. Pin Configurations

AT28C K (32K x 8) Paged CMOS E 2 PROM. Features. Description. Pin Configurations AT28C256 Features Fast Read Access Time - 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64-Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms

More information

HM628128BI Series. 131,072-word 8-bit High speed CMOS Static RAM

HM628128BI Series. 131,072-word 8-bit High speed CMOS Static RAM 131,072-word 8-bit High speed CMOS Static RAM ADE-203-363A(Z) Rev. 1.0 Apr. 28, 1995 The Hitachi HM628128BI is a CMOS static RAM organized 131,072-word 8-bit. It realizes higher density, higher performance

More information

EDI8G322048C DESCRIPTION FEATURES PIN CONFIGURATION PIN NAMES

EDI8G322048C DESCRIPTION FEATURES PIN CONFIGURATION PIN NAMES 2048K x 32 Static RM CMOS, High Speed Module FETURES n 2048K x 32 bit CMOS Static n Random ccess Memory ccess Times: 20, 25, and 35ns Individual Byte Selects Fully Static, No Clocks TTL Compatible I/O

More information

LY68L M Bits Serial Pseudo-SRAM with SPI and QPI

LY68L M Bits Serial Pseudo-SRAM with SPI and QPI REVISION HISTORY Revision Description Issue Date Rev. 0.1 Initial Issued May.6. 2016 Rev. 0.2 Revised typos May.19. 2016 Revised the address bit length from 32 bits to 24 bits Oct.13. 2016 0 FEATURES GENERAL

More information

K1C6416B2D Document Title 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory 2 Revision History Revision No. History Draft Date Remark 0.

K1C6416B2D Document Title 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory 2 Revision History Revision No. History Draft Date Remark 0. 64Mb (4M x 16 bit) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

More information

512KX8 CMOS S-RAM (Monolithic)

512KX8 CMOS S-RAM (Monolithic) 512KX8 CMOS S-RAM (Monolithic) Features Access Times: 55, 70, 85 and 100ns Package Option: 32-Pin Ceramic DIP, JEDEC Approved Pinout 36-Lead Ceramic SOJ JEDEC Approved Revolutionary Pinout 32-Lead Ceramic

More information

W956D6KBKX. 64Mb Async./Burst/Sync./A/D MUX

W956D6KBKX. 64Mb Async./Burst/Sync./A/D MUX 64Mb Async./Burst/Sync./A/D MUX TABLE OF CONTENTS 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. ORDERING INFORMATION... 3 4. BALL CONFIGURATION... 4 5. BALL DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7.

More information

ACT S512K32 High Speed 16 Megabit SRAM Multichip Module

ACT S512K32 High Speed 16 Megabit SRAM Multichip Module ACT S512K32 High Speed 16 Megabit SRAM Multichip Module Features 4 Low Power CMOS 512K x 8 SRAMs in one MCM Factory configured as 512K x 32; User configurable as 1M x 16 or 2M x 8 Input and Output TTL

More information

HIGH SPEED 128K (8K X 16 BIT) IDT70825S/L SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM )

HIGH SPEED 128K (8K X 16 BIT) IDT70825S/L SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM ) HIGH SPEED 18K (8K X 16 BIT) SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM ) Features High-speed access Commercial: ///4 (max.) Low-power operation IDT78S Active: 77mW (typ.) Standby: mw (typ.) IDT78L

More information

512Kx8 Monolithic SRAM, SMD

512Kx8 Monolithic SRAM, SMD 512Kx Monolithic SRAM, SMD 5962-956 FEATURES Access Times of,, 2,, 35, 45, 55 Data Retention Function (LPA version) TTL Compatible Inputs and Outputs Fully Static, No Clocks Organized as 512Kx Commercial,

More information

16Mbit, 512KX32 CMOS S-RAM MODULE

16Mbit, 512KX32 CMOS S-RAM MODULE 16Mbit, 512KX32 CMOS S-RAM MODULE Features Access Times: 25, 35 and 45ns Package Options: 66-Pin Ceramic PGA 1.385" SQ 66-Pin Ceramic PGA 1.173" SQ 68-Lead Ceramic QFP 0.88" SQ Fit & Function JEDEC 68-CQFP

More information

IS62/65WVS1288FALL IS62/65WVS1288FBLL. 128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE DESCRIPTION

IS62/65WVS1288FALL IS62/65WVS1288FBLL. 128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE DESCRIPTION 128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE JANUARY 2018 KEY FEATURES SPI-Compatible Bus Interface: - 16/20 MHz Clock rate - SPI/SDI/SQI mode Low-Power CMOS Technology: - Read Current:

More information

HIGH-SPEED 4K x 8 FourPort TM STATIC RAM

HIGH-SPEED 4K x 8 FourPort TM STATIC RAM Features High-speed access Commercial: // (max.) Industrial: (max.) ow-power operation IDT754 Active: 75mW (typ.) tandby: 7.5mW (typ.) IDT754 Active: 75mW (typ.) tandby: mw (typ.) True FourPort memory

More information

IS62/65WVS1288GALL IS62/65WVS1288GBLL. 128Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE KEY FEATURES DESCRIPTION MAY 2018

IS62/65WVS1288GALL IS62/65WVS1288GBLL. 128Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE KEY FEATURES DESCRIPTION MAY 2018 128Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE MAY 2018 KEY FEATURES SPI-Compatible Bus Interface: - 30/45 MHz Clock rate - SPI/SDI/SQI mode Single Power Supply: - VDD = 1.65V - 2.2V

More information

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,024 X 9, 2,048 X 9, 4,096 x 9 and 8,192 x 9

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,024 X 9, 2,048 X 9, 4,096 x 9 and 8,192 x 9 Integrated Device Technology, Inc. CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,24 X 9, 2,48 X 9, 4,96 x 9 and 8,192 x 9 IDT72421 IDT7221 IDT72211 IDT72221 IDT72231 IDT72241 IDT72251 FEATURES: 64 x 9-bit

More information

AT24C01A/02/04/08/16. 2-Wire Serial CMOS E 2 PROM. Features. Description. Pin Configurations. 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8)

AT24C01A/02/04/08/16. 2-Wire Serial CMOS E 2 PROM. Features. Description. Pin Configurations. 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8) AT24C01A/02/04/08/16 Features Low Voltage and Standard Voltage Operation 5.0 (V CC = 4.5V to 5.5V) 2.7 (V CC = 2.7V to 5.5V) 2.5 (V CC = 2.5V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Internally Organized 128

More information

White Electronic Designs

White Electronic Designs 12Kx32 EEPROM MODULE, SMD 5962-9455 FEATURES Access Times of 120**, 140, 150, 200, 250, 300ns Packaging: 66-pin, PGA Type, 27.3mm (1.075") square, Hermetic Ceramic HIP (Package 400) 6 lead, 22.4mm sq.

More information

4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Rev. No. History Issue Date Remark

4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Rev. No. History Issue Date Remark 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue July 23, 2003 1.0 Remove 24/26-pin

More information

IS62/65WVS5128GALL IS62/65WVS5128GBLL. 512Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE KEY FEATURES DESCRIPTION

IS62/65WVS5128GALL IS62/65WVS5128GBLL. 512Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE KEY FEATURES DESCRIPTION 512Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE JUNE 2018 KEY FEATURES SPI-Compatible Bus Interface: - 30/45 MHz Clock rate - SPI/SDI/SQI mode Single Power Supply: - VDD = 1.65V -

More information

W957D6HB. 128Mb Async./Burst/Sync./A/D MUX

W957D6HB. 128Mb Async./Burst/Sync./A/D MUX 28Mb Async./Burst/Sync./A/D MUX TABLE OF CONTENTS. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. ORDERING INFORMATION... 3 4. PIN CONFIGURATION... 4 4. Ball Assignment... 4 5. PIN DESCRIPTION... 5 5. Signal

More information

16Mbit, 512KX32 CMOS S-RAM MODULE

16Mbit, 512KX32 CMOS S-RAM MODULE 16Mbit, 512KX32 CMOS S-RAM MODULE Features Access Times: 17 and 20ns Package Options: 66-Pin Ceramic PGA 1.080" SQ 66-Pin Ceramic PGA 1.173" SQ 68-Lead Ceramic QFP 0.88" SQ Fit & Function JEDEC 68-CQFJ

More information

Product Change Notification (PCN)

Product Change Notification (PCN) Product Change Notification (PCN) Alliance Memory Inc. 511 Taylor Way, Suite 1, San Carlos, CA 94070 Main +1(650)610-6800 FAX +1(650)620-9211 Date: June 1, 2017 PCN TRACKING NO:PCN-29052017-01 Subject:

More information

IS41C16257C IS41LV16257C

IS41C16257C IS41LV16257C 256Kx16 4Mb DRAM WITH FAST PAGE MODE JANUARY 2013 FEATURES TTL compatible inputs and outputs; tri-state I/O Refresh Interval: 512 cycles/8 ms Refresh Mode: -Only, CAS-before- (CBR), and Hidden JEDEC standard

More information

CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240

More information

My-MS. MM27C ,072 x 8 CMOS EPROM PRELIMINARY INFORMATION ISSI IS27C010 FEATURES DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

My-MS. MM27C ,072 x 8 CMOS EPROM PRELIMINARY INFORMATION ISSI IS27C010 FEATURES DESCRIPTION FUNCTIONAL BLOCK DIAGRAM IS27C010 ISSI MM27C010 131,072 x CMOS EPROM PRELIMINARY INFORMATION FEATURES Fast read access time: 90 ns JEDEC-approved pinout High-speed write programming Typically less than 16 seconds 5V ±10% power

More information

64Mbit, 2MX32 3V Flash Memory Module

64Mbit, 2MX32 3V Flash Memory Module 64Mbit, 2MX32 3V Flash Memory Module Features 3.0V ± 10% read and write operation 1,000,000 Block Erase Cycles Access Times: 70,90,120 &150ns 4X(32 Equal Sectors of 64-Kbyte Each) Package Options: Individual

More information

VERY LOW POWER 1.8V 16K/8K/4K x 16 DUAL-PORT STATIC RAM

VERY LOW POWER 1.8V 16K/8K/4K x 16 DUAL-PORT STATIC RAM VERY LOW POWER 1.8V 16K/8K/4K x 16 DUAL-PORT STATIC RAM IDT70P264/254/244L DATASHEET Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access

More information

M Rev: /10

M Rev: /10 www.centon.com MEMORY SPECIFICATIONS 16,777,216 words x 64Bit Synchronous Dynamic RAM Memory Module (Unbuffered DIMM) Centon's 128MB Memory Module is 16,777,216 words by 64Bit Synchronous Dynamic RAM Memory

More information

WINTEC I. DESCRIPTION: III. TIMING

WINTEC I. DESCRIPTION: III. TIMING ISIONS ZONE DESCRIPTION APPVD 1/26/01 NR I. DESCRIPTION: III. TIMING is a 8Mx64 industry standard 8-pin PC-100 DIMM Manufactured with 4 8Mx 400-mil TSOPII-54 100MHz Synchronous DRAM devices Requires 3.3V+/-0.3V

More information

4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Rev. No. History Issue Date Remark

4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Rev. No. History Issue Date Remark 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 13, 2001 Preliminary 0.1

More information

MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION

MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION FEATURES 32K x 8 organization Single +5V power supply +125V programming voltage Fast access time: 45/55/70/90/100/120/150 ns Totally static operation Completely TTL compatible 256K-BIT [32K x 8] CMOS EPROM

More information

MARCH/2008, V 1.0 Alliance Memory Inc. Page 1 of 12

MARCH/2008, V 1.0 Alliance Memory Inc. Page 1 of 12 January MAR 2008 2007 AS64016 256K 16 BIT SUPER 512K OW POWER 8BITMOS OW SRAM POWER MOS SRAM FEATURES Fast access time : 55ns ow power consumption: Operating current :30mA (TYP.) Standby current : 4 A

More information

512K bitstwo-wire Serial EEPROM

512K bitstwo-wire Serial EEPROM General Description The provides 524,288 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 65,536 words of 8 bits each. The device is optimized for use in many

More information

4Mbit, 512KX8 5V Flash Memory (Monolithic)

4Mbit, 512KX8 5V Flash Memory (Monolithic) 4Mbit, 512KX8 5V Flash Memory (Monolithic) Features 5V Programming, 5V±10% Supply TTL Compatible Inputs and CMOS Outputs Access Times: 90, 120 and 150ns Low Vcc Write Inhibit 3.2v 8 Equal Size Sectors

More information

A24C08. AiT Semiconductor Inc. ORDERING INFORMATION

A24C08. AiT Semiconductor Inc.   ORDERING INFORMATION DESCRIPTION The provides 8192 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 1024 words of 8 bits each. The device is optimized for use in many industrial

More information

Product Specification

Product Specification General Information 512MB 64Mx72 ECC SDRAM PC100/PC133 DIMM Description: The VL 374S6553 is a 64M x 72 Synchronous Dynamic RAM high density memory module. This memory module consists of eighteen CMOS 32Mx8

More information

ISSI IS25C02 IS25C04 2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM FEATURES DESCRIPTION. Advanced Information January 2005

ISSI IS25C02 IS25C04 2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM FEATURES DESCRIPTION. Advanced Information January 2005 2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM January 2005 FEATURES Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Low power CMOS Active current less than 3.0

More information

M0360. Rev: /08

M0360. Rev: /08 www.centon.com MEMORY SPECIFICATIONS 32MX8 BASED 33,554,432words x 72Bit Synchronous Dynamic RAM Memory Module (Unbuffered DIMM) Centon's 256MB ECC UNBUFFERED Memory Module is 33,554,432 words by 72Bit

More information

Am27C128. Advanced Micro Devices. 128 Kilobit (16,384 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL

Am27C128. Advanced Micro Devices. 128 Kilobit (16,384 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL FINAL 128 Kilobit (16,384 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 45 ns Low power consumption 20 µa typical CMOS standby current JEDEC-approved pinout Single

More information

High Performance 4Kx4 Static RAM MIL-STD-883C

High Performance 4Kx4 Static RAM MIL-STD-883C High Performance 4Kx4 Static RAM MIL-STD-883C FEATURES Full Military Temperature Operating Range (-55 0 C to + 125 0 C) MIL-STD-883C Processing 4Kx4 Bit Organisation 55 and 70 nsec-agce-ss-times Fully

More information

MB85R1002A. 1 M Bit (64 K 16) Memory FRAM CMOS. DS v01-E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET

MB85R1002A. 1 M Bit (64 K 16) Memory FRAM CMOS. DS v01-E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET FUJITSU SEMICONDUCTOR DATA SHEET DS501-00004-0v01-E Memory FRAM CMOS 1 M Bit (64 K 16) MB85R1002A DESCRIPTIONS The MB85R1002A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 65,536 words

More information

IDT7132SA/LA IDT7142SA/LA

IDT7132SA/LA IDT7142SA/LA HIGH SPEED 2K x 8 DUAL PORT STATIC RAM IDT7132/ IDT7142/ Features High-speed access Commercial: //35/55/1 (max.) Industrial: (max.) : /35/55/1 (max.) Low-power operation IDT7132/42 Active: 3mW (typ.) Standby:

More information

Industrial Temperature Range: -40 o C to +85 o C Lead-free available KEY TIMING PARAMETERS. Max. CAS Access Time (tcac) ns

Industrial Temperature Range: -40 o C to +85 o C Lead-free available KEY TIMING PARAMETERS. Max. CAS Access Time (tcac) ns 1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE APRIL 2005 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms Refresh Mode: -Only, CAS-before- (CBR), and Hidden

More information

IS41C16256C IS41LV16256C

IS41C16256C IS41LV16256C 256Kx16 4Mb DRAM WITH EDO PAGE MODE JANUARY 2013 FEATURES TTL compatible inputs and outputs; tri-state I/O Refresh Interval: 512 cycles/8 ms Refresh Mode : -Only, CAS-before- (CBR), and Hidden JEDEC standard

More information

1Mx16 16Mb DRAM WITH FAST PAGE MODE SEPTEMBER 2018

1Mx16 16Mb DRAM WITH FAST PAGE MODE SEPTEMBER 2018 1Mx16 16Mb DRAM WITH FAST PAGE MODE SEPTEMBER 2018 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms Refresh Mode: -Only, CAS-before- (CBR), and Hidden JEDEC

More information

Am27C512. Advanced Micro Devices. 512 Kilobit (65,536 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL

Am27C512. Advanced Micro Devices. 512 Kilobit (65,536 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL FINAL 512 Kilobit (65,536 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 55 ns Low power consumption 20 µa typical CMOS standby current JEDEC-approved pinout Single

More information

Am27C020. Advanced Micro Devices. 2 Megabit (262,144 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL

Am27C020. Advanced Micro Devices. 2 Megabit (262,144 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL FINAL 2 Megabit (262,144 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 70 ns Low power consumption 100 µa maximum CMOS standby current JEDEC-approved pinout Plug

More information

8Mb Async/Page PSRAM

8Mb Async/Page PSRAM 8Mb Async/Page PSRAM NOVEMBER 2015 Overview The IS66/67WVE51216EALL/BLL/CLL and IS66/67WVE51216TALL/BLL/CLL are integrated memory device containing 8Mbit Pseudo Static Random Access Memory using a self-refresh

More information

VSS VSS D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC VCC VSS VSS NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE BYTE A16 A15 A14 A13 A12 A11 A10 A19 VSS A21 A20

VSS VSS D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC VCC VSS VSS NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE BYTE A16 A15 A14 A13 A12 A11 A10 A19 VSS A21 A20 5 Volt 16-Mbit (2M x 8 / 1M x 16) Mask ROM FEATURES Bit organization - 2M x 8 (byte mode) - 1M x 16 (word mode) Fast access time - Random access: 100ns (max.) Current - Operating: 60mA - Standby: 50uA

More information

HIGH SPEED 4K X 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

HIGH SPEED 4K X 8 DUAL-PORT STATIC RAM WITH SEMAPHORE HIGH SPEED 4K X 8 DUAL-PORT STATIC RAM WITH SEMAPHORE IDT7142/ Features High-speed access Commercial: 2//5/45//7 (max.) Industrial: (max.) Low-power operation IDT7142 Active: 7mW (typ.) Standby: 5mW (typ.)

More information

AK6512CA SPI bus 64Kbit Serial CMOS EEPROM

AK6512CA SPI bus 64Kbit Serial CMOS EEPROM AK6512CA SPI bus 64Kbit Serial CMOS EEPROM Features Advanced CMOS EEPROM Technology Single Voltage Supply: 1.8V to 5.5V 64Kbits; 8192 x 8 organization SPI Serial Interface Compatible High Speed Operation

More information

A24C02. AiT Semiconductor Inc. ORDERING INFORMATION

A24C02. AiT Semiconductor Inc.   ORDERING INFORMATION DESCRIPTION provides 2048 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 256 words of 8 bits each. The device is optimized for use in many industrial and

More information

1.8V Core Async/Page PSRAM

1.8V Core Async/Page PSRAM 1.8V Core Async/Page PSRAM Overview The IS66WVE4M16ALL is an integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits.

More information

ISSI Preliminary Information January 2006

ISSI Preliminary Information January 2006 2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM January 2006 FEATURES Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Low-voltage Operation Vcc = 1.8V to 5.5V Low

More information

HyperDisk SOLID STATE DISK

HyperDisk SOLID STATE DISK SOLID STATE DISK NAND Flash-based 2.5 SATA Standard Type Product Data sheet Preliminary Mar 2008 Storage Tecnologies Ltd INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO HYPERDISK PRODUCTS, AND

More information

MB85R1001A. 1 M Bit (128 K 8) Memory FRAM CMOS. DS v01-E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET

MB85R1001A. 1 M Bit (128 K 8) Memory FRAM CMOS. DS v01-E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET FUJITSU SEMICONDUCTOR DATA SHEET DS501-00003-0v01-E Memory FRAM CMOS 1 M Bit (128 K 8) MB85R1001A DESCRIPTIONS The MB85R1001A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 131,072

More information

MOS INTEGRATED CIRCUIT

MOS INTEGRATED CIRCUIT DATA SHEET MOS INTEGRATED CIRCUIT µpd42s18165, 4218165 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The µpd42s18165, 4218165 are 1,048,576 words by 16 bits

More information

GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND

GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE DECEMBER 2006 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: Auto refresh Mode: 1,024 cycles /16 ms -Only, CAS-before- (CBR),

More information