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1 University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 1/11 Exam 2 Instructions: Turn off all cell phones, beepers and other noise making devices Show all work on the front of the test papers Box each answer If you need more room, make a clearly indicated note on the front of the page, "MORE ON BCK", and use the back The back of the page will not be graded without an indication on the front You may not use any notes, HW, labs, books, or calculators This exam counts for 20% of your total grade Read each question carefully and follow the instructions You must pledge and sign this page in order for a grade to be assigned The point values for problems may be changed at prof s discretion Truth tables and voltage tables must be in counting order Label the inputs and outputs of each circuit with activation-levels For each mixed-logic circuit design, equations must not be used as replacements for circuit elements Label inputs of each gate with the appropriate logic equations Boolean expression answers must be in lexical order,( ie, / before, before B, & D 3 before D 2 ) Good Evening! Welcome! Good luck & Go Gators!!! For K-maps, label each grouping with the appropriate equation Put your name at the top of this test page (and, if you remove the staple, all others) Be sure your exam consists of 11 distinct pages Sign your name and add the date below PLEDGE: On my honor as a University of Florida student, I certify that I have neither given nor received any aid on this examination, nor I have seen anyone else do so SIGN YOUR NME DTE (9 November 2011) Regrade comments below: Give page # and problem # and reason for the petition Page TOTL 100 vailable Points

2 University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 2/11 Exam 2 [15%] 1 Design a system that sequences through the following outputs: 5 10, 3 10, 7 10, 5 10, 3 10, 7 10, etc 2 min The system must asynchronously reset to output the 3 10 when Start (active-low) goes true When the sequence output is 7 10, the active-high output Z should be true Use a T- FF for the most significant bit of the design, a JK-FF for the least significant bit, and a D-FF for any other bits you might need Note: ll the given FFs have active-low asynchronous clear and set inputs Use the minimum number of flip-flops and then try to minimize the number of other SSI gates necessary to solve this problem (No ROMs allowed) 5 min a) Complete the next-state truth table You may not need all the rows and/or columns 5 min b) Find the required simplified (MSOP or MPOS) equations

3 University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 3/11 Exam 2 5 min 1 c) Design the complete circuit, minimizing the total number of components, but using the T-FF and JK-FF (and D-FF(s), if necessary) as described previously ll inputs and outputs of the circuit should be clearly indicated coming into or out of the below box Your design must include the circuitry necessary to asynchronous re-start the system at output 3 10 when the Start (active-low) signal goes true and show the active-high output Z when the output is 7 10 Inputs Outputs

4 University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page /11 Exam 2 [18%] 2 Design a 2-bit registered LU that 10 min performs the functions shown here to generate the 2-bit output (labeled Out 1-0 ) There are also three other 2-bit buses: In 1-0, 1-0, and B 1-0 Use only flip-flops and other non-memory SSI or MSI gates You can assume that a -bit full-adder is available [HINT: See problem 8] LU function selection S 1 S 0 ction 0 0 OR and B 0 1 Shift right 1-bit with sign extension 1 0 Sum and B and Cin ( Cout) 1 1 Shift B left 1-bit Registers and B should have the same capabilities, ie, input sources that you had in lab 6, ie, as described in the table shown here Input sources for Registers and B The design should be complete, ie, all of the SSI and MSI devices should be shown as they MS1/ MSB1 MS0/ MSB0 Bus Selected as Input to REG/REGB would in a Quartus schematic entry (bdf) file 0 0 In 1-0 ll inputs and outputs of the circuit should be clearly indicated coming into or out of 1 0 B 1-0 the below box 1 1 Out 1-0 Inputs Outputs

5 University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 5/11 Exam 2 [6%] 3 nswer the following questions about a state machine designed with one EEPROM, one J-K flip, one T flip-flop, and any other necessary flip-flops of type D (3%) a) What is the size of the EEPROM [addresses x data bits] if the state machine has 3 inputs, 2 min 2 outputs, and 3 states? Provide numbers only, ie, 37 9, NOT expressions like 3 7 (3%) b) What is the size of the EEPROM [addresses x data bits] if the state machine has 1 input, 3 outputs, and 7 states? Provide numbers only 2 min [5%] Draw a debounced switch circuit Do NOT draw a 5 min layout Label the output that can be used as a clock input Draw the switch in the position that makes low The only gates from ICs you can use are NOR gates Use only the necessary other components lso, draw a timing diagram of the output as the switch goes from the position drawn, to the opposite position and then back to the drawn position H L [5%] 5 Draw a complete circuit diagram including two min switch circuits, one for an active-low input signal, X(L) and one for an active-high input Y(H) These switch circuits are used for the inputs of a 2-input ND gate with bubbles at the inputs (ie, a BND gate) Draw the switches in the positions necessary to make the output of the gate, W(H), true Draw an LED circuit at the output of this gate Do NOT draw a layout What is the equation of the circuit that you have drawn?

6 University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 6/11 Exam 2 D Data Bits D 0 $0 $0 [22%] 6 Given as many 32x SRMs as needed and as many 32x8 EEPROMs as needed, design the 2 min memory module described below, with an active-low chip enable, CE The device should begin with 32x8 of SRM and then immediately follow with 6x8 of EEPROM The 32x8 of SRM must start at address $0 and the first address of the 6x8 of EEPROM must immediately follow the last SRM address dd the minimum number of memory devices and the minimum number of additional SSI components required (no MSI) ( %) a) Draw vertical and horizontal lines in the box below and label each resulting box with the 5 min memory type and size, using only the defined types and sizes given above lso, fill in the subscript on the D at the top left and the maximum address at the bottom right Increasing ddresses = max address ( %) b) What is the address and data ranges for each of the memory components drawn above (in binary and in hex)? 5 min 32x SRM(s): 32x8 EEPROM(s):

7 University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 7/11 Exam 2 ( %) 6 c) Design the required memory device circuit diagram below dd the minimum number 5 min of additional memory components and SSI gates necessary (no MSI gates or PLDs) dd address subscripts as needed and cross out unneeded address and data pins Use labels instead of wires for the design lso, write the equations for each CS Show all connections with either labels or wires (labels are preferred), just as in Quartus Don t forget the system s active-low chip enable, CE x RM WE CS D 0 D 1 D 2 D 3 32x 8 EEPROM D 0 D 1 D 2 D 3 D D 5 D 6 D 7 CS D 0 D 1 D 2 D 3 D D 5 D 6 D 7 D 8 D 9 D 10 D 11 CE(L) R/W

8 University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 8/11 Exam 2 ( %) 6 d) Design a circuit to add a 6x8 SRM to the memory module designed previously This 5 min single SRM s addresses should immediately follow the address of the last device of the previous design Draw the memory module from parts a-c as a single device, add the necessary 6x8 SRM, and add the connections and SSI components needed to complete the design dd address subscripts as needed and cross out unneeded address and data pins Use labels instead of wires for the design lso, write the equations for each CS or CE Show all connections with either labels or wires (labels are preferred), just as in Quartus Don t forget the system s active-low chip enable, CE CE(L) Memory for parts a-c D 0 D 1 D 2 D 3 D D 5 D 6 D 7 R/W CE 6x 8 SRM D 0 D 1 D 2 D 3 D D 5 D 6 D 7 WE CS D 0 D 1 D 2 D 3 D D 5 D 6 D 7 D 8 D 9 D 10 D 11 R/W

9 University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 9/11 Exam 2 [12%] 7 The following figure shows a simplified circuit diagram ssume that all of the 12 min inputs and outputs are active-high The ROM contents are given in the below table; note that the addresses are in octal [base 8] and the values in the table are in hex [base 16] (This problem is very similar to a problem in homework 8 that was also done in class) (10%) a) Derive the SM chart for this circuit Show LL work, ie, use at least part of the below blank table (Do not miss part b below) X Q1 Q x 5 ROM D3 D2 D1 D0 D D Q Q Q1 Q0 Y1 Y0 Contents of the ROM ddr Value Octal Hex E E (2%) b) ssume that an additional active-low output, Y 2, is needed (without changing the 2 min ROM) Y 2 is true only when Q1 and Q0 are both true Show all the changes in both the truth table and the SM (if any) Draw any additional circuitry required to accomplish this change

10 2 min INPUT Bus University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 10/11 Exam 2 REG Bus REGB Bus OUTPUT Bus MS1 MS0 REG Bus Cin MSC2:0 3 MUX s REG MUX B s REG B Combinatorial Logic MUX C s MSB1 MSB0 REGB Bus Cout OUTPUT Bus MSC MS1:0/ MSB1:0 [17%] 8 block diagram of your lab 6 is shown here, along with two tables from the same handout Use proper default values for MS, MSB, and MSC, as done in lab 6 Bus Selected as Input to Combinatorial Logic 00 INPUT Bus 01 REG Bus 10 REG B Bus 11 Output Bus ction 000 REG Bus to OUTPUT Bus 001 REGB Bus to OUTPUT Bus 010 complement of REG Bus to OUTPUT Bus 011 bit wise ND REG/REGB to OUTPUT Bus 100 bit wise OR REG/REGB Bus to OUTPUT Bus 101 sum of REG Bus & REGB Bus to OUTPUT Bus 110 shift REG Bus left one bit to OUTPUT Bus 111 shift REG Bus right one bit to OUTPUT Bus without sign extension (%) a) ssume that you can add small additional circuits to the circuit described with the above min block diagram The purpose of these additional circuits is first, to know when Reg (when representing a -bit 2's complement number) is negative (output is N ) and second, to know when =3 and B=7 (output is B 37 ) Design these two circuits Show LL your work ssume all signals are active-high

11 University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 11/11 Exam 2 (5%) 8 b) Multiply the number in Reg by 5 (Your algorithm should still work for any number min in Reg) Store the result in register Describe what is accomplished in each step Use the minimum number of clock cycles Give appropriate values for LL signals # MS MSB MSC Input Cin Reg RegB Output Cout Reg+ RegB+ Output+ Cout (8%) c) Use the table below to SUBTRCT $3 from $D (Your algorithm should still work even 5 min if the two numbers are changed) Store your solution in register Describe what is accomplished in each step Use the minimum number of clock cycles Give appropriate values for LL signals # MS MSB MSC Input Cin Reg RegB Output Cout Reg+ RegB+ Output+ Cout